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83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
s Direct Drive LED Outputs -- Four Pins (P3.7:4) -- 13 mA Typical Current Sink Capability s 20 pF Cap On-chip for RC Resonator -- Frequency Selectable (4-6 MHz) s 8 Dedicated Key Scan Input (KSI) Pins -- Schmitt-trigger Inputs -- External Interrupt -- Level Detect Interrupt Mode for Automatic Power-down Exit s 16 Dedicated Key Scan Output (KSO) Pins with Quasi-bidirectional Port Drivers -- No External Resistor Required -- Located on P0.7:0 and P2.7:0 s 4-Kbyte On-chip ROM Memory s 128-byte On-chip RAM Memory s Clock/Data Drivers to Motherboard -- Strong Pullup Drivers for Keyboard Cable Communication -- 8X42 Compatible Interface -- Selectable external interrupt for Clock s ONCE mode (On-chip Emulation) s Power-on Reset Mode -- Automatic Operation s 5 Volt D.C. Operation s Reduces Manufacturing Cost by Reducing Overall Component Count s Configurable Timer (16 bit or 2 by 8 Bit) s Uses Industry Standard Design Tools s Control Oriented Instruction Set s Industry Standard Architecture
The 83C51KB is a highly integrated keyboard microcontroller for the standard and advanced desktop keyboard industry. The integration of external components into the microcontroller reduces overall keyboard control system manufacturing cost in terms of the number of components used, the amount of PCB space required, reduced inventory, and a reduction in required assembly activities. In addition, the integration reduces the number and amount of software routines needed for signal debounce and input status poll operation. There is a resultant reduction in CPU overhead as well as on-chip memory requirements. The 83C51KB product line is manufactured with Intel state of the art complimentary high-performance metallic oxide semiconductor (CHMOS) design rules.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcontroller products may have minor variations to this specification known as errata. COPYRIGHT (c) INTEL CORPORATION, 1996 March 1996 Order Number: 272800-001
83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
KSO 0-7 P0.0 - P0.7
KSO 8-15 P2.0 - P2.7
VCC VSS
RAM Address Register
Port 0 Drivers
Port 0 Drivers
RAM
Port 0 Latch
Port 2 Latch
ROM
Program Address Register ACC Stack Pointer Buffer B Register TMP2 TMP1 PC Incrementer SFRs Timer
ALU
PSEN# ALE EA#
Timing and Control
Instruction Register
RST
Power On Reset Ctrl.
PSW
Program Counter
DPTR
VCC
Port 1 Latch
Port 3 Latch
RC Osc.
Port 1 Drivers
Port 3 Drivers
KSI 0-7 P1.0 - P1.7
CLK, Data, LED 0-3 P3.0 - P3.7
A3350-01
Figure 1. 83C51KB Block Diagram
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83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
1.0 TEMPERATURE RANGE
With the commercial (standard) temperature marking, this product line operates over the temperature range 0C to +70C.
All thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. Values change depending on operating conditions and application requirements. The Intel Packaging Handbook (order number 240800) describes Intel's thermal impedance test methodology. Table 1. Thermal Characteristics Package Type 40-lead PDIP JA 70C/W JC 25C/W
2.0 PROCESS INFORMATION
This device is manufactured on a complimentary high-performance metal-oxide semiconductor (CHMOS) process. Additional process and reliability information is available in Intel's Components Quality and Reliability Handbook (order number 210997).
3.0 83C51KB PACKAGE INFORMATION
X
Te
XX
Pa ck
8
X
Pr og
X
Pr oc
XXXXX
Pr od
XX
De
The 83C51KB Family Nomenclature
mp er
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m-
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atu re an
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nfo rm ati
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dB ur
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Op tio
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A2815-01
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83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
Table 2. 83C51KB Nomenclature Definitions Parameter Temperature and Burn-in Options Packaging Options Program Memory Options Process Information Product Family Device Memory Options Options no mark P 3 C 51 KB Description Commercial operating temperature range (0C to 70C) with Intel standard burn-in. Plastic Dual-in-line Package (PDIP) Factory programmed ROM CHMOS MCS 51 Compatible Product Family 128 bytes RAM 4 Kbytes ROM Device Speed no mark 4-6 MHz
P1.0/KSI0 P1.1/KSI1 P1.2/KSI2 P1.3/KSI3 P1.4/KSI4 P1.5/KSI5 P1.6/KSI6 P1.7/KSI7 RST P3.0/DATA P3.1 P3.2/CLK0/INT0# P3.3/CLK1/INT1# P3.4/LED0/T0 P3.5/LED1 P3.6/LED2/WR# P3.7/LED3/RD# NC RCIN VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28
VCC P0.0/KSO0/AD0 P0.1/KSO1/AD1 P0.2/KSO2/AD2 P0.3/KSO3/AD3 P0.4/KSO4/AD4 P0.5/KSO5/AD5 P0.6/KSO6/AD6 P0.7/KSO7/AD7 EA# ALE PSEN# P2.7/KSO15/A15 P2.6/KSO14/A14 P2.5/KSO13/A13 P2.4/KSO12/A12 P2.3/KSO11/A11 P2.2/KSO10/A10 P2.1/KSO9/A9 P2.0/KSO8/A8
P83C51KB
View of component as mounted on PC board
27 26 25 24 23 22 21
A4248-01
Figure 2. 83C51KB 40-pin DIP Diagram
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83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
4.0 83C51KB MEMORY
Table 3. 83C51KB Memory Map Code Memory FFFFH 0000H 0FFFH 0000H Description External code memory 4-Kbyte on-chip code memory array. Notes 4
Data Memory FFFFH 0000H 00FFH 0080H 007FH 0020H 001FH 0000H
Description External data memory Special function registers On-chip RAM 4 banks of general purpose registers, R0-R7 2, 3 1 5
NOTE: 1. The special function registers (SFRs) are accessible by direct addressing only. 2. Data in this area is accessible by indirect addressing only. 3. RD#/WR# active for these external data addresses. 4. PSEN# active for the external code addresses. 5. Addresses 20H through 2FH are bit addressable.
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83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
5.0 SIGNAL DESCRIPTION
Table 4. 40-pin DIP Signals Arranged by Name Keyboard Name P0.7/KSO7/AD7 P0.6/KSO6/AD6 P0.5/KSO5/AD5 P0.4/KSO4/AD4 P0.3/KSO3/AD3 P0.2/KSO2/AD2 P0.1/KSO1/AD1 P0.0/KSO0/AD0 P2.7/KSO15/A15 P2.6/KSO14/A14 P2.5/KSO13/A13 P2.4/KSO12/A12 P2.3/KSO11/A11 P2.2KSO10/A10 P2.1/KSO9/A9 P2.0/KSO8/A8 Pin 32 33 34 35 36 37 38 39 28 27 26 25 24 23 22 21 Name P 1.0/KSI0 P1.1/KSI1 P1.2/KSI2 P1.3/KSI3 P1.4/KSI4 P1.5/KSI5 P1.6/KSI6 P1.7/KSI7 P3.0/DATA P3.1 P3.2/CLK0/INT0# P3.3/CLK1/INT1# P3.4/LED0/T0 P3.5/LED1 P3.6/LED2/WR# P3.7/LED3/RD# Keyboard Pin 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17
Chip Control Name RCIN RST ALE PSEN# EA# Pin 19 9 30 29 31 Power & Ground Name VCC
VSS
Pin 40 20
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83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
Table 5. 40-pin DIP Signals Arranged by Pin Number Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name P 1.0/KSI0 P1.1/KSI1 P1.2/KSI2 P1.3/KSI3 P1.4/KSI4 P1.5/KSI5 P1.6/KSI6 P1.7/KSI7 RST P3.0/DATA P3.1 P3.2/CLK0/INT0# P3.3/CLK1/INT1# P3.4/LED0/T0 P3.5/LED1 P3.6/LED2/WR# P3.7/LED3/RD# NC RCIN
VSS
Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Name P2.0/KSO8/A8 P2.1/KSO9/A9 P2.2KSO10/A10 P2.3/KSO11/A11 P2.4/KSO12/A12 P2.5/KSO13/A13 P2.6/KSO14/A14 P2.7/KSO15/A15 PSEN# ALE EA# P0.7/KSO7/AD7 P0.6/KSO6/AD6 P0.5/KSO5/AD5 P0.4/KSO4/AD4 P0.3/KSO3/AD3 P0.2/KSO2/AD2 P0.1/KSO1/AD1 P0.0/KSO0/AD0 VCC
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83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
Table 6. 83C51KB Signal Description Signal Name A15:8 Type O Description Address Signals . Upper address lines for the external bus. These signals are normally used for the KSO15:8 scan function and are not available for external memory access in a keyboard application. (See KSO signals). Address/Data Signals. Multiplexed lower address and data signals for external memory. These signals are normally used for the KSO7:0 scan function and are not available for external memory access in a keyboard application. (See KSO) Address Latch Enable. ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A15:8 and AD7:0. Since these external address signals are normally used for the KSO scan function, the ALE should not be used for external memory access in a keyboard application. ALE can be disabled when not used for external memory access by setting bit 0 of SFR AUXR at address 8EH. Clock signal. Either P3.2 or P3.3 is configurable with a 1.8K pullup and with external interrupt INT0# or INT1# and used as keyboard CLK signal. DATA signal. P3.0 is configurable with a 1.8K pullup and used as keyboard Data signal.. External Access. Directs program memory accesses to on-chip or offchip code memory. For EA# = 0, all program memory accesses are offchip. EA# should always be strapped to VCC for keyboard applications using the 83C51KB. External Interrupts 0 and 1. These inputs set bits IE1:0 in the TCON register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by a falling edge on INT1#/INT0#. If bits INT1:0 are clear, bits IE1:0 are set by a low level on INT1:0#. For keyboard applicaitons, these signals are normally used for the CLK signals. (See KSIINT and CDPU bits in the PCON register) Keyboard Scan Inputs. Application specific keyboard signals. Keyboard Scan Outputs. The KSO signals are application specific to keyboard scan functions. Light Emitting Diode Drivers. The LED signals are specifically designed to drive LEDs connected to Vcc directly (see D.C. Characteristics). The alternate functions are not available for keyboard applications. No Connection Signal. This signal is to be unconnected. Port 0. This is an 8-bit quasi-bidirectional I/O port (see KSO signals, see also AD7:0). Port 1. This is an 8-bit quasi-bidirectional I/O port (see KSI signals). Port 2. This is an 8-bit quasi-bidirectional I/O port (see also A15:8). A15:8 AD7:0 RD#, WR#, T0 CLK1:0 P3.3:2 INT1:0# Alternate Function KSO.15:8 P2.15:8
AD7:0
I/O
KSO.7:0 P0.7:0
ALE
O
CLK1:0 P3.3:2 DATA P3.0 EA#
I/O
I/O I
INT1:0#
I
KSI7:0 P1.7:0 KSO15:0 P2.15:8 P0.7:0 LED3:0 P3.7:4 N/C P0.7:0 P1.7:0 P2.7:0
I/O I/O
I/O
-- I/O I/O I/O
The descriptions of RD#, WR#, ALE, P'SEN#, A15:8/P2.7:0 and AD7:0/P0.7:0 are documented for the standard MCS 51 microcontrollers. They are not used for these functions in keyboard applications.
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83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
Table 6. 83C51KB Signal Description Signal Name P3.7:0 PSEN# RCIN Type I/O O I Description Port 3. This is an 8-bit quasi-bidirectional I/O port (see CLK1:0, DATA, LED3:0). Program Store Enable. This output is asserted for external program memory fetch operations. It is not available for keyboard applications. Resonant Clock Input. RC resonator generated by connecting 1% precision resistor to VCC or provide an external clock input from an external clock device. Read . Read signal output for external data memory read operations. It is not available for keyboard applications. Reset. Asserting RST when the chip is in idle mode or powerdown mode returns the chip to normal operation. This signal is input only. When power is applied to the chip, the internal reset signal remains high for approximately 80ms to 260ms (see the datasheet for current specifications). The reset circuit then deactivates and does not reactivate unless VCC drops below the crossover at approximately 3VDC. Supply Voltage. Connect this pin to the +5V supply voltage. Circuit Ground. Connect this pin to ground. Write. Write signal output for external data memory write operations. It is not available for keyboard applications. LED3 -- -- Alternate Function
RD# RST
O I
VCC
VSS
PWR GND O
-- -- LED2
WR#
The descriptions of RD#, WR#, ALE, P'SEN#, A15:8/P2.7:0 and AD7:0/P0.7:0 are documented for the standard MCS 51 microcontrollers. They are not used for these functions in keyboard applications.
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83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
6.0 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature under Bias: Commercial ...................................... 0C to +70C Storage Temperature............................. -65C to +150C Voltage on Any Pin to VSS ...................... -0.5 V to +6.5 V IOL per I/O Pin..........................................................15 mA Power Dissipation ................................................... 1.5 W
NOTICE: This document contains information on products in the design phase of development. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
NOTE:
Maximum power dissipation is based on package heat-transfer limitations, not device power consumption.
OPERATING CONDITIONS
TA (Ambient Temperature Under Bias): Commercial ..................................... 0C to +70C VCC (Digital Supply Voltage) ..................... 4.5 V to 5.5 V VSS ............................................................................. 0 V
WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
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83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
RCIN Frequency vs. Resistance
7 6.5
6
RCIN Frequency (MHz)
5.5
5
4.5
4
3.5
3 5 6 7 8 9 10
Resistance (KOhm)
A4250-01
Figure 3. RCIN Frequency NOTE: RC resonator accuracy is 5% at fixed VCC and temperature using a 1% external precision resistor.
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83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
external VCC
internal
VCC
R RCin C 2/3 VCC
A
1/3 VCC B
A4245-01
Figure 4. RC Oscillator
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83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
6.1 D.C. Characteristics
Table 7. D.C. Characteristics Symbol VIL VIL1 VIL2 VIL3 VIH VIH1 VIH2 Parameter Input Low Voltage (except EA#, RCIN, RST) Input Low Voltage RST Input Low Voltage EA# Input Low Voltage RCIN Input High Voltage (except EA#, RCIN, RST) Input High Voltage (EA#, RST) Input High Voltage RCIN 0.2VCC+ 0.9 0.7VCC 2VCC/3 Min -0.5 0 -0.5 Typical (note 1) Max 0.2 VCC -0.1 0.2 VCC -0.3 0.5 VCC/3 VCC+0.5 VCC+0.5 Unit V V V V V V IIH = 8 mA when external clock source is used on RCIN 0.3 0.45 1.0 6 13 22 V IOL=200 A IOL=3.2 mA IOL=7.0 mA (note 2,3) VOL=3.0 V Test Condition
VOL
Output Low Voltage (Port 0, 1, 2, 3, ALE, PSEN# except P3.4/LED0, P3.5/LED1, P3.6/LED2, P3.7/LED3) Output Low Current (P3.4/LED0, P3.5/LED1, P3.6/LED2, P3.7/LED3 only) Output High Voltage (Port 0, 1, 2, 3, ALE, PSEN#, except P3.0, P3.2, P3.3)
IOL
mA
VOH
VCC-0.3 VCC-0.7 VCC-1.5
V
IOH= -25 A IOH= -65 A IOH= -100 A (note 4)
NOTE: 1. Typical values are obtained using VCC=5.0V, TA=25C and are not guaranteed. 2. Under steady state (non-transient) conditions, IOL must be externally limited as follow: Maximum IOL per Port Pin--Port 0, 1, 2, P3.1-P3.3: 10mA Maximum IOL per Port Pin--P3.4-P3.7: 22mA Maximum IOL per 8-bit port--Port 0-2: 15mA Ports 3: 95mA Maximum Total IOL for AllOutput Pins: 110mA If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 3. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4V to be superimposed on the low level outputs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where capacitive loading exceeds 100pF, the noise pulses on these signals may exceed 0.8V. It may be desirable to qualify signals with a Schmitt Trigger, or CMOS-level input logic. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 VCC specification when the address lines are stabilizing.
4.
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83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
Table 7. D.C. Characteristics (Continued) Symbol VOH1 Parameter Output High Voltage (P3.0, P3.2, P3.3 without 1.8K Ohm pullup) Output High Voltage (P3.0, P3.2, P3.3 with 1.8K Ohm pullup) Reset Pulldown Resistor Pull Up Resistance (P3.0, P3.2, P3.3 with 1.8K Ohm pullup) Pin Capacitance Logical 0 Input Current (Port 0, 1, 2, 3, except P3.0, P3.2, P3.3) Logical 0 Input Current (P3.0, P3.2, P3.3 without 1.8K Ohm pullup) Logical 0 Input Current (P3.0, P3.2, P3.2 with 1.8K Ohm pullup) Logical 1-to-0 Transiton Current (Port 0, 1, 2, 3) Logical 1-to-0 Transition Current (P3.0, P3.2 or P3.3 with 1.8K Ohm pullups) -1.5 Min VCC-0.3 VCC-0.7 VCC-1.5 VCC-0.3 VCC-0.7 VCC-1.5 40 1.2 1.8 225 2.9 Typical (note 1) Max Unit V Test Condition IOH= -8 A IOH= -25 A IOH= -50 A IOH= -0.15 mA IOH= -0.50 mA IOH= -1.0 mA
VOH2
V
RRST RCD
K Ohm K Ohm
CIO IIL
10 -50
pF A
@1MHz, 25C VIN=0.45V
IIL1
-250
A
VIN=0.45V
IIL2
-4.5
mA
VIN=0.45V
ITL ITL1
-650 -4.5
A mA
VIN=2.0V VIN = 2.0V
NOTE: 1. Typical values are obtained using VCC=5.0V, TA=25C and are not guaranteed. 2. Under steady state (non-transient) conditions, IOL must be externally limited as follow: Maximum IOL per Port Pin--Port 0, 1, 2, P3.1-P3.3: 10mA Maximum IOL per Port Pin--P3.4-P3.7: 22mA Maximum IOL per 8-bit port--Port 0-2: 15mA Ports 3: 95mA Maximum Total IOL for AllOutput Pins: 110mA If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 3. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4V to be superimposed on the low level outputs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where capacitive loading exceeds 100pF, the noise pulses on these signals may exceed 0.8V. It may be desirable to qualify signals with a Schmitt Trigger, or CMOS-level input logic. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 VCC specification when the address lines are stabilizing.
4.
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83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
Table 7. D.C. Characteristics (Continued) Symbol ICC Parameter Power Supply Current: Active Mode at 6MHz Idle Mode at 6MHz Power Down Mode Min Typical (note 1) 7 2 10 Max 12 5 50 Unit mA mA A Test Condition RST, EA# to VCC RST, EA# to VSS RST, EA# to VSS (RCIN pin to external resistor, all other pins are no connect)
VPOR
Power on reset crossover
2.4
3
3.6
V
NOTE: 1. Typical values are obtained using VCC=5.0V, TA=25C and are not guaranteed. 2. Under steady state (non-transient) conditions, IOL must be externally limited as follow: Maximum IOL per Port Pin--Port 0, 1, 2, P3.1-P3.3: 10mA Maximum IOL per Port Pin--P3.4-P3.7: 22mA Maximum IOL per 8-bit port--Port 0-2: 15mA Ports 3: 95mA Maximum Total IOL for AllOutput Pins: 110mA If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 3. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses above 0.4V to be superimposed on the low level outputs of ALE and Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins change from 1 to 0. In applications where capacitive loading exceeds 100pF, the noise pulses on these signals may exceed 0.8V. It may be desirable to qualify signals with a Schmitt Trigger, or CMOS-level input logic. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 VCC specification when the address lines are stabilizing.
4.
TCLCH
VCC - 0.5 0.7 VCC
TCHCX
TCLCX 0.45 V
0.2 VCC - 0.1
TCHCL
TCLCL
A4252-01
Figure 5. External Clock Drive
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83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
6.2 A.C. Characteristics
Table 8. A.C. Characteristics (Note 1, 2) Symbol FOSC TOSC TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH TPOR Parameter RCIN Frequency 1/Fosc ALE Pulse Width Address Valid to ALE Low Address Hold after ALE Low ALE Low to Valid Instruction In ALE Low to PSEN# Low Psen# Pulse Width Psen# Low to Valid Instruction In Input Instruction Hold after PSEN# Input Instruction Float after PSEN# Address Valid to Valid Instruction In Psen# Low to Address Float RD# Pulse Width Write# Pulse Width RD# Low to Valid Data In Input Data Hold after RD# High Input Data Float after RD# High ALE Low to Valid Data In Address Valid to Valid Data In ALE Low to RD# or WR# Low Address Valid to WR# Low Output Data Valid before WR# Output Data Valid to WR# High Output Data Hold after WR# High RD# Low to Address Float RD# or WR# High to ALE High Power on reset internal high time (note 3) Tosc - 55 80 3Tosc - 70 4Tosc - 150 Tosc - 70 7Tosc - 170 Tosc - 60 0 Tosc + 40 260 0 2Tosc - 45 8Tosc - 130 9Tosc - 145 3Tosc + 70 6Tosc - 120 6Tosc - 120 5Tosc - 150 0 Tosc - 20 5Tosc - 90 20 Tosc - 40 3Tosc - 60 3Tosc - 90 Min 4 166.7 2Tosc - 50 Tosc - 50 Tosc - 40 4Tosc - 80 Max 6 250 Unit MHz ns *ns *ns *ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
NOTE: 1. Capacitive loading=100pF 2. Rise time and fall time = 20ns for external clock drive 3. TPOR timing begins when the voltage exceeds the VPOR crossover voltage.
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83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
6.3 External Program Memory Read Cycle Waveform
TLHLL ALE TLLPL TAVLL PSEN# TLLAX PORT 0 A0 - A7 TAVIV PORT 2 A8 - A15 A8 - A15
A4254-01
TPLPH TLLIV TPLIV TPLAZ TPXIX Instruction In TPXIZ A0 - A7
6.4
External Program Memory Read Cycle
External Data Memory Read Cycle Waveform
ALE TLHLL PSEN# TLLDV TLLWL RD# TAVLL PORT 0 TLLAX TRLDV TRLAZ TRHDX Data In A0 - A7 from PCL Instr. In TRHDZ TRLRH TWHLH
A0-A7 from RI or DPL TAVWL TAVDV
PORT 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
A4255-01
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83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
6.5
External Data Memory Read Cycle
External Data Memory Write Cycle Waveform
ALE TLHLL PSEN# TLLWL WR# TAVLL TLLAX PORT 0 A0-A7 from RI or DPL TAVWL PORT 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH A4256-01 TRLWH TWHLH
TQVWX TQVWH Data Out
TWHQX A0 - A7 from PCL Instr. In
Figure 6. External Data Memory Write Cycle
6.6 Testing Characteristics
VLOAD + 0.1 V VLOAD VLOAD - 0.1 V Timing Reference Points
VOH - 0.1 V
VOL + 0.1 V
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading VOH/VOL level occurs with IOL/IOH = 20 mA.
A4243-01
Figure 7. Float Waveforms
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83C51KB HIGH PERFORMANCE KEYBOARD MICROCONTROLLER
Inputs VCC - 0.5
0.45 V
Outputs 0.2 VCC + 0.9 0.2 VCC - 0.1 VIH MIN VOL MAX
AC inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45 V for a logic 0. Timing measurements are made at a min of VIH for a logic 1 and VOL for a logic 0.
A4244-01
6.7
A.C. Testing Input, Output Waveforms
Signature Byte Information
Valid signature bytes for the 83C51KB are detailed in the following table: Table 9. 83C51KB Signature Byte Values TROM Address 30H 31H 60H Contents 89H 58H 20H Device Type Intel Corp. FX-core 83C51KB
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