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FEATURES 256 Position 10 k , 100 k , 1 M Low Tempco 30 ppm/ C Internal Power ON Midscale Preset Single Supply 2.7 V to 5.5 V or Dual Supply 2.7 V for AC or Bipolar Operation I2C-Compatible Interface with Reaback Capability Extra Programmable Logic Outputs APPLICATIONS Multimedia, Video and Audio Communications Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage-to-Current Conversion Line Impedance Matching GENERAL DESCRIPTION
I2C(R)-Compatible 256-Position Digital Potentiometers AD5241/AD5242
FUNCTIONAL BLOCK DIAGRAM
A1 W1 B1 O1 O2 SHDN VDD VSS ADDR DECODE
AD5241
RDAC REGISTER 1
REGISTER 2
8
SDA SCL GND
SERIAL INPUT REGISTER
PWR-ON RESET
AD0
AD1
A1
W1 B1
A2
W2 B2
O1
O2
The AD5241/AD5242 provides a single-/dual-channel, 256position digitally controlled variable resistor (VR) device. These devices perform the same electronic adjustment function as a potentiometer, trimmer or variable resistor. Each VR offers a completely programmable value of resistance, between the A terminal and the wiper, or the B terminal and the wiper. For AD5242, the fixed A-to-B terminal resistance of 10 k, 100 k or 1 M has a 1% channel-to-channel matching tolerance. Nominal temperature coefficient of both parts is 30 ppm/C. Wiper position programming defaults to midscale at system power ON. Once powered, the VR wiper position is programmed by an I2C-compatible 2-wire serial data interface. Both parts have available two extra programmable logic outputs that enable users to drive digital loads, logic gates, LED drivers, and analog switches in their system. The AD5241/AD5242 is available in surface-mount (SO-14/-16) packages and, for ultracompact solutions, TSSOP-14/-16 packages. All parts are guaranteed to operate over the extended industrial temperature range of -40C to +85C. For 3-wire, SPI-compatible interface applications, please refer to AD5200, AD5201, AD5203, AD5204, AD5206, AD5231* AD5232* , , AD5235* AD7376, AD8400, AD8402, and AD8403 products. ,
SHDN VDD VSS ADDR DECODE
REGISTER
RDAC REGISTER 1
RDAC REGISTER 2
AD5242
1 SDA SCL GND
8 PWR-ON RESET
SERIAL INPUT REGISTER
AD0
AD1
*Nonvolatile digital potentiometer. I2C is a registered trademark of Philips Corporation.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
AD5241/AD5242-SPECIFICATIONS
10 k , 100 k , 1 M
Parameter
VERSION
Symbol
(VDD = 3 V 10% or 5 V otherwise noted.)
Conditions
10%, VA = +VDD, VB = 0 V, -40 C < TA < +85 C unless
Min -1 -2 -30 -30 Typ1 0.4 0.5 Max +1 +2 +30 +50 120 Unit LSB LSB % % ppm/C Bits LSB LSB ppm/C LSB LSB V pF pF nA V V V V V V A pF V V V V A pF V V A A W %/% kHz kHz kHz % s nVHz
DC CHARACTERISTICS, RHEOSTAT MODE (Specifications apply to all VRs.) Resistor Differential Nonlinearity 2 R-DNL RWB, VA = NC Resistor Integral Nonlinearity2 R-INL RWB, VA = NC Nominal Resistor Tolerance R TA = 25C, RAB = 10 k R TA = 25C, RAB = 100 k/1 M Resistance Temperature Coefficient RAB/T VAB = VDD, Wiper = No Connect Wiper Resistance RW IW = VDD /R, VDD = 3 V or 5 V DC CHARACTERISTICS, POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.) Resolution N Differential Nonlinearity3 DNL Integral Nonlinearity3 INL Voltage Divider Temperature Coefficient VW/T Code = 80H Full-Scale Error VWFSE Code = FFH Zero-Scale Error VWZSE Code = 00H RESISTOR TERMINALS Voltage Range4 Capacitance5 A, B Capacitance5 W Common-Mode Leakage DIGITAL INPUTS Input Logic High (SDA and SCL) Input Logic Low (SDA and SCL) Input Logic High (AD0 and AD1) Input Logic Low (AD0 and AD1) Input Logic High Input Logic Low Input Current Input Capacitance5 DIGITAL OUTPUT Output Logic Low (SDA) Output Logic Low (O1 and O2) Output Logic High (O1 and O2) Three-State Leakage Current (SDA) Output Capacitance5 POWER SUPPLIES Power Single-Supply Range Power Dual-Supply Range Positive Supply Current Negative Supply Current Power Dissipation6 Power Supply Sensitivity DYNAMIC CHARACTERISTICS5, 7, 8 Bandwidth -3 dB VA, B, W CA, B CW ICM VIH VIL VIH VIL VIH VIL IIL CIL VOL VOL VOL VOH IOZ COZ VDD RANGE VDD/SS RANGE IDD ISS PDISS PSS BW_10 k BW_100 k BW_1 M THDW tS eN_WB
30 60 8 -1 -2 -1 0 VSS
0.4 0.5 5 -0.5 0.5
+1 +2 0 1 VDD
f = 1 MHz, Measured to GND, Code = 80H f = 1 MHz, Measured to GND, Code = 80H VA = VB = VW 0.7 VDD -0.5 2.4 0 2.1 0
45 60 1 VDD + 0.5 +0.3 VDD VDD 0.8 VDD 0.6 1 3 0.4 0.6 0.4 4 3 1 8
VDD = 5 V VDD = 5 V VDD = 3 V VDD = 3 V VIN = 0 V or 5 V IOL = 3 mA IOL = 6 mA ISINK = 1.6 mA ISOURCE = 40 A VIN = 0 V or 5 V
VSS = 0 V VIH = 5 V or VIL = 0 V VSS = -2.5 V, VDD = +2.5 V VIH = 5 V or VIL = 0 V, VDD = 5 V
2.7 2.3
-0.01 RAB = 10 k, Code = 80H RAB = 100 k, Code = 80H RAB = 1 M, Code = 80H VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz VA = VDD, VB = 0 V, 1 LSB Error Band, RAB = 10 k RWB = 5 k, f = 1 kHz
5.5 2.7 0.1 50 +0.1 -50 0.5 250 +0.002 +0.01 650 69 6 0.005 2 14
Total Harmonic Distortion VW Settling Time Resistor Noise Voltage
-2-
REV. A
AD5241/AD5242
Parameter Symbol Conditions
5, 9
Min 0 1.3 600 1.3 0.6 600 100
Typ1
Max 400
Unit kHz s ns s s ns ns ns ns ns
INTERFACE TIMING CHARACTERISTICS (Applies to all parts. ) SCL Clock Frequency fSCL tBUF Bus Free Time Between t1 STOP and START tHD; STA Hold Time (Repeated START) t2 After this period the first clock pulse is generated. tLOW Low Period of SCL Clock t3 tHIGH High Period of SCL Clock t4 tSU; STA Setup Time for START Condition t5 t6 tHD; DAT Data Hold Time tSU; DAT Data Setup Time t7 tR Rise Time of Both t8 SDA and SCL Signals tF Fall Time of Both SDA and SCL Signals t9 tSU; STO Setup Time for STOP Condition t10
50 900 300 300
NOTES 1 Typicals represent average readings at 25C, VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 10 test circuit. 3 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 9 test circuit. 4 Resistor terminals A, B, W have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test. 6 PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. 7 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 8 All dynamic characteristics use V DD = 5 V. 9 See timing diagram for location of measured values. Specifications subject to change without notice.
REV. A
-3-
AD5241/AD5242
ABSOLUTE MAXIMUM RATINGS*
(TA = 25C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 , +7 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V , -7 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD AX-BX, AX-WX, BX-WX at 10 k in TSSOP-14 . . . 5.0 mA* AX-BX, AX-WX, BX-WX at 100 k in TSSOP-14 . . 1.5 mA* AX-BX, AX-WX, BX-WX at 1 M in TSSOP-14 . . . 0.5 mA* Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . 0 V, 7 V Operating Temperature Range . . . . . . . . . . . -40C to +85C
Thermal Resistance JA SOIC (SO-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . 158C/W SOIC (SO-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206C/W TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180C/W Maximum Junction Temperature (TJ max) . . . . . . . . . . 150C Package Power Dissipation PD = (TJ max - TA)/JA Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperatures R-14, R-16, RU-14, RU-16 (Vapor Phase, 60 sec) . . 215C R-14, R-16, RU-14, RU-16 (Infrared, 15 sec) . . . . . . 220C
*Max Current increases at lower resistance and different packages.
ORDERING GUIDE
Model AD5241BR10 AD5241BR10-REEL7 AD5241BRU10-REEL7 AD5241BR100 AD5241BR100-REEL7 AD5241BRU100-REEL7 AD5241BR1M AD5241BR1M-REEL7 AD5241BRU1M-REEL7 AD5242BR10 AD5242BR10-REEL7 AD5242BRU10-REEL7 AD5242BR100 AD5242BR100-REEL7 AD5242BRU100-REEL7 AD5242BR1M AD5242BR1M-REEL7 AD5242BRU1M-REEL7
Number of Channels 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2
End to End RAB ( ) 10 k 10 k 10 k 100 k 100 k 100 k 1M 1M 1M 10 k 10 k 10 k 100 k 100 k 100 k 1M 1M 1M
Temperature Range ( C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85
Package Description SO-14 SO-14 TSSOP-14 SO-14 SO-14 TSSOP-14 SO-14 SO-14 TSSOP-14 SO-16 SO-16 TSSOP-16 SO-16 SO-16 TSSOP-16 SO-16 SO-16 TSSOP-16
Package Option R-14 R-14 RU-14 R-14 R-14 RU-14 R-14 R-14 RU-14 R-16A R-16A RU-16 R-16A R-16A RU-16 R-16A R-16A RU-16
#Devices per Container 56 1000 1000 56 1000 1000 56 1000 1000 48 1000 1000 48 1000 1000 48 1000 1000
NOTES 1. The AD5241/AD5242 die size is 69 mil x 78 mil, 5,382 sq. mil. Contains 386 transistors for each channel. Patent Number 5495245 applies. 2. TSSOP packaged units are only available in 1,000-piece quantity Tape and Reel.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5241/AD5242 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. A
AD5241/AD5242
AD5241 PIN CONFIGURATION AD5242 PIN CONFIGURATION
A1 1 W1 2 B1 3 VDD 4 SHDN 5 SCL 6 SDA 7
14 13 12
O1 NC O2 VSS DGND AD1 AD0
O1 1 A1 2 W1 3 B1 4
16 A2 15 W2 14 B2
AD5241
TOP VIEW (Not to Scale)
11 10 9 8
13 O2 TOP VIEW VDD 5 (Not to Scale) 12 VSS
AD5242
SHDN 6 SCL 7 SDA 8
11 DGND 10 AD1 9
NC = NO CONNECT
AD0
AD5241 PIN FUNCTION DESCRIPTIONS
AD5242 PIN FUNCTION DESCRIPTIONS
Pin 1 2 3 4 5
Mnemonic A1 W1 B1 VDD SHDN
Description Resistor Terminal A1 Wiper Terminal W1 Resistor Terminal B1 Positive power supply, specified for operation from 2.2 V to 5.5 V. Active low, asynchronous connection of the Wiper W to Terminal B, and open circuit of Terminal A. RDAC register contents unchanged. SHDN should tie to VDD if not used. Serial Clock Input Serial Data Input/Output Programmable address bit for multiple package decoding. Bits AD0 and AD1 provide four possible addresses. Programmable address bit for multiple package decoding. Bits AD0 and AD1 provide four possible addresses. Common Ground Negative power supply, specified for operation from 0 V to -2.7 V. Logic Output Terminal O2 No Connect Logic Output Terminal O1
Pin 1 2 3 4 5 6
Mnemonic O1 A1 W1 B1 VDD SHDN
Description Logic Output Terminal O1 Resistor Terminal A1 Wiper Terminal W1 Resistor Terminal B1 Positive power supply, specified for operation from 2.2 V to 5.5 V. Active low, asynchronous connection of the Wiper W to Terminal B, and open circuit of Terminal A. RDAC register contents unchanged. SHDN should tie to VDD if not used. Serial Clock Input Serial Data Input/Output Programmable address bit for multiple package decoding. Bits AD0 and AD1 provide four possible addresses. Programmable address bit for multiple package decoding. Bits AD0 and AD1 provide four possible addresses. Common Ground Negative power supply, specified for operation from 0 V to -2.7 V. Logic Output Terminal O2 Resistor Terminal B2 Wiper Terminal W2 Resistor Terminal A2
6 7 8
SCL SDA AD0
7 8 9
SCL SDA AD0
9
AD1
10
AD1
10 11 12 13 14
DGND VSS O2 NC O1
11 12 13 14 15 16
DGND VSS O2 B2 W2 A2
REV. A
-5-
AD5241/AD5242
t8 SDA t1 t8 SCL t2
P S
t9
t2
t4 t3 t6
t7
S
t5
P
t 10
Figure 1. Detail Timing Diagram
Data of AD5241/AD5242 is accepted from the I2C bus in the following serial format:
S 0 1 0 1 1 AD1 AD0 R/W A A/B RS SD O1 O2 X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
DATA BYTE
where: S = Start Condition P = Stop Condition A = Acknowledge X = Don't Care AD1, AD0 = Package pin programmable address bits. Must be matched with the logic states at pins AD1 and AD0. R/W = Read Enable at High and output to SDA. Write Enable at Low. A/B = RDAC sub address select. `0' for RDAC1 and `1' for RDAC2. RS = Midscale reset, active high. SD = Shutdown in active high. Same as SHDN except inverse logic. O1, O2 = Output logic pin latched values. D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits.
1
9
1
9
1
9
SCL SDA
0 1 0 1 1 AD1 AD0 R/W A/B RS SD O1 O2 X X X D7 D6 D5 D4 D3 D2 D1 D0
ACK BY AD5241 START BY MASTER FRAME 1 SLAVE ADDRESS BYTE FRAME 2 INSTRUCTION BYTE
ACK BY AD5241 FRAME 3 DATA BYTE
ACK BY AD5241 STOP BY MASTER
Figure 2. Writing to the RDAC Serial Register
1
9
1
9
SCL SDA
0 1 0 1 1 AD1 AD0 R/W D7 D6 D5 D4 D3 D2 D1 D0
ACK BY AD5241 START BY MASTER FRAME 1 SLAVE ADDRESS BYTE
NO ACK BY MASTER STOP BY FRAME 2 MASTER DATA BYTE FROM PREVIOUSLY SELECTED RDAC REGISTER IN WRITE MODE
Figure 3. Reading Data from a Previously Selected RDAC Register in Write Mode
-6-
REV. A
Typical Performance Characteristics-AD5241/AD5242
1 VDD = 2.7V VDD = 5.5V VDD = 2.7V 0.5 VDD /VSS = 2.7V/0V 0
0.50 VDD = 2.7V VDD = 5.5V VDD = 2.7V 0.25 VDD /VSS = 0.00 VDD /VSS = 2.7V/0V, 5.5V/0V 2.7V
RHEOSTAT MODE DIFFERENTIAL NONLINEARITY - LSB
-0.5 VDD /VSS = 5.5V/0V, 2.7V
POTENTIOMETER MODE INTEGRAL NONLINEARITY - LSB
256
-0.25
-1 0 32 64 96 128 160 CODE - Decimal 192 224
-0.50 0 32 64 96 128 160 192 224 256 CODE - Decimal
TPC 1. RDNL vs. Code
TPC 4. INL vs. Code
1 VDD = 2.7V VDD = 5.5V VDD = 2.7V
10000 VDD = 2.7V TA = 25 C 1M
NOMINAL RESISTANCE - k
RHEOSTAT MODE INTEGRAL NONLINEARITY - LSB
VDD /VSS = 2.7V/0V 0.5
1000
100k 100
0
VDD /VSS = 5.5V/0V, -0.5
2.7V
10k 10
-1 0 32 64 96 128 160 192 224 256 CODE - Decimal
1 -40
-20
0
20 40 TEMPERATURE - C
60
80
TPC 2. RINL vs. Code
TPC 5. Nominal Resistance vs. Temperature
0.25
10000
VDD = 2.7V VDD = 5.5V VDD = 2.7V
POTENTIOMETER MODE DIFFERENTIAL NONLINEARITY - LSB
VDD /VSS = 2.7V/0V, 5.5V/0V,
2.7V
IDD - SUPPLY CURRENT -
0.13
1000
VDD = 5V
A
0.00
100
VDD = 3V
-0.13
10 VDD = 2.5V
-0.25 0 32 64 96 128 160 192 224 256 CODE - Decimal
1 0 1 2 3 INPUT LOGIC VOLTAGE - V 4 5
TPC 3. DNL vs. Code
TPC 6. Supply Current vs. Logic Input Voltage
REV. A
-7-
AD5241/AD5242
0.1 RAB = 10k VDD = 5.5V
100 TA = 25 C 90 80
SHUTDOWN CURRENT - A
WIPER RESISTANCE -
VDD /VSS = 2.7V/0V 70 60 50 VDD /VSS = 40 30 VDD /VSS = 5.5V/0V 20 2.7V/0V
0.01
0.001 -40
-20
0
20
40
60
80
10 -3
-2
-1
0
1
2
3
4
5
6
TEMPERATURE - C
COMMON MODE - Volts
TPC 7. Shutdown Current vs. Temperature
TPC 10. Incremental Wiper Contact vs. VDD/VSS
70
POTENTIOMETER MODE TEMPCO - ppm/ C
300
60 10M 50 10k 40 100k 30 20 10 0 -10 VERSION VERSION VERSION
VDD /VSS = 2.7V/0V TA = 25 C
A
250
IDD - SUPPLY CURRENT
A - VDD /VS S = 5.5V/0V CODE = FF B - VDD /VSS = 3.3V/0V CODE = FF
D
200
A
C - VDD /VSS = 2.5V/0V CODE = FF D - VDD /VSS = 5.5V/0V CODE = 55 E - VDD /VSS = 3.3V/0V CODE = 55 F - VDD /VSS = 2.5V/0V CODE = 55 E B F C
150
100
50
-20 -30 0 16 32 48 64 80 96 112 128 CODE - Decimal
0 10
100 FREQUENCY - kHz
1000
TPC 8.
VWB/ T Potentiometer Mode Tempco
TPC 11. Supply Current vs. Frequency
120
6
VDD /VSS = 2.7V/0V TA = 25 C
RHEOSTAT MODE TEMPCO - ppm/ C
100 100k 80 60 VERSION
0 -6 -12
GAIN - dB
FFH 80H 40H 20H 10H 08H
40 20 0 -20 10k -40 10M -60 -80 0 16 32 48 64 80 96 112 128 CODE - Decimal VERSION VERSION
-18 -24 -30
04H -36 -42 -48 -54 100 1k 10k FREQUENCY - Hz 100k 1M 02H 01H
TPC 9.
RWB/ T Rheostat Mode Tempco
TPC 12. AD5242 10 k Gain vs. Frequency vs. Code
-8-
REV. A
AD5241/AD5242
6 0 -6 -12 FFH 80H 40H 20H 10H 08H 04H 02H -42 01H -48 -54 100 1k 10k FREQUENCY - Hz 100k -48 -54 100 1k 6 0 -6 -12 FFH 80H 40H 20H 10H 08H 04H 02H 01H
GAIN - dB
-24 -30 -36 -42
GAIN - dB
-18
-18 -24 -30 -36
10k FREQUENCY - Hz
100k
TPC 13. AD5242 100 k Gain vs. Frequency vs. Code
TPC 14. AD5242 1 M Gain vs. Frequency vs. Code
OPERATION
The AD5241/AD5242 provides a single-/dual-channel, 256position digitally controlled variable resistor (VR) device. The terms VR, RDAC, and programmable resistor are commonly used interchangeably to refer to digital potentiometer. To program the VR settings, refer to the Digital Interface section. Both parts have an internal power ON preset that places the wiper in midscale during power-on, which simplifies the fault condition recovery at power-up. In addition, the shutdown SHDN pin of AD5241/AD5242 places the RDAC in an almost zero power consumption state where Terminal A is open circuited and the Wiper W is connected to Terminal B, resulting in only leakage current being consumed in the VR structure. During shutdown, the VR latch contents are maintained when the RDAC is inactive. When the part is returned from shutdown, the stored VR setting will be applied to the RDAC.
A SHDN SWSHDN D7 D6 D5 D4 D3 D2 D1 D0 R
N SW 2-1
PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation
The nominal resistance of the RDAC between Terminals A and B are available in 10 k, 100 k, and 1 M. The final two or three digits of the part number determine the nominal resistance value, e.g. 10 k = 10; 100 k = 100; 1 M = 1 M. The nominal resistance (RAB) of the VR has 256 contact points accessed by the wiper terminal, plus the B terminal contact. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings. Assume a 10 k part is used; the wiper's first connection starts at the B terminal for data 00H. Since there is a 60 wiper contact resistance, such connection yields a minimum of 60 resistance between terminals W and B. The second connection is the first tap point corresponds to 99 (RWB = RAB /256 + RW = 39 + 60) for data 01H. The third connection is the next tap point representing 138 (39 x 2 + 60) for data 02H and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10021 [RAB - 1 LSB + RW]. Figure 4 shows a simplified diagram of the equivalent RDAC circuit where the last resistor string will not be accessed; therefore, there is 1 LSB less of the nominal resistance at full scale in addition to the wiper resistance. The general equation determining the digitally programmed resistance between W and B is:
R
N SW 2-2
W R RDAC LATCH & DECODER SW1 R R SW0 RAB /2N
RWB ( D ) = D x R AB + RW 256 where: D
(1)
is the decimal equivalent of the binary code between 0 and 255 which is loaded in the 8-bit RDAC register.
B
DIGITAL CIRCUITRY OMITTED FOR CLARITY
RAB is the nominal end-to-end resistance. RW is the wiper resistance contributed by the on-resistance of the internal switch. Again, if RAB = 10 k and A terminal can be either open circuit or tied to W, the following output resistance at RWB will be set for the following RDAC latch codes.
Figure 4. AD5241/AD5242 Equivalent RDAC Circuit
REV. A
-9-
AD5241/AD5242
D (DEC) 255 128 1 0 RWB () 10021 5060 99 60 which can be simplified to Output State Full-Scale (RWB - 1 LSB + RW) Midscale 1 LSB Zero-Scale (Wiper Contact Resistance) VW (D) = D VAB + VB 256 (4)
where D is decimal equivalent of the binary code between 0 to 255 which is loaded in the 8-bit RDAC register. For more accurate calculation including the effects of wiper resistance, VW can be found as:
VW ( )= D RWB ( ) D RWA ( ) D VA + VB RAB RAB
Note that in the zero-scale condition a finite wiper resistance of 60 is present. Care should be taken to limit the current flow between W and B in this state to a maximum current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur. Similar to the mechanical potentiometer, the resistance of the RDAC between the Wiper W and Terminal A also produces a digitally controlled resistance RWA. When these terminals are used, the B terminal can be opened or tied to the wiper terminal. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is: RWA ( D ) = 256 - D x R AB + RW 256 (2)
(5)
where RWB(D) and RWA(D) can be obtained from Equations 1 and 2. Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent on the ratio of the internal resistors RWA, RWB, and not the absolute values; therefore, the temperature drift reduces to 5 ppm/C.
DIGITAL INTERFACE 2-Wire Serial Bus
For RAB = 10 k and B terminal can be either open circuit or tied to W. The following output resistance RWA will be set for the following RDAC latch codes. D (DEC) 255 128 1 0 RWA () 99 5060 10021 10060 Output State Full-Scale Midscale 1 LSB Zero-Scale
The AD5241/AD5242 are controlled via an I2C-compatible serial bus. The RDACs are connected to this bus as slave devices. Referring to Figures 2 and 3, the first byte of AD5241/AD5242 is a Slave Address Byte. It has a 7-bit slave address and a R/W bit. The 5 MSBs are 01011 and the following two bits are determined by the state of the AD0 and AD1 pins of the device. AD0 and AD1 allow users to use up to four of these devices on one bus. The 2-wire I2C serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, which is when a high-to-low transition on the SDA line occurs while SCL is high, Figure 2. The following byte is the Slave Address Byte, Frame 1, which consists of the 7-bit slave address followed by an R/W bit (this bit determines whether data will be read from or written to the slave device). The slave whose address corresponds to the transmitted address will respond by pulling the SDA line low during the ninth clock pulse (this is termed the Acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is high, the master will read from the slave device. If the R/W bit is low, the master will write to the slave device. 2. A Write operation contains an extra Instruction Byte more than the Read operation. Such Instruction Byte, Frame 2, in Write mode follows the Slave Address Byte. The MSB of the Instruction Byte labeled A/B is the RDAC subaddress select. A "low" selects RDAC1 and a "high" selects RDAC2 for the dual-channel AD5242. Set A/B to low for AD5241. The second MSB, RS, is the Midscale reset. A logic high of this bit moves the wiper of a selected RDAC to the center tap where RWA = RWB. The third MSB, SD, is a shutdown bit. A logic high on SD causes the RDAC open circuit at Terminal A while shorting wiper to Terminal B. This operation yields almost a 0 in rheostat mode or zero volt in potentiometer mode. This SD bit serves the same function as the SHDN pin except SHDN pin reacts to active low. The following two REV. A
The typical distribution of the nominal resistance RAB from channel-to-channel matches within 1% for AD5242. Deviceto-device matching is process lot dependent and it is possible to have 30% variation. Since the resistance element is processed in thin film technology, the change in RAB with temperature has no more than 30 ppm/C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation
The digital potentiometer easily generates output voltages at wiper-to-B and wiper-to-A to be proportional to the input voltage at A-to-B. Unlike the polarity of VDD - VSS, which must be positive, voltage across A-B, W-A, and W-B can be at either polarity provided that VSS is powered by a negative supply. If ignoring the effect of the wiper resistance for approximation, connecting A terminal to 5 V and B terminal to ground produces an output voltage at the wiper-to-B starting at zero volt up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across Terminal AB divided by the 256 position of the potentiometer divider. Since AD5241/AD5242 can be supplied by dual supplies, the general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to Terminals A and B is: VW (D) = D 256 - D VA + VB 256 256 (3)
-10-
AD5241/AD5242
bits are O2 and O1. They are extra programmable logic output that users can use to drive other digital loads, logic gates, LED drivers, and analog switches, etc. The three LSBs are DON'T CARE. See Figure 2. 3. After acknowledging the Instruction Byte, the last byte in Write mode is the Data Byte, Frame 3. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an "Acknowledge" bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL, Figure 2. 4. Unlike the Write mode, the Data Byte follows immediately after the acknowledgment of the Slave Address Byte in the Read mode, Frame 2. Data is transmitted over the serial bus in sequences of nine clock pulses (slight difference with the Write mode, there are eight data bits followed by a "No Acknowledge" bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL, Figure 3. 5. When all data bits have been read or written, a STOP condition is established by the master. A STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. In Write mode, the master will pull the SDA line high during the tenth clock pulse to establish a STOP condition (see Figure 2). In Read mode, the master will issue a No Acknowledge for the ninth clock pulse (i.e., the SDA line remains high). The master will then bring the SDA line low before the tenth clock pulse which goes high to establish a STOP condition (see Figure 3). A repeated Write function gives the user flexibility to update the RDAC output a number of times after addressing and instructing the part only once. During the Write cycle, each Data byte will update the RDAC output. For example, after the RDAC has acknowledged its Slave Address and Instruction Bytes, the RDAC output will be updated. If another byte is written to the RDAC while it is still addressed to a specific slave device with the same instruction, this byte will update the output of the selected slave device. If different instructions are needed, the Write mode has to start a whole new sequence with a new Slave Address, Instruction, and Data Bytes transferred again. Similarly, a repeated Read function of the RDAC is also allowed.
MULTIPLE DEVICES ON ONE BUS LEVEL-SHIFT FOR BIDIRECTIONAL INTERFACE
While most old systems may be operated at one voltage, a new component may be optimized at another. When they operate the same signal at two different voltages, a proper method of levelshifting is needed. For instance, one can use a 3.3 V E2PROM to interface with a 5 V digital potentiometer. A level-shift scheme is needed in order to enable a bidirectional communication so that the setting of the digital potentiometer can be stored to and retrieved from the E2PROM. Figure 6 shows one of the techniques. M1 and M2 can be N-Ch FETs 2N7002 or low threshold FDV301N if VDD falls below 2.5 V.
VDD2 = 3.3V RP SDA1 M1 S SCL1 3.3V E2PROM M2 5V RP S G D G D SCL2 SDA2 RP RP VDD2 = 5V
AD5242
Figure 6. Level-Shift for Different Voltage Devices Operation
VDD MP 1 2
IN
O1
O1 DATA IN FRAME 2 OF WRITE MODE
MN VSS
Figure 7. Output Stage of Logic Output O1
READBACK RDAC VALUE
Figure 5 shows four AD5242 devices on the same serial bus. Each has a different slave address since the state of their AD0 and AD1 pins are different. This allows each RDAC within each device to be written to or read from independently. The master device output bus line drivers are open-drain pull-downs in a fully I2C-compatible interface. Note, a device will be addressed properly only if the bit information of AD0 and AD1 in the Slave Address Byte matches with the logic inputs at pins AD0 and AD1 of that particular device.
5V RP MASTER SDA SCL AD1 AD0 VDD SDA SCL AD1 AD0 VDD SDA SCL AD1 AD0 VDD SDA SCL AD1 AD0 RP SDA SCL
AD5241/AD5242 allows user to read back the RDAC values in Read Mode. However, for AD5242 dual channel device, the channel of interest is the one that is previously selected in Write Mode. In the case that users need to read the RDAC values of both channels in AD5242, they can program the first subaddress in the Write Mode and then change to the Read Mode to read the first channel value. After that, they can change back to the Write Mode with the second subaddress and finally read the second channel value in the Read Mode again. Note that it is not necessary for users to issue the Frame 3 Data Byte in the Write Mode for subsequent readback operation. Users should refer to Figures 2 and 3 for the programming format.
ADDITIONAL PROGRAMMABLE LOGIC OUTPUT
AD5241/AD5242 features additional programmable logic outputs, O1 and O2, which can be used to drive digital load, analog switches, and logic gates. The logic states of O1 and O2 can be programmed in Frame 2 of the Write Mode (see Figure 2). Figure 7 shows the output stage O1 where the logic levels are equal to the supply levels and the current driving capability reaches tenths of mA. All digital inputs are protected with a series input resistor and parallel Zener ESD structures shown in Figure 8. This applies to digital input pins SDA, SCL, and SHDN.
AD5242
AD5242
AD5242
AD5242
Figure 5. Multiple AD5242 Devices on One Bus
REV. A
-11-
AD5241/AD5242
340 LOGIC
A,B,W VSS
VSS
Figure 8. ESD Protection of Digital Pins
Figure 9. ESD Protection of Resistor Terminals
Test Circuits
Test Circuits 1 to 9 define the test conditions used in the product specification table.
DUT A V B W VMS V+ = VDD 1LSB = V+/2N
5V
OP279 VIN OFFSET GND W A DUT B
VOUT
OFFSET BIAS
Test Circuit 1. Potentiometer Divider Nonlinearity Error (INL, DNL)
NO CONNECT DUT A B VMS IW W
Test Circuit 6. Noninverting Gain
A +15V W VIN OFFSET GND 2.5V DUT OP42 B -15V VOUT
Test Circuit 2. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
Test Circuit 7. Gain vs. Frequency
RSW = 0.1V ISW
H
DUT
DUT A VMS2 B VMS1 RW = [VMS1 - VMS2]/I W W VW I W = VDD /RNOMINAL
CODE = W B ISW VSS TO VDD
0.1V
Test Circuit 3. Wiper Resistance
VA V+ = VDD 10% VDD V+ B PSRR (dB) = 20 LOG A W PSS (%/%) = VMS VMS% VDD%
Test Circuit 8. Incremental ON Resistance
NC
(
VMS VDD
)
VDD DUT VSS GND
A B
W
I CM
VCM
NC
Test Circuit 4. Power Supply Sensitivity (PSS, PSRR)
A DUT B 5V W OP279 OFFSET GND OFFSET BIAS VOUT
Test Circuit 9. Common-Mode Leakage Current
Test Circuit 5. Inverting Gain
-12-
REV. A
AD5241/AD5242
DIGITAL POTENTIOMETER SELECTION GUIDE
Number of VRs Terminal per Voltage Package1 Range 1 3 V, +5.5 V 5.5 V 15 V, +28 V 3 V, +5.5 V 5.5 V 3 V, +5.5 V Interface Data Control2 3-Wire Nominal Resistance (k ) 10, 50 Resolution (Number of Wiper Positions) 33 Power Supply Current (IDD) 40 A 40 A 100 A 40 A 5 A 50 A 10 A 80 A 5 A 10 A 50 A 60 A 5 A 10 A 60 A 5 A 60 A 60 A 40 A 20 A
Part Number AD5201
Packages SOIC-10 PDIP, SO-8, SOIC-8 PDIP-14, SOL-16, TSSOP-14 SOIC-10 SO-8 SO-14, TSSOP-14
Comments Full AC Specs, Dual Supply, Pwr-On-Reset, Low Cost No Rollover, Pwr-On-Reset Single 28 V or Dual 15 V Supply Operation Full AC Specs, Dual Supply, Pwr-On-Reset Full AC Specs I2C-Compatible, TC < 50 ppm/C Nonvolatile Memory, Direct Program, I/D, 6 dB Settability No Rollover, Stereo, Pwr-OnReset, TC < 50 ppm/C Full AC Specs, nA Shutdown Current Nonvolatile Memory, Direct Program, I/D, 6 dB Settability I2C-Compatible, TC < 50 ppm/C Medium Voltage Operation, TC < 50 ppm/C Full AC Specs, nA Shutdown Current Nonvolatile Memory, Direct Program, I/D, 6 dB Settability Full AC Specs, Dual Supply, Pwr-On-Reset Full AC Specs, nA Shutdown Current Full AC Specs, Dual Supply, Pwr-On-Reset TC < 50 ppm/C Full AC Specs, SVO Nonvolatile Memory, TC < 50 ppm/C
AD5220 AD7376
1 1
Up/Down 3-Wire
10, 50, 100 10, 50, 100, 1000
128 128
AD5200
1
3-Wire
10, 50
256
AD8400 AD5241
1 1
3-Wire 2-Wire
1, 10, 50, 100 10, 100, 1000
256 256
AD5231* 1
2.75 V, +5.5 V 3-Wire
10, 50, 100
1024
TSSOP-16
AD5222
2
3 V, +5.5 V 5.5 V
Up/Down
10, 50, 100, 1000
128
SO-14, TSSOP-14
AD8402
2
3-Wire
1, 10, 50, 100
256
PDIP, SO-14, TSSOP-14 TSSOP-16
AD5232
2
2.75 V, +5.5 V 3-Wire
10, 50, 100
256
AD5242
2
3 V, +5.5 V 5 V, +12 V 5.5 V
2-Wire
10, 100, 1000
256
SO-16, TSSOP-16
AD5262* 2
3-Wire
20, 50, 200
256
TSSOP-16
AD5203
4
3-Wire
10, 100
64
PDIP, SOL-24, TSSOP-24 TSSOP-16
AD5233* 4
2.75 V, +5.5 V 3-Wire
10, 50, 100
64
AD5204
4
3 V, +5.5 V 5.5 V 3 V, +5.5 V 5 V, +15 V 3 V, +5.5 V
3-Wire
10, 50, 100
256
PDIP, SOL-24, TSSOP-24 PDIP, SOL-24, TSSOP-24 PDIP, SOL-24, TSSOP-24 TSSOP-14 TSSOP-14 TSSOP-16
AD8403
4
3-Wire
1, 10, 50, 100
256
AD5206
6
3-Wire
10, 50, 100
256
AD5260 AD5207 AD5235
1 2 2
3-Wire 3-Wire
20, 50, 200 10, 50, 100 25, 250
256 256 1024
2.75 V, +5.5 V 3-Wire
NOTES *Future product, consult factory for latest status. 1 VR stands for variable resistor. This term is used interchangeably with RDAC, programmable resistor, and digital potentiometer. 2 3-wire interface is SPI- and microwire-compatible. 2-wire interface is I 2C-compatible.
REV. A
-13-
AD5241/AD5242
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead TSSOP (RU-14)
0.201 (5.10) 0.193 (4.90) 0.201 (5.10) 0.193 (4.90)
16-Lead TSSOP (RU-16)
14
8
16
9
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
1 7 1 8
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
PIN 1 0.006 (0.15) 0.002 (0.05) 8 0 0.0433 (1.10) MAX
SEATING PLANE
0.0256 (0.65) BSC
0.0118 (0.30) 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
0.028 (0.70) 0.020 (0.50)
SEATING PLANE
8 0.0256 (0.65) 0.0118 (0.30) 0.0079 (0.20) 0 BSC 0.0075 (0.19) 0.0035 (0.090)
0.028 (0.70) 0.020 (0.50)
14-Lead SOIC (R-14)
0.3444 (8.75) 0.3367 (8.55) 0.1574 (4.00) 0.1497 (3.80)
14 1 8 7
16-Lead SOIC (R-16A)
0.3937 (10.00) 0.3859 (9.80)
0.2440 (6.20) 0.2284 (5.80)
0.1574 (4.00) 0.1497 (3.80)
16 1
9 8
0.2440 (6.20) 0.2284 (5.80)
PIN 1
0.050 (1.27) BSC
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) 0.0099 (0.25)
45
PIN 1
0.050 (1.27) BSC
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) 0.0099 (0.25)
45
0.0098 (0.25) 0.0040 (0.10)
8 0.0192 (0.49) SEATING 0.0099 (0.25) 0 0.0138 (0.35) PLANE 0.0075 (0.19)
0.0500 (1.27) 0.0160 (0.41)
0.0098 (0.25) 0.0040 (0.10)
8 0.0192 (0.49) SEATING 0 0.0099 (0.25) PLANE 0.0138 (0.35) 0.0075 (0.19)
0.0500 (1.27) 0.0160 (0.41)
-14-
REV. A
AD5241/AD5242 Revision History
Location Data Sheet changed from REV. 0 to REV. A. Page
Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to FUNCTIONAL BLOCK DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Additions to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to Figures 1, 2, 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Addition of Readback RDAC Value and Additional Programmable Logic Output sections, and addition of new Figure 7 (which changed succeeding figure numbers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Additions/edits to DIGITAL POTENTIOMETER SELECTION GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
REV. A
-15-
-16-
C00926-0-2/02(A)
PRINTED IN U.S.A.

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