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Final Electrical Specifications
LTC2923 Power Supply Tracking Controller
August 2003
FEATURES
s s s s s s s s s
DESCRIPTIO
Flexible Power Supply Tracking Tracks Both Up and Down Power Supply Sequencing Supply Stability is Not Affected Controls Two Supplies Without Series FETs Controls a Third Supply with a Series FET Adjustable Ramp Rates Electronic Circuit Breaker Available in 10-Lead MS Package
The LTC(R)2923 provides a simple solution to power supply tracking and sequencing requirements. By selecting a few resistors, the supplies can be configured to ramp-up and ramp-down together with voltage offsets, with time delays or with differing ramp rates. By introducing currents into the feedback nodes of two independent supplies, the LTC2923 causes their outputs to track without inserting any pass element losses. Because the currents are controlled in an open-loop manner, the LTC2923 does not affect the transient response or stability of the supplies. Furthermore, it presents a high impedance when power-up is complete, effectively removing it from the DC/DC circuit. For systems that require a third supply, or when a supply does not allow direct access to its feedback resistors, one supply can be controlled with a series FET. When the FET is used, an electronic circuit breaker provides protection from short-circuit conditions.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
s s s s
VCORE and VI/O Supply Tracking Microprocessor, DSP and FPGA Supplies Servers Communication Systems
TYPICAL APPLICATIO
VIN 3.3V Q1 CGATE 10nF
3.3V 3.3V 2.5V 1.8V
1V/DIV VIN
RONB 154k RONA 100k
VCC ON
GATE
RAMP FB1
IN DC/DC FB = 1.235V RFA1 35.7k RFB1 16.5k VIN
OUT
1.8V
LTC2923 RAMPBUF TRACK1 TRACK 2 FB2 GND RFA2 412k
2923 TA01
RTB1 16.5k RTA1 13k RTB2 887k RTA2 412k
IN DC/DC FB = 0.8V RFB2 887k
3.3V OUT 2.5V 2.5V 1.8V 1V/DIV
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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1ms/DIV 1ms/DIV
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2923 TA02
2923 F08b
2923I
1
LTC2923
ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
Supply Voltage (VCC) ................................ - 0.3V to 10V Input Voltages ON ........................................................ - 0.3V to 10V TRACK1, TRACK2 ...................... - 0.3V to VCC + 0.3V RAMP ........................................... - 0.3V to VCC + 1V Output Voltages FB1, FB2 ................................................- 0.3V to 10V RAMPBUF ................................. - 0.3V to VCC + 0.3V GATE (Note 2) ................................... - 0.3V to 11.5V Average Current TRACK1, TRACK2 .............................................. 5mA FB1, FB2 ............................................................ 5mA RAMPBUF ......................................................... 5mA Operating Temperature Range LTC2923C ............................................... 0C to 70C LTC2923I ............................................ - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
ORDER PART NUMBER
TOP VIEW VCC ON TRACK1 TRACK2 RAMPBUF 1 2 3 4 5 10 9 8 7 6 RAMP GATE FB1 FB2 GND
LTC2923CMS LTC2923IMS MS PART MARKING LTAED LTAEE
MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125C, JA = 120C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
SYMBOL VCC ICC PARAMETER Input Supply Range Input Supply Current
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. 2.9V < VCC < 5.5V unless otherwise noted (Note 3).
CONDITIONS
q
MIN 2.9 5 2.2 5 -7 7 5 1.212 30 0.3 160
q q q
TYP 1.3 7 2.5 25 5.5 -10 10 20 1.230 75 0.4 0 200 0 90 100
MAX 5.5 3 10 2.7 6 -13 13 40 1.248 150 0.5 100 240 1 150 200 30
UNITS V mA mA V mV V A A mA V mV V nA mV A mV mV mV
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IFBx = 0, ITRACKx = 0 IFBx = -1mA, ITRACKx = -1mA, IRAMPBUF = -2mA VCC Rising IGATE = -1A Gate On, VGATE = 0V, No Faults Gate Off, VGATE = 5V, No Faults Gate Off, VGATE = 5V, Short-Circuit Fault VON Rising
VCC(UVL) VCC(UVLHYST) VGATE IGATE
Input Supply Undervoltage Lockout Input Supply Undervoltage Lockout Hysteresis External N-Channel Gate Drive (VGATE - VCC) GATE Pin Current
q q q q q q q
VON(TH) VON(HYST) VON(FC) ION VDS(TH) IRAMP VRAMPBUF(OL) VRAMPBUF(OH) VOS
ON Pin Threshold Voltage ON Pin Hysteresis ON Pin Fault Clear Threshold Voltage ON Pin Input Current FET Drain-Source Overcurrent Voltage Threshold (VCC - VRAMP) RAMP Pin Input Current RAMPBUF Low Voltage RAMPBUF High Voltage (VCC - VRAMPBUF) Ramp Buffer Offset (VRAMPBUF - VRAMP)
VON = 1.2V, VCC = 5.5V
q q
0V < RAMP < VCC, VCC = 5.5V IRAMPBUF = 2mA IRAMPBUF = -2mA VRAMPBUF = VCC/2, IRAMPBUF = 0A
q q q
-30
0
2
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LTC2923
ELECTRICAL CHARACTERISTICS
SYMBOL IERROR(%) VTRACKx IFB(LEAK) VFB(CLAMP) tPSC PARAMETER IFBx to ITRACKx Current Mismatch IERROR(%) = (IFBx - ITRACKx)/ITRACKx TRACK Pin Voltage IFB Leakage Current VFB Clamp Voltage Short-Circuit Propagation Delay VDS High to GATE Low
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. 2.9V < VCC < 5.5V unless otherwise noted (Note 3).
CONDITIONS ITRACKx = -10A ITRACKx = -1mA ITRACKx = -10A ITRACKx = -1mA VFB = 1.5V, VCC = 5.5V 1A < IFB < 1mA VDS = VCC, VCC = 2.9V
q q q q q q
MIN
TYP 0 0
MAX 5 5 0.824 0.824 100 2 20
UNITS % % V V nA V s
0.776 0.776 1.5
0.8 0.8 1 1.7 10
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The GATE pin is internally limited to a minimum of 11.5V. Driving this pin to voltages beyond the clamp may damage the part.
Note 3: All currents into the device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified.
TYPICAL PERFOR A CE CHARACTERISTICS
Specifications are at TA = 25C unless otherwise noted. VGATE vs VCC
12
11
VCC = 2.9V
10
IGATE (mA)
VGATE (V)
VGATE (V)
9
8 2 3 4 VCC (V) 5 6
2923 G01
UW
VGATE vs IGATE
15
30 25
IGATE vs VCC Fast Pull-Down
VGATE = 5V
VCC = 5.5V 10
20 15 10 5
5
0 0 5 IGATE (A)
2923 G02
10
0
15
0
1
2
3 VCC (V)
4
5
6
2923 G03
2923I
3
LTC2923
PI FU CTIO S
VCC (Pin 1): Positive Supply Input Pin. The operating supply input range is 2.9V to 5.5V. An undervoltage lockout circuit resets the part when the supply is below 2.5V. VCC should be bypassed to GND with a 0.1F capacitor. ON (Pin 2): On Control Input. The ON pin has a threshold of 1.23V with 75mV of hysteresis. An active high will cause 10A to flow from the GATE pin, ramping up the supplies. An active low pulls 10A from the GATE pin, ramping the supplies down. Pulling the ON pin below 0.4V resets the electronic circuit breaker in the LTC2923. If a resistive divider connected to VCC drives the ON pin, the supplies will automatically start up when VCC is fully powered. TRACK1, TRACK2 (Pins 3, 4): Tracking Control Input Pin. A resistive divider between RAMPBUF, TRACKx and GND determines the tracking profile of OUTx (see Applications Information). TRACKx pulls up to 0.8V and the current supplied at TRACKx is mirrored at FBx. The TRACKx pin is capable of supplying at least 1mA when VCC = 2.9V. It may be capable of supplying up to 10mA when the supply is at 5.5V, so care should be taken not to short this pin for extended periods. Limit the capacitance at the TRACKx pin to less than 25pF. Float the TRACK pins if unused. RAMPBUF (Pin 5): Ramp Buffer Output. Provides a low impedance buffered version of the signal on the RAMP pin. This buffered output drives the resistive dividers that connect to the TRACKx pins. Limit the capacitance at the RAMPBUF pin to less than 100pF. GND (Pin 6): Circuit Ground. FB1, FB2 (Pins 8, 7): Feedback Control Output. FBx pulls up on the feedback node of slave supplies. Tracking is achieved by mirroring the current from TRACKx into FBx. If the appropriate resistive divider connects RAMPBUF and TRACKx, the FBx current will force OUTx to track RAMP. To prevent damage to the slave supply, the FBx pin will not force the slave's feedback node above 1.7V. In addition, it will not actively sink current from this node even when the LTC2923 is unpowered. Float the FB pins if unused. GATE (Pin 9): Gate Drive for External N-Channel FET. When the ON pin is high, an internal 10A current source charges the gate of the external N-channel MOSFET. A capacitor connected from GATE to GND sets the ramp rate. An internal charge pump guarantees that GATE will pull up to 4.5V above RAMP ensuring that logic level N-channel FETs are fully enhanced. When the ON pin is pulled low, the GATE pin is pulled to GND with a 10A current source. Under a short-circuit condition, the electronic circuit breaker in the LTC2923 pulls the GATE low immediately with 20mA. Tie GATE to GND if unused. RAMP (Pin 10): Ramp Buffer Input. When the RAMP pin is connected to the source of the external N-channel FET, the slave supplies track the FET's source as it ramps up and down. If the GATE is fully enhanced (GATE > VCC + 4.9V) and (VCC - RAMP > 200mV) indicates a shorted output, then the electronic circuit breaker trips and GATE quickly pulls low with 20mA. The GATE will not ramp up again until ON is pulled below 0.4V and then above 1.23V. Alternatively, when no external FET is used, the RAMP pin can be tied directly to the GATE pin. In this configuration, the supplies track the capacitor on the GATE pin as it is charged and discharged by the 10A current source controlled by the ON pin.
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LTC2923
FU CTIO AL BLOCK DIAGRA
2
ON 1.2V
+ - - +
SHORT-CIRCUIT FAULT LATCH R S Q 10A
0.4V
VCC - RAMP > 200mV 0.2V VCC 5 RAMPBUF 1x VCC
3
TRACK1
+ -
VCC
0.8V FB1
4
TRACK2
+ -
0.8V FB2 GND
6
+ -
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1 VCC CHARGE PUMP 10A GATE 9 GATE > VCC + 4.9V 4.9V VCC RAMP > VCC VCC RAMP 10 8 8
2923 FBD
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2923I
5
LTC2923
APPLICATIO S I FOR ATIO
Power Supply Tracking and Sequencing The LTC2923 handles a variety of power-up profiles to satisfy the requirements of digital logic circuits including FPGAs, PLDs, DSPs and microprocessors. These requirements fall into one of the four general categories illustrated in Figures 1 to 4. Some applications require that the potential difference between two power supplies must never exceed a specified voltage. This requirement applies during power-up and power-down as well as during steady-state operation, often to prevent destructive latch-up in a dual supply ASIC. Typically, this is achieved by ramping the supplies up and down together (Figure 1). In other applications it is desirable to have the supplies ramp up and down with fixed voltage offsets between them (Figure 2) or to have them ramp up and down ratiometrically (Figure 3).
1V/DIV
1ms/DIV
2923 F01
Figure 1. Coincident Tracking
1V/DIV
1ms/DIV
2923 F03
Figure 3. Ratiometric Tracking
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Certain applications require one supply to come up after another. For example, a system clock may need to start before a block of logic. In this case, the supplies are sequenced as in Figure 4 where the 2.5V supply ramps up after the 1.8V supply is completely powered. Operation The LTC2923 provides a simple solution to all of the power supply tracking and sequencing profiles shown in Figures 1 to 4. A single LTC2923 controls up to three supplies with two "slave" supplies that track a "master" signal. With just two resistors, a slave supply is configured to ramp up as a function of the master signal. This master signal can be a third supply that is ramped up through an external FET, whose ramp rate is set with a single capacitor, or it can be a signal generated by tying the GATE and RAMP pins to an external capacitor.
MASTER SLAVE1 SLAVE2 1V/DIV MASTER SLAVE1 SLAVE2 1ms/DIV
2923 F02
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Figure 2. Offset Tracking
MASTER SLAVE1 SLAVE2 SLAVE1 1V/DIV SLAVE2
1ms/DIV
2923 F04
Figure 4. Supply Sequencing
2923I
LTC2923
APPLICATIO S I FOR ATIO
Tracking Cell
The LTC2923's operation is based on the tracking cell shown in Figure 5, which uses a proprietary wide-range current mirror. The tracking cell shown in Figure 5 servos the TRACK pin at 0.8V. The current supplied by the TRACK pin is mirrored at the FB pin to establish a voltage at the output of the slave supply. The slave output voltage varies with the master signal, enabling the slave supply to be controlled as a function of the master signal with terms set by RTA and RTB. By selecting appropriate values of RTA and RTB, it is possible to generate any of the profiles in Figures 1 to 4. Controlling the Ramp-Up and Ramp-Down Behavior The operation of the LTC2923 is most easily understood by referring to the simplified functional diagram in Figure 6. When the ON pin is low, the GATE pin is pulled to ground causing the master signal to remain low. Since the currents through RTB1 and RTB2 are at their maximum when the master signal is low, the currents from FB1 and FB2 are also at their maximum. These currents drive the slaves' outputs to their minimum voltages. When the ON pin rises above 1.23V, the master signal rises and the slave supplies track the master signal. The ramp rate is set by an external capacitor driven by a 10A current source from an internal charge pump. If no external FET is used, the ramp rate is set by tying the RAMP and
MASTER RTB TRACK RTA
Figure 5. Simplified Tracking Cell
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GATE pins together at one terminal of the external capacitor (see the Ratiometric Tracking Example). In a properly designed system, when the master signal has reached its maximum voltage the current from the TRACKx pin is zero. In this case, there is no current from the FBx pin and the LTC2923 has no effect on the output voltage accuracy, transient response or stability of the slave supply. When the ON pin falls below VON(TH) - VON(HYST), typically 1.225V, the GATE pin pulls down with 10A and the master signal and the slave supplies will fall at the same rate as they rose previously. The ON pin can be controlled by a digital I/O pin or it can be used to monitor an input supply. By connecting a resistive divider from an input supply to the ON pin, the supplies will ramp up only after the monitored supply has reached a preset voltage. Optional External FET The Coincident Tracking Example (Figures 8 and 9) illustrates how an optional external N-channel FET can ramp up a single supply that becomes the master signal. When used, the FET's gate is tied to the GATE pin and its source is tied to the RAMP pin. Under normal operation, the GATE pin sources or sinks 10A to ramp the FET's gate up or down at a rate set by the external capacitor connected to the GATE pin.
VCC
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+ + - -
FB 0.8V DC/DC FB OUT RFB SLAVE
RFA
2923 F05
2923I
7
LTC2923
APPLICATIO S I FOR ATIO U
VCC 10A GATE RONA 1.2V 9 CGATE Q1 10A VCC
RONB 2 ON
5
RAMPBUF
RTB1 3 RTA1 TRACK1 VCC
RTB2 4 RTA2 TRACK2
The LTC2923 features an electronic circuit breaker function that protects the optional series FET against short circuits. When the FET is fully enhanced (GATE > VCC + 4.9V), the electronic circuit breaker is enabled. Then, if the voltage across the FET (VDS) exceeds 200mV as measured from VCC to the RAMP pin for more than about 10s the gate of the FET is pulled down with 20mA, turning it off. Because the slaved supplies track the RAMP pin, they are pulled low by the tracking circuit when a short-circuit fault occurs. Following a short-circuit fault, the FET is latched off until the fault is cleared by pulling the ON pin below 0.4V.
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+ -
+-
200mV
+ -
1x VCC
RAMP
10
MASTER
+ -
0.8V
FB1
8
DC/DC RFB1
SLAVE1
RFA1
+ -
0.8V
FB2
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DC/DC RFB2
SLAVE2
RFA2
2923 F06
Figure 6. Simplified Functional Diagram
The Ramp Buffer The RAMPBUF pin provides a buffered version of the RAMP pin voltage that drives the resistive dividers on the TRACKx pins. When there is no external FET, it provides up to 2mA to drive the resistors even though the GATE pin only supplies 10A. The RAMPBUF pin also proves useful in systems with an external FET. Since the track cell in the simplified functional diagram above drives 0.8V on the TRACKx pins, if RTBx is connected directly to the FET's source, the TRACKx pin could potentially pull up the FET's source towards 0.8V when the FET is off. RAMPBUF blocks this path.
2923I
LTC2923
APPLICATIO S I FOR ATIO
3-Step Design Procedure The following 3-step procedure allows one to complete a design for any of the tracking or sequencing profiles shown in Figures 1 to 4. A basic three supply application circuit is shown in Figure 7. 1. Set the ramp rate of the master signal. Solve for the value of CGATE, the capacitor on the GATE pin, based on the desired ramp rate (V/s) of the master supply, SM.
CGATE = IGATE where IGATE 10A SM
If the external FET has a gate capacitance comparable to CGATE, then the external capacitor's value should be reduced to compensate for the FET's gate capacitance. If no external FET is used, tie the GATE and RAMP pins together. 2. Solve for the pair of resistors that provide the desired ramp rate of the slave supply, assuming no delay. Choose a ramp rate for the slave supply, SS. If the slave supply ramps up coincident with the master supply or with a fixed voltage offset, then the ramp rate equals the master supply's ramp rate. Be sure to use a fast enough ramp rate for the slave supply so that it will finish ramping before the master supply has reached its final supply value. If not, the slave supply will be held below the intended regulation value by the master supply. Use the following formulas to determine the resistor values for the desired ramp rate, where RFB and RFA are the feedback resistors in the slave supply and VFB is the feedback reference voltage of the slave supply:
S RTB = RFB * M SS
RTA = VTRACK V V + FB - TRACK RFA RTB
VFB RFB
where VTRACK 0.8V.
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Note that large ratios of slave ramp rate to master ramp rate, SS/SM, may result in negative values for RTA. If sufficiently large delay is used in step 3, RTA will be positive, otherwise SS/SM must be reduced. 3. Choose RTA to obtain the desired delay. If no delay is required, such as in coincident and ratiometric tracking, then simply set RTA = RTA. If a delay is desired, as in offset tracking and supply sequencing, calculate RTA to determine the value of RTA where tD is the desired delay. (1)
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RTA =
VTRACK * RTB tD * SM
(4) (5)
RTA = RTA||RTA the parallel combination of RTA and RTA
As noted in step 2, small delays and large ratios of slave ramp rate to master ramp rate (usually only seen in sequencing) may result in solutions with negative values for RTA. In such cases, either the delay must be increased or the ratio of slave ramp rate to master ramp rate must be reduced.
Q1 VIN 0.1F CGATE VIN RONB RONA IN DC/DC FB RFB1 VIN TRACK1 RTA1 RTB2 TRACK 2 RTA2 GND RFB2 RFA2 FB2 FB IN DC/DC OUT SLAVE2 OUT SLAVE1 MASTER
VCC ON
GATE
RAMP FB1
LTC2923 RAMPBUF RFA1
RTB1
(2)
(3)
2923 F07
Figure 7. Three Supply Application
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LTC2923
APPLICATIO S I FOR ATIO
Coincident Tracking Example
1V/DIV
1ms/DIV
Figure 8. Coincident Tracking (From Figure 9)
A typical three supply application is shown in Figure 9. The master signal is a 3.3V module. The slave 1 supply is a 1.8V switching power supply and the slave 2 supply is a 2.5V switching power supply. Both slave supplies track coincidently with the 3.3V supply that is controlled with an external FET. The ramp rate of the supplies is 1000V/s. The 3-step design procedure detailed previously can be used to determine component values. Only the slave 1 supply is considered here as the procedure is the same for the slave 2 supply. 1. Set the ramp rate of the master signal. From Equation 1: CGATE = 10A = 10nF 1000 V/s
2. Solve for the pair of resistors that provide the desired slave supply behavior, assuming no delay. From Equation 2: RTB = 16.5k * From Equation 3: RTA = 0.8 V 13k 1.235V 1.235V 0.8 V + - 16.5k 35.7k 16.5k 1000 V/s = 16.5k 1000 V/s
3. Choose RTA to obtain the desired delay. Since no delay is desired, RTA = RTA
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MASTER SLAVE2 SLAVE1 1V/DIV
2923 F08a
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1ms/DIV
2923 F08b
Q1 3.3V CGATE 10nF
3.3V MASTER
3.3V RONB 154k RONA 100k RTB1 16.5k RTA1 13k RTB2 887k RTA2 412k IN DC/DC FB = 1.235V OUT RFA1 RFB1 16.5k 35.7k 3.3V IN DC/DC FB = 0.8V OUT RFA2 412k
2923 F09
VCC ON
GATE
RAMP FB1
1.8V SLAVE1
LTC2923 RAMPBUF TRACK1 FB2 TRACK2 GND RFB2 887k
2.5V SLAVE2
Figure 9. Coincident Tracking Example
In this example, all supplies remain low while the ON pin is held below 1.23V. When the ON pin rises above 1.23V, 10A pulls up CGATE and the gate of the FET at 1000V/s. As the gate of the FET rises, the source follows and pulls up the output to 3.3V at 1000V/s. This output serves as the master signal and is buffered from the RAMP pin to the RAMPBUF pin. As this output and the RAMPBUF pin rise, the current from the TRACK pins is reduced. Consequently, the voltage at the slave supply's outputs is reduced, and the slave supplies track the master supply. When the ON pin is again pulled below 1.23V, 10A will pull down CGATE and the gate of the FET at 1000V/s. If the loads on the outputs are sufficient, all outputs will track down coincidently at 1000V/s.
2923I
LTC2923
APPLICATIO S I FOR ATIO
Ratiometric Tracking Example
1V/DIV
1ms/DIV
Figure 10. Ratiometric Tracking (From Figure 11)
This example converts the coincident tracking example to the ratiometric tracking profile shown in Figure 10, using two supplies without an external FET. The ramp rate of the master signal remains unchanged (Step 1) and there is no delay in ratiometric tracking (Step 3), so only the result of step 2 in the 3-step design procedure needs to be considered. In this example, the ramp rate of the 1.8V slave 1 supply ramps up at 600V/s and the 2.5V slave 2 supply ramps up at 850V/s. Always verify that the chosen ramp rate will allow the supplies to ramp-up completely before RAMPBUF reaches VCC. If the 1.8V supply were to rampup at 500V/s it would only reach 1.65V because the RAMPBUF signal would reach its final value of VCC = 3.3V before the slave supply reached 1.8V. 2. Solve for the pair of resistors that provide the desired slave supply behavior, assuming no delay. From Equation 2: 1000 V/s RTB = 16.5k * 27.4k 600 V/s
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SLAVE2 SLAVE1 1V/DIV
2923 F10a
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1ms/DIV
2923 F10b
From Equation 3: RTA = 0.8 V = 10k 1.235V 1.235V 0.8 V - + 16.5k 35.7k 27.5k
Step 3 is unnecessary because there is no delay, so RTA = RTA.
3.3V CGATE 10nF RONB 154k RONA 100k RTB1 27.4k RTA1 10k RTB2 1M RTA2 383k VCC GATE ON LTC2923 RAMPBUF TRACK1 TRACK 2 GND RFA2 412k
2923 F11
3.3V IN DC/DC FB = 1.235V OUT RFA1 RFB1 35.7k 16.5k 3.3V IN DC/DC FB = 0.8V OUT RFB2 887k
RAMP FB1
1.8V SLAVE1
FB2
2.5V SLAVE2
Figure 11. Ratiometric Tracking Example
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11
LTC2923
APPLICATIO S I FOR ATIO
Offset Tracking Example
1V/DIV
1ms/DIV
Figure 12. Offset Tracking (From Figure 13)
Converting the circuit in the coincident tracking example to the offset tracking shown in Figure 12 is relatively simple. Here the 1.8V slave 1 supply ramps up 0.5V below the master. The ramp rate remains the same (1000V/s), so there are no changes necessary to steps 1 and 2 of the 3-step design procedure. Only step 3 must be considered. Be sure to verify that the chosen voltage offsets will allow the slave supplies to ramp up completely. In this example, if the voltage offset were 2V, the slave supply would only ramp up to 3.3V - 2V = 1.3V. 3. Choose RTA to obtain the desired delay. First, convert the desired voltage offset, VOS, to a delay, tD, using the ramp rate: tD = VOS 1V = = 1ms SS 1000 V/s (6)
From Equation 4: RTA = 0.8 V * 16.5k = 13.2k 1ms * 1000 V/s
From Equation 5: RTA = 13.1k||13.2k 6.65k
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MASTER SLAVE2 SLAVE1 1V/DIV
2923 F12a
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1ms/DIV
2923 F12b
Q1 3.3V
3.3V MASTER
CGATE 10nF 3.3V RONB 154k RONA 100k RTB1 16.5k RTA1 6.65k RTB2 887k RTA2 316k IN DC/DC FB = 1.235V OUT RFA1 RFB1 35.7k 16.5k 3.3V IN DC/DC FB = 0.8V OUT RFB2 887k
VCC ON
GATE
RAMP FB1
1.8V SLAVE1
LTC2923 RAMPBUF TRACK1 TRACK 2 GND RFA2 412k
2923 F13
FB2
2.5V SLAVE2
Figure 13. Offset Tracking Example
2923I
LTC2923
APPLICATIO S I FOR ATIO
Supply Sequencing Example
1V/DIV
10ms/DIV
Figure 14. Supply Sequencing (From Figure 15)
In Figure 14, the slave 1 supply and the slave 2 supply are sequenced instead of tracking. The 3.3V supply ramps up at 100V/s with an external FET and serves as the master signal. The 1.8V slave 1 supply ramps up at 1000V/s beginning 10ms after the master signal starts to ramp up. The 2.5V slave 2 supply ramps up at 1000V/s beginning 25ms after the master signal begins to ramp up. Note that not every combination of ramp rates and delays is possible. Small delays and large ratios of slave ramp rate to master ramp rate may result in solutions that require negative resistors. In such cases, either the delay must be increased or the ratio of slave ramp rate to master ramp rate must be reduced. In this example, solving for the slave 1 supply yields: 1. Set the ramp rate of the master signal. From Equation 1: CGATE = 10A = 100nF 100 V/s
2. Solve for the pair of resistors that provide the desired slave supply behavior, assuming no delay. From Equation 2: 100 V/s RTB = 16.5k * = 1.65k 1000 V/s
RTB1 1.65k RTA1 3.48k
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MASTER SLAVE2 SLAVE1 1V/DIV
2923 F14a
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10ms/DIV
2923 F14b
From Equation 3: RTA = 0.8 V = -2.13k 1.235V 1.235V 0.8 V + - 16.5k 35.7k 1.65k
3. Choose RTA to obtain the desired delay. From Equation 4: RTA = 0.8 V * 1.65k = 1.32k 10ms * 100 V/s
From Equation 5: RTA = - 2.13k||1.32k = 3.48k
Q1 3.3V CGATE 100nF 3.3V RONB 154k RONA 100k IN DC/DC FB = 1.235V OUT RFA1 RFB1 16.5k 35.7k 3.3V IN DC/DC FB = 0.8V OUT RFA2 412k RFB2 887k 3.3V MASTER
VCC ON
GATE
RAMP FB1
1.8V SLAVE1
LTC2923 RAMPBUF TRACK1 FB2 TRACK 2 GND
RTB2 88.7k RTA2 36.5k
2.5V SLAVE2
2923 F15
Figure 15. Supply Sequencing Example
2923I
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LTC2923
APPLICATIO S I FOR ATIO
Final Sanity Checks
The collection of equations below is useful for identifying unrealizable solutions. As stated in step 2, the slave supply must finish ramping before the master signal has reached its final voltage. This can be verified by the following equation:
R VTRACK 1 + TB < VCC, where VTRACK = 0.8 V RTA
It is possible to choose resistor values that require the LTC2923 to supply more current than the Electrical Characteristics table guarantees. To avoid this condition, check that ITRACKx does not exceed 1mA and IRAMPBUF does not exceed 2mA. To confirm that ITRACKx < 1mA, the TRACKx pin's maximum guaranteed current, verify that:
VTRACK < 1mA RTA RTB
Finally, check that the RAMPBUF will not be forced to sink more then 2mA when it is at 0V or be forced to source more than 2mA when it is at VCC.
VTRACK V + TRACK < 2mA and RTA1 RTB1 RTA2 RTB2 VCC VCC + < 2mA RTA1 + RTB1 RTA2 + RTB2
1V/DIV
Load Requirements When the supplies are ramped down quickly, either the load or the supply itself must be capable of sinking enough current to support the ramp rate. For example, if there is a large output capacitance on the supply and a weak resistive load, supplies that do not sink current will have their falling ramp rate limited by the RC time constant of the load and the output capacitance. Figure 16 shows the case when the 2.5V supply does not track the 1.8V and 3.3V supplies near ground. Start-Up Delays Often power supplies do not start-up immediately when their input supplies are applied. If the LTC2923 tries to
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ramp-up these power supplies as soon as the input supply is present, the start-up of the outputs may be delayed, defeating the tracking circuit (Figure 17). Often this delay is intentionally configured by a soft-start capacitor. This can be remedied either by reducing the soft-start capacitor on the slave supply or by including a capacitor in the ON pin's resistive divider to delay the ramp up. See Figure 18.
MASTER SLAVE2 SLAVE1 1V/DIV 1ms/DIV
2923 F16
W
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Figure 16. Weak Resistive Load
MASTER
SLAVE1 SLAVE2
ON
1ms/DIV
2923 F17
Figure 17. Power Supply Start-Ups Delayed
MASTER
SLAVE1 1V/DIV SLAVE2
ON
1ms/DIV
2923 F18
Figure 18. ON Pin Delayed
2923I
LTC2923
APPLICATIO S I FOR ATIO
Layout Considerations
Be sure to place a 0.1F bypass capacitor as near as possible to the supply pin of the LTC2923. To minimize the noise on the slave supplys' outputs, keep the traces connecting the FBx pins of the LTC2923 and the feedback nodes of the slave supplies as short as possible. In addition, do not route those traces next to signals with fast transition times. In some circumstances it might be advantageous to add a resistor near the feedback node of the slave supply in series with the FBx pin of the LTC2923. This resistor must not exceed: RSERIES = 1.5V - VFB IMAX 1.5V -1 VFB = RFA || RFB
PACKAGE DESCRIPTIO
(Reference LTC DWG # 05-08-1661)
3.00 0.102 (.118 .004) (NOTE 3) 10 9 8 7 6
0.889 0.127 (.035 .005)
5.23 (.206) MIN
3.20 - 3.45 (.126 - .136)
0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT
GAUGE PLANE 12345 0.53 0.152 (.021 .006) DETAIL "A" 0.18 (.007) 1.10 (.043) MAX 0.86 (.034) REF
SEATING NOTE: PLANE 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
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This resistor is most effective if there is already a capacitor at the feedback node of the slave supply (often a compensation component). Increasing the capacitance on a slave supply's feedback node will further improve the noise immunity, but could affect the stability and transient response of the supply.
FET VCC OUT VCC RAMP FB1 GND 0.1F
2923 F19
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W
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LTC2923
MINIMIZE TRACE LENGTH RSERIES
DC/DC FB OUT RFB
RFA
Figure 19. Layout Considerations
MS Package 10-Lead Plastic MSOP
0.497 0.076 (.0196 .003) REF
0.254 (.010)
DETAIL "A" 0 - 6 TYP
4.90 0.152 (.193 .006)
3.00 0.102 (.118 .004) (NOTE 4)
0.17 - 0.27 (.007 - .011) TYP
0.50 (.0197) BSC
0.127 0.076 (.005 .003)
MSOP (MS) 0603
2923I
15
LTC2923
TYPICAL APPLICATIO S
Daisy-Chained Application
3.3V 0.1F IN DC/DC FB = 1.235V OUT RFB1 3.3V 0.1F CGATE 10nF RONB 154k RONA 100k VCC GATE ON LTC2923 RAMPBUF RTB1 2.5V SLAVE2 TRACK1 RTA1 RTB2 TRACK 2 RTA2 GND RFA2 CGATE 10nF RONB 154k RONA 100k VCC GATE ON LTC2923 RAMPBUF RTB TRACK1 RTA RTB TRACK 2 RTA GND RFA
2923 TA03 2923 TA04
VCC ON
GATE FB1 LTC2923
RAMPBUF RTB1 TRACK1 RTA1 RTB2 TRACK 2 RTA2 GND FB2 RAMP
3.3V 0.1F
RAMP FB1
FB2
RELATED PARTS
PART NUMBER LTC1645 LTC2920 LTC2921/LTC2922 LT 4220 LTC4230 LTC4253
(R)
DESCRIPTION Dual Hot Swap Controller Power Supply Margining Controller Power Supply Tracker with Input Monitors Dual Supply Hot Swap Controller Triple Hot Swap Controller with Multifunction Current Control - 48V Hot Swap Controller and Supply Sequencer
TM
Hot Swap is a trademark of Linear Technology Corporation.
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
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High Voltage Supply Application
3.3V SLAVE1
RAMP FB1
IN DC/DC FB = 1.235V OUT RFB1
RFA1
12V SLAVE1
RFA1
IN DC/DC FB = 0.8V OUT RFB2 RFA2
FB2
IN DC/DC FB = 0.8V OUT RFB2
5V SLAVE2
IN DC/DC FB = 1.235V OUT RFB
1.8V SLAVE1
RFA
IN DC/DC FB = 0.8V OUT RFB
1.5V SLAVE2
COMMENTS Operates from 1.2V to 12V, Allows Supply Sequencing Single or Dual Versions, Symmetric/Symmetric High and Low Margining Includes 3 (LTC2921) or 5 (LTC2922) Remote Sense Switches 2.7V to 16.5V, Supply Tracking Mode 1.7V to 16.5V, Active Inrush Limiting, Fast Comparator Floating Supply from -15V, Active Current Limiting, Enables Three DC/DC Converters
2923I LT/TP 0803 1K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2003

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