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| 29C532E 32-Bit Bus-Watch EDAC Error Detection And Correction unit 1. Description The 29C532E EDAC is a very low power bus-watch 32-bit Error Detection And Correction unit (EDAC). EDAC is used in a high integrity system for monitoring and correcting data values coming from the memory space. Such a bus-watch EDAC is connected as a peripheral on the data bus and watches on and controls the integrity of the data memory. During a processor write cycle, at each memory location (32-bit width), EDAC calculated checkword (7 or 8-bit width) is added. When performing a read operation from memory, the 29C532E verifies the entire checkword and data combination. It detects and can correct 100% of all the single-bit errors and it detects all multi-bit errors but can not correct them. All the errors are reported to the master system to allow the processor to take action as required. In case of single-bit error, the Correctable ERRor flag is set and the single-bit in error is complemented (corrected). Then, the data can be substituted to the corrupted data on the system data bus. In case of multi-bit error, the Non-Correctable ERRor flag is set, the data can not be repaired. Note that when multi-bit errors occur, there are some bit patterns which may appear as possible correctable errors. Therefore, if the environment produces this type of error, the EDAC must be used in detect-only-without-correction configuration. Data and syndrome analysis must be rapidly done. Because the 29C532E latches the data, byte or 16-bit word write operations are possible if they take place in a read-modify-write accesses to the memory space. When the 29C532E uses 7-checkbit, it can detect any errors on any single 1 or 4-bit memory chip. The 8-checkbit option gives the additional capability to detect all errors on any 8-bit memory chip. 2. Features D D D D D 32-bit Operation (7 or 8 Check Bits) Bus Watch Architecture Fast Error Detection: 32 ns Fast Error Correction: 39 ns Corrects All Single-Bit Errors Detects All Double-Bit Errors Detects Some Multi-Bit Errors Detects Chip Error (x1, x4 & x8 RAM Format) D D D D D D Correctable and Non-Correctable Error Flags Very Low Power CMOS TTL Compatible Single 5V 10% Power Supply High Drive Capability on Bus: 12.8 mA 100-Pin Multi-Layer Quad Flatpack Rev. B - 26 February, 1997 1 Preliminary Information 29C532E 3. Interface 3.1. Block Diagram SYNCHK CORRECT OLE/CHK 32 DOE [3..0] Data-Out LATCH GCB [7..0] D [31..24] D [23..16] 8 BUFFER 8 32 CHECKBIT GENERATOR 32 Data 32 DO [31..0] 8 8 8 D [15..8] D [7..0] Data-In LATCH 32 8 32 DI [31..0] RCB [7..0] 8 32 SYNDROME GENERATOR ILE CONTROL Chk-In LATCH BUFFER Checkbit 8 8 CI [7..0] SY [7..0] C [7..0] 8 8 8 8 Diagnosis LATCH CO [7..0] CDO [31..0] 32 32 SYNDROME DECODER COE 8 8 DIA [7..0] DLE DIAG [1..0] N39 CERR NCERR 2 Rev. B - 26 February, 1997 Preliminary Information 29C532E 3.2. Pin Configuration SYNCHK ILE VccB DIAG [1] DIAG [0] GndC DOE [3] GndB D [31] D [30] D [29] D [28] VccB D [27] D [26] D [25] (n.c) (n.c) 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 60 Index Corner 99 100 98 1 (n.c) N39 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (n.c) GndB (n.c) (n.c) (n.c) (n.c) (n.c) CORRECT DOE [0] D [0] D [1] D [2] VccB D [3] D [4] D [5] D [6] GndB D [7] D [8] D [9] D [10] (n.c) (n.c) (n.c) (n.c) (n.c) (n.c) (n.c) VccB 30 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 79 78 77 76 75 74 73 72 71 70 69 68 29C532E (Top View) 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 (n.c) (n.c) (n.c) (n.c) (n.c) (n.c) D [24] GndB D [23] D [22] D [21] D [20] VccB D [19] D [18] D [17] D [16] GndB DOE [2] OLE/CHK DLE COE VccB CERR NCERR (n.c) (n.c) VccC (n.c) (n.c) (n.c) D [11] D [12] D [13] D [14] GndB D [15] DOE [1] C [0] C [1] VccB C [2] C [3] C [4] C [5] GndB C [6] C [7] (n.c) (n.c) Rev. B - 26 February, 1997 3 Preliminary Information 29C532E 3.3. Pin Description Name Buses D [31..24] D [23..16] D [15..8] D [7..0] C [7..0] 90, 89, 88, 87, 85, 84, 83, 74 72, 71, 70, 69, 67, 66, 65, 64 I/O 37, 35, 34, 32, 31, 22, 21, 20 19, 17, 16, 15, 14, 12, 11, 10 48, 47, 45, 44, 43, 42, 40, 39 I/O Checkbit bus. Output checkbit on C [7..0] bus is controlled by COE. Data bus. Output data on D [31..24] bus is controlled by DOE [3]. Output data on D [23..16] bus is controlled by DOE [2]. Output data on D [15..8] bus is controlled by DOE [1]. Output data on D [7..0] bus is controlled by DOE [0]. Pin Nb. I/O Active Description Flags CERR NCERR 57 56 O O Low Low Correctable ERror. UnCorrectable ERror. Controls DOE [3] DOE [2] DOE [1] DOE [0] COE 9 38 I 62 92 59 I Low Low Data Output Enable for D [15..8] bus. Data Output Enable for D [7..0] bus. Checkbit Output Enable for C [7..0] bus. OLE OLE/CHK 61 I H/L CHK CHecKbit enable. Only if DIAG [0] = 0 (non active): 0: CO [7..0] = GCB [7..0]. 1: CO [7..0] = SY [7..0]. Output Latch Enable for DO [31..0] internal bus: 1: transparent, 0: latched. Data Output Enable for D [31..24] bus. Data Output Enable for D [23..16] bus. ILE 97 I High Input Latch Enable to produce DI [31..0] and CI [7..0] internal buses respectively from D [31..0] and C [7..0]: 1: transparent, 0: latched. Diagnosis Latch Enable to produce DIA [7..0] internal bus from D [7..0] bus: 1: transparent, 0: latched. DLE 60 I High 4 Rev. B - 26 February, 1997 Preliminary Information 29C532E Name Controls SYNdrome & CHecKbit enable. During a read mode: 0: DO [31..24] = DIA [7..0], DO [23..16] = SY [7..0], SYNCHK 98 I Low DO [15..8] = CI [7..0], Pin Nb. I/O Active Description DO [7..0] = DIA [7..0]. 1: DO [31..0] = CDO [31..0]. CORRECT 8 I High CORRECTion enable. Only if SYNCHK = 1 (non active): 1: DO [31..0] = CDO [31..0]. 0: DO [31..0] = DI [31..0]. Code leNgth equals 39: 1: the EDAC uses 7 check bits. 0: the EDAC uses 8 check bits. DIAGnosis mode 1. Diagnosis detect & correct: 1: RCB [7..0] = DIA [7..0]. 0: RCB [7..0] = CI [7..0]. I DIAG [0] 94 High DIAGnosis mode 0. Diagnosis generate: 1: CO [7..0] = DIA [7..0]. 0: CO [7..0] = SY [7..0] or GCB [7..0] following the OLE/CHK value. N39 99 I High DIAG [1] 95 Power (Buffers) VccB GndB 13, 30, 41, 58, 68, 86, 96 2, 18, 36, 46, 63, 73, 91 Buffers supply (5V nominal) Buffers 0V reference Power (Core) VccC GndC 53 93 Core supply (5V nominal) Core 0V reference All I/O and I buffers have a pull-up resistor ' 100 . Rev. B - 26 February, 1997 5 Preliminary Information 29C532E 4. Checkbit Generation The checkbit generator produces 8 checkbits (whatever N39 value) from the incoming data DI [31..0] according the following table. Table 1: Checkbit generation (x indicates bit of D [31..0] used in the parity calculation) DI [31..0] GCB Parity [7..0] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0 1 2 3 4 5 6 7 Even (XOR) 8 x x x 7 6 5 x 4 x x 3 2 1 x 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Even (XOR) x x x x x x x x x x x x x x x x x Odd (NXOR) x x x x x x x x x x x x x x x x x x x x x x x x x x x Even (XOR) x x Odd (NXOR) x x x x Even (XOR) x x x x x Even (XOR) x x x Odd (NXOR) x x Example To create GCB [3], bit 31, 30, 27, 23, 22, 19, 15, 14, 13, 12, 10, 9, 8, 7, 4 and 0 of DI [31..0] are 3ORed together.If SRAM devices 1 or 4-bit are used in a memory system controlled by the 29C532E EDAC, it is only necessary to store 39 bits (D [31..0] & C [6..0]).If SRAM devices 8-bit are used in a memory system controlled by the 29C532E EDAC, 40 bits (D [31..0] & C [7..0]) must be stored. 6 Rev. B - 26 February, 1997 Preliminary Information 29C532E 5. Syndrome Generation The syndrome generator produces 8 syndrome-bits (whatever N39 value) from the incoming data DI [31..0] and the associated checkbit RCB [7..0] (via CI [7..0] or DIA [7..0] following DIAG [1] value) according the following table. Table 2: Checkbit generation (x indicates bit of D [x1..0] used in the parity calculation) DI [x1..0] SY [7..0] Parity 31 0 30 x 29 x 28 x 27 26 25 24 x 23 22 21 x 20 x 19 x 18 18 17 16 15 x 14 1x 12 Even (XOR) x 1 Even (XOR) x x x x x x x x x x 2 Odd (NXOR) x x x x x x x x x 3 Even (XOR) x x x x x x x x x x 4 Odd (NXOR) x x x x x x x x x x 5 Even (XOR) x x x x x x x x x x 6 Even (XOR) x x x x x x x x x x x x x 7 Odd (NXOR) x x x x x x x x x x Rev. B - 26 February, 1997 7 Preliminary Information 29C532E Table 2: (continue) SY [7..0] 0 DI [x1..0] Parity 11 10 x 9 x 8 x 7 6 5 x 4 x 3 2 1 x 0 RCB [7..0] Parity 7 6 5 4 3 2 1 0 x Even (XOR) x Evn (XOR) 1 Even (XOR) x x x x x x Even (XOR) x x x 2 Odd (NXOR) x x x x x x Even (XOR) x x 3 Even (XOR) x x x x x Even (XOR) x 4 Odd (NXOR) x x x x x x Even (XOR) x 5 Even (XOR) x x x x x x x Even (XOR) x 6 Even (XOR) x x x x Even (XOR) x x 7 Odd (NXOR) x x x x x Even (XOR) x The syndrome bit SY[x] is the XOR of the received checkbit RCB[x] and the parity calculation on DI [31..0]. Example: To create SY [1], bit 30, 28, 25, 24, 20, 17, 16, 15, 13, 12, 9, 8, 7, 6, 4 and 3 of DI [31..0] are NXORed together. Then, the result is XORed with the associated checkbit RCB [1] of the checkbit byte read at the same address than the data word DI [31..0]. If SRAM devices 1 or 4-bit are used in a memory system controlled by the 29C532E EDAC, only 39 bits (D [31..0] & C [6..0]) are checked and the generated syndrome word is 7-bit width. If SRAM devices 8-bit are used in a memory system controlled by the 29C532E EDAC, 40 bits (D [31..0] & C [7..0]) are checked, the generated syndrome word is 8-bit width. 6. Syndrome Decoding The syndrome decoder generates the error flags CERR (Correctable ERror) and NCERR (Non-Correctable ERror). It mainly provides corrected data word to the system bus if a correctable error occurs. In case of single bit-error, using the syndrome value, this block decodes which bit is in error and complements it to correct the data word. This correction is only made on the 32 bits of data not on the checkbit word. The inputs of the syndrome decoder are: D the 32 bits of data coming from the system data bus, D the syndrome coming from the syndrome generator, D the control signal N39. N39 signal controls if 39 or 40 bits will be decoded from the entire word. 8 Rev. B - 26 February, 1997 Preliminary Information 29C532E Table 3: 7-bit syndrome word to bit-in-error (N39=1) hex 0 7 6 5 4 hex 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 Syndrome bit SY [7..0] 0 0 0 0 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D[4] D[8] D[15] D[14] D[10] D[12] D[13] D[9] D[22] D[19] D[31] D[7] D[30] C [3] D[0] D[27] D[23] D[3] C [2] D[5] D[6] N.E.D C [0] C [1] D[24] D[20] D[26] D[1] D[16] C [4] C [5] D[21] D[25] D[28] D[2] D[18] C [6] D[29] D[17] D[11] 0 1 2 3 4 5 6 7 8 9 A B C D E F Note: N.E.D D [x] C [x] = = = = No Error Detected, Data bit-in-error, Check bit-in-error Multi-bit-in-error Rev. B - 26 February, 1997 9 Preliminary Information 29C532E Table 4: 8-bit syndrome word to bit-in-error (N39=0) hex Syndrome 7 6 5 4 hex 3 2 1 0 0 1 2 3 4 5 6 7 8 9 A B C D E F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 D[4] D[8] D[15] D[10] D[19] D[31] D[13] D[9] D[30] D[14] D[22] D[12] D[7] C [3] D[23] D[0] D[27] D[3] C [2] D[5] D[6] N.E.D C [4] C [0] C [1] D[20] D[28] D[18] D[24] D[26] D[1] D[16] D[2] C [5] C [6] D[29] C [7] D[21] D[25] D[17] D[11] 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 A 1 0 1 0 B 1 0 1 1 C 1 1 0 0 D 1 1 0 1 E 1 1 1 0 F 1 1 1 1 bit SY [7..0] Note : N.E.D D [x] C [x] = = = = No Error Detected, Data bit-in-error, Check bit-in-error Multi-bit-in-error 10 Rev. B - 26 February, 1997 Preliminary Information 29C532E 7. 7-Bit Syndrome Word This feature is available when the N39 pin is driven at a high level. 7.1. No Error If there is no error in the read data or checkbit, all the syndrome word is "00". The EDAC flags are inactive. No Error SY= 0x00 7.2. Single Bit-In-Error When the Memory Data word (D [31..0] & C[6..0]) read has one bit-in-error, the 20C532E EDAC develops a code (syndrome) which indicates the bit in error (each bit have its own syndrome value). In this case, the syndrome decoder sets low the correctable error flag CERR, but NCERR flag remains at high level. In case of single bit-error on D [31..0], if the control lines SYNCHK = non active and CORRECT = active, the Table 5: 7-bit syndrome word for single bit-error. D[31..16] SY 31 0x6D 30 0x5B 29 0x51 28 0x4x 27 0x58 26 0x34 25 0x32 24 0x13 23 0x68 22 0x4C 21 0x31 20 0x23 19 0x5D 18 0x64 17 0x52 16 0x46 corrected value (CDO [31..0]) is available on DO [31..0] internal bus and the syndrome word is available on CO [6..0]. The corrected value is obtains to complement the bit-in-error. In same conditions, if a single bit-error occurs on C [6..0], the corrected value of the checkbit is not available in the device. D[15..0] SY 15 0x4F 14 0x2C 13 0x2A 12 0x1A 11 0x60 10 0x3D 9 0x3B 8 0x2F 7 0x4A 6 0x26 5 0x25 4 0x1F 3 0x16 2 0x54 1 0x45 0 0x38 C[7..0] SY -- 6 0x40 5 0x20 4 0x10 3 0x08 2 0x04 1 0x02 0 0x01 7.3. Double Bit-In-Error When the Memory Data word (D [31..0] & C[6..0]) read has two bit-in-error, the 20C532E EDAC develops a syndrome different of 0x00. The syndrome value generated by a double bit-in-error never takes place of a syndrome value generated by a single bit-in-error. In this case, the syndrome decoder sets low the non correctable error flag NCERR and CERR flag remains at high level. Example : If data D [12] and D [9] are incorrect, syndrome bit SY [5] and SY [0] are set to one (SY= 0x21), NCERR flag is set low (CERR flag remains at high level). 7.4. Triple Bit-In-Error When the Memory Data word (D [31..0] & C[6..0]) read has three bit-in-error, the 20C532E EDAC develops a syndrome different of 0x00. The syndrome value Rev. B - 26 February, 1997 generated by a triple bit-in-error can have any value, even a syndrome value normally generated by a single 11 Preliminary Information 29C532E bit-in-error. NCERR flag or CERR flag can be activated following the value of the generated syndrome. Example : If data D [28], D [18] and D [1] are incorrect, syndrome bit SY [6], SY [5] and SY [1] are set to one (SY= 0x62), NCERR flag is set low (CERR flag remains at high level). Fault example : If data D [24], D [12] and D [3] are incorrect, syndrome bits SY [4..0] are set to one (SY= 0x1F). The syndrome is decoded by the 29C532E EDAC has being a correctable error on D [4]. Then, CERR flag is set low and NCERR flag remains at high level. A correction would cause more errors. 7.5. Multi Bit-In-Error When the Memory Data word (D [31..0] & C[6..0]) read has four or more bit-in-error, the 20C532E EDAC develops a non controlled syndrome. This syndrome can take any value, from 0x00 (No Error Detected) to specific syndrome value of single bit-in-error . Example : If the data read = 0x00000000 instead of 0xFFFFFFFF, the generated syndrome is 0x00. Then, no error flag is actived. 7.6. 4-Bit Wide Memory Error The 7 checkbit code can be used to provide error detection for up to four errors occuring in the following fields: D D D D D D D D D D D [31..28], D [27..24], D [23..20], D [19..16], D [15..12], D [11..8], D [7..4], D [3..0], C [6..4], C [3..0]. The 29C532E EDAC can flag any number of errors in 4-bit wide memory chip. If the one device returns from one to four bit-in error, the CERR and NCERR flags are generated following the error type and the generated syndrome takes a value which never overlaps the code of a single bit-in-error. This is a restriction to triple and multi bit-in-error. Example : If the device controlling D [23..20] generates error, the 15 possible codes are different of 0x00 and of those describing a single bit-in-error. Bit in error 23 22 21 20 23 22 0x24 x 23 21 0x59 x 23 20 0x4B x 22 21 0x7D x 22 20 0x67 x 21 20 0x12 x 23 22 21 0x15 x 23 22 20 0x07 x 23 21 20 0x00 x 22 21 20 0x7A x 23 22 21 20 0x36 x SY CERR NCERR 0x68 x - 0x4C x - 0x31 x - 0x23 x - 8. 8-Bit Syndrome Word This feature is available when the N39 pin is driven at a low level. 8.1. No Error If there is no error in the read data or checkbit, all the syndrome word is "00". The EDAC flags are inactive. No Error SY= 0x00 12 Rev. B - 26 February, 1997 Preliminary Information 29C532E 8.2. Single Bit-In-Error When the Memory Data word (D [31..0] & C[7..0]) read has one bit-in-error, the 20C532E EDAC develops a code (syndrome) which indicates the bit in error (each bit have its own syndrome value). In this case, the syndrome decoder sets low the correctable error flag CERR, but NCERR flag remains at high level. In case of single bit-error on D [31..0], if the control lines SYNCHK = non active and CORRECT = active, the Table 6: 8-bit syndrome word for single bit-error. corrected value (CDO [31..0]) is available on DO [31..0] internal bus and the syndrome word is available on CO [7..0]. The corrected value is obtains to complement the bit-in-error. In same conditions, if a single bit-error occurs on C [7..0], the corrected value of the checkbit is not available in the device. D[31..16] SY 31 0x6D 30 0x5B 29 0x51 28 0x43 27 0xD8 26 0xB4 25 0xB2 24 0x93 23 0x68 22 0xCC 21 0xB1 20 0x23 19 0x5D 18 0x64 17 0xD2 16 0xC6 D[15..0] SY 15 0x4F 14 1x 12 0x9A 11 0xE0 10 0x3D 9 0x3B 8 0x2F 7 6 5 0x25 4 0x1F 3 0x16 2 0x54 1 0xC5 0 0xB8 0xAC 0x2A 0xCA 0xA6 C[7..0] SY 7 0x80 6 0x40 5 0x20 4 0x10 3 0x08 2 0x04 1 0x02 0 0x01 8.3. Double Bit-In-Error When the Memory Data word (D [31..0] & C[7..0]) read has two bit-in-error, the 20C532E EDAC develops a syndrome different of 0x00. The syndrome value generated by a double bit-in-error never takes place of a syndrome value generated by a single bit-in-error. In this case, the syndrome decoder sets low the non correctable error flag NCERR and CERR flag remains at high level. Example: If data D [24] and D [3] are incorrect, syndrome bit SY [7, 2, 0] are set to one (SY= 0x85), NCERR flag is set low (CERR flag remains at high level). 8.4. Triple Bit-In-Error When the Memory Data word (D [31..0] & C[7..0]) read has three bit-in-error, the 20C532E EDAC develops a syndrome different of 0x00. The syndrome value generated by a triple bit-in-error can have any value, even a syndrome value normally generated by a single bit-in-error. NCERR flag or CERR flag can be activated following the value of the generated syndrome. Example : If data D [25], D [20] and D [6] are incorrect, syndrome bit SY [5, 4, 2, 1, 0] are set to one (SY= 0x37), NCERR flag is set low (CERR flag remains at high level). Fault example: If data D [30], D [15] and D [0] are incorrect, syndrome bits SY [7, 5, 3, 2] are set to one (SY= 0xAC). The syndrome is decoded by the 29C532E EDAC has being a correctable error on D [14]. Then, CERR flag is set low and NCERR flag remains at high level. A correction would cause more errors. 8.5. Multi Bit-In-Error When the Memory Data word (D [31..0] & C[7..0]) read has four or more bit-in-error, the 20C532E EDAC develops a non controlled syndrome. This syndrome can take any value, from 0x00 (No Error Detected) to specific syndrome value of single bit-in-error . Rev. B - 26 February, 1997 Example: If the data read = 0x00000000 instead of 0xFFFFFFFF, the generated syndrome is 0x00. Then, no error flag is actived. 13 Preliminary Information 29C532E 8.6. 4-Bit Wide Memory Error The 8 checkbit code can be used to provide error detection for up to four errors occuring in the following fields: D D D D D D D D D D D [31..28], D [27..24], D [23..20], D [19..16], D [15..12], D [11..8], D [7..4], D [3..0], C [7..4], C [3..0]. The 29C532E EDAC can flag any number of errors in 4-bit wide memory chip. If the one device returns from one to four bit-in error, the CERR and NCERR flags are generated following the error type and the generated syndrome takes a value which never overlaps the code of a single bit-in-error. This is a restriction to triple and multi bit-in-error. Example : If the device controlling D [7..4] generates error, the 15 possible codes are different of 0x00 and of those describing a single bit-in-error. Bit in error 7 6 5 4 7 6 0x6C x 7 5 0xEF x 7 4 0xD5 x 6 5 0x83 x 6 4 0xB9 x 5 4 0x3A x 7 6 5 0x49 x 7 6 4 0x73 x 7 5 4 0xF1 x 6 5 4 0x9C x 7 6 5 4 0x56 x SY CERR NCERR 0xCA x - 0xA6 x - 0x25 x - 0x1F x - 8.7. 8-Bit Wide Memory Error The 8 checkbit code can be used to provide error detection for up to eight errors occuring in the following fields: D D D D D D [31..24], D [23..16], D [15..8], D [7..0], C [7..0]. The 29C532E EDAC can flag any number of errors in 8-bit wide memory chip. If the one device returns from one to eight bit-in error, the CERR and NCERR flags are generated following the error type and the generated syndrome takes a value which never overlaps the code of a single bit-in-error. This is a restriction to triple and multi bit-in-error. 14 Rev. B - 26 February, 1997 Preliminary Information 29C532E 9. Transactions 9.1. Control The controller guides The data flow in the 29C532E EDAC. This data flow control defines the value of the output buses DO [31..0] & CO [7..0] and the checkbit bus RCB [7..0]: D SYNCHK and CORRECT control flow on DO [31..0], D OLE/CHK and DIAG [0] control flow on CO [7..0], D DIAG [1] controls flow on RCB [7..0]. Table 7: Data Flow Control SYNCHK High DO [31..0] High Low CORRECT High Low x Connected to ... CDO [31..0] DI [31..0] DIA [7..0] // SY [7..0] // CI [7..0] // DIA[7..0] OLE/CHK Low CO [7..0] High x DIAG [0] Low Low High Connected to ... GCB [7..0] SY [7..0] DIA [7..0] DIAG [1] Low RCB [7..0] High Connected to ... CI [7..0] DIA [7..0] Eight signals are used to supervise the transactions : D DOE [3..0] control Data Output Buffers, D COE control Checkbit Output Buffer. D OLE/CHK controls Data Output Latch, D ILE controls Checkbit and Data Input Latchs, D DLE controls Diagnostic Input Latch. Rev. B - 26 February, 1997 15 Preliminary Information 29C532E 9.2. Memory Write SYNCHK CORRECT OLE/CHK DOE [3..0] Data-Out LATCH GCB [7..0] DO [31..0] D [31..24] D [23..16] D [15..8] D [7..0] Data BUFFER CHECKBIT GENERATOR Data-In LATCH DI [31..0] RCB [7..0] ILE Chk-In LATCH SYNDROME GENERATOR CONTROL Checkbit BUFFER CI [7..0] SY [7..0] CO [7..0] C [7..0] Diagnosis LATCH CDO [31..0] DIA [7..0] COE SYNDROME DECODER DLE DIAG [1] DIAG [0] N39 CERR NCERR SYNCHK High CORRECT High OLE/CHK Low DOE [3..] High ILE HL COE Low DLE Low DIAG [1] Low DIAG [0] Low N39 H or L 16 Rev. B - 26 February, 1997 Preliminary Information 29C532E 9.3. Memory Read ... Till Error Generation SYNCHK CORRECT OLE/CHK DOE [3..0] Data-Out LATCH CHECKBIT GENERATOR D [31..24] D [23..16] D [15..8] D [7..0] Data BUFFER Data-In LATCH DI [31..0] RCB [7..0] ILE Chk-In LATCH SYNDROME GENERATOR CONTROL Checkbit BUFFER CI [7..0] C [7..0] Diagnosis LATCH COE SYNDROME DECODER DLE DIAG [1] DIAG [0] N39 CERR NCERR SYNCHK High CORRECT High OLE/CHK Low DOE [3..] High ILE HL COE High DLE Low DIAG [1] Low DIAG [0] Low N39 H or L Rev. B - 26 February, 1997 17 Preliminary Information 29C532E 9.4. Memory Read (continue) ... With Correction - Single Bit-in-error SYNCHK CORRECT OLE/CHK DOE [3..0] Data-Out LATCH D [31..24] D [23..16] D [15..8] D [7..0] Data BUFFER DO [31..0] CHECKBIT GENERATOR Data-In LATCH DI [31..0] RCB [7..0] ILE Chk-In LATCH SYNDROME GENERATOR CONTROL Checkbit BUFFER CI [7..0] SY [7..0] CO [7..0] C [7..0] Diagnosis LATCH COE CDO [31..0] SYNDROME DECODER DLE DIAG [1] DIAG [0] N39 CERR NCERR SYNCHK High CORRECT High OLE/CHK LM(*) DOE [3..] High ILE Low COE Low DLE Low DIAG [1] Low DIAG [0] Low N39 H or L (*) when OLE/CHK = H, then CO [7..0] = SY [7..0] (placed in schematic), when OLE/CHK = I, then CO [7..0] = GCB [7..0] 18 Rev. B - 26 February, 1997 Preliminary Information 29C532E 9.5. Byte Memory Write - Read Modify Write A) 32-bit Data Memory + Checkbit Read DOE CORRECT OLE/CHK SYNCHK COE DLE ILE DIAG N39 [1] [0] [0] [0] X C [7..0] In CHECKBIT GENERATOR SYNDROME GENERATOR SYNDROME DECODER [3] [2] [1] [0] H H L H H H H HL H L D [31..24] [23..16] [15..8] [7..0] In In In In SYNCHK CORRECT OLE/CHK DOE [3..0] D [31..24] D [23..16] D [15..8] D [7..0] ILE CONTROL C [7..0] COE DLE DIAG [1] DIAG [0] N39 CERR NCERR Rev. B - 26 February, 1997 19 Preliminary Information 29C532E B) Preparing of 32-bit Corrected Data DOE CORRECT OLE/CHK SYNCHK COE DLE ILE DIAG N39 [1] [0] [0] [0] X C [7..0] In CHECKBIT GENERATOR SYNDROME GENERATOR SYNDROME DECODER [3] [2] [1] [0] H HLHH H H H L H L D [31..24] [23..16] [15..8] [7..0] In In In In SYNCHK CORRECT OLE/CHK DOE [3..0] D [31..24] D [23..16] D [15..8] D [7..0] ILE CONTROL C [7..0] COE DLE DIAG [1] DIAG [0] N39 CERR NCERR 20 Rev. B - 26 February, 1997 Preliminary Information 29C532E C) 8-bit Data Memory + Checkbit Write DOE CORRECT OLE/CHK SYNCHK COE DLE ILE DIAG N39 [1] [0] [0] [0] X [3] [2] [1] [0] H H HL L L L H HL L L D [31..24] [23..16] [15..8] [7..0] C [7..0] In-Out In-Out In-Out In Out SYNCHK CORRECT OLE/CHK DOE [3..0] D [31..24] D [23..16] D [15..8] D [7..0] CONTROL CHECKBIT GENERATOR ILE SYNDROME GENERATOR C [7..0] COE SYNDROME DECODER DLE DIAG [1] DIAG [0] N39 CERR NCERR Rev. B - 26 February, 1997 21 Preliminary Information 29C532E 10. Signal Timing 10.1. Memory Write tsu1 user word tpd1 tpd16 tpd9 ton th1 D [31..0] toff generated checkbit C [7..0] COE tpw ILE OLE/CHK tsu 1 Max (ns) min (ns) 6 th 1 tpd 1 30 tpd 16 38 tpd 9 20 ton 14 toff 14 tpw 5 5 22 Rev. B - 26 February, 1997 Preliminary Information 29C532E 10.2. Memory Read D [31..0] memory word C [7..0] memory word ILE tpd18 tpd7 tpd3 CERR tpd19 tpd6 tpd4 NCERR valid error flag valid error flag tpd 18 Max (ns) min (ns) 41 tpd 7 32 tpd 3 34 tpd 19 45 tpd 8 35 tpd 4 37 Rev. B - 26 February, 1997 23 Preliminary Information 29C532E 10.3. Memory Read With Correction CORRECT tpd11 tpd6 tpd10 tpd2 ton memory word corrected data D [31..0] DOE [3..0] tpd1 tpd5 tpd9 tsu1 ton C [7..0] COE tsu1 ILE tpd3 tpd7 CERR tpd4 tpd8 NCERR checkbit syndrome OLE/CHK tpd 11 Max (ns) min (ns) 20 tpd 6 38 tpd 10 18 tpd 2 39 ton 14 tpd 1 30 tpd 5 29 tpd 9 20 tsu 1 tpd 3 34 tpd 7 32 tpd 4 37 tpd 8 35 6 24 Rev. B - 26 February, 1997 Preliminary Information 29C532E 10.4. Memory Byte Write (Read Modify Write) DOE [0] DOE [2..0] tsu1 th1 tpd2 tpd6 ton D [31..8] memory (corrected) memory D [7..0] memory tsu2 tsu3 tpd1 tpd1 new byte from user C [7..0] COE memory ton tpd16 gen. checkbit tsu1 ILE OLE/CHK tpd7 tpd3 CERR tpd8 tpd4 NCERR tpw tsu 1 Max (ns) min (ns) 6 th 1 tpd 2 39 tpd 6 38 ton 14 tsu 2 tsu 3 5 34 32 tpd 1 Max (ns) min (ns) 30 tpd 16 38 tpw tpd 7 32 tpd 3 34 tpd 8 35 tpd 4 37 5 The information contained herein is subject to change without notice. No responsibility is assumed by Atmel Wireless & Microcontrollers for using this publication and/or circuits described herein : nor for any possible infringements of patents or other rights of third parties which may result from its use. Rev. B - 26 February, 1997 25 Preliminary Information |
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