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PIC17C7XX
EPROM Memory Programming Specification
This document includes the programming specifications for the following devices:
* PIC17C752 * PIC17C756 The PIC17C7XX requires two programmable power supplies, one for VDD (2.5V to 6.0V recommended) and one for VPP (13 0.25V). Both supplies should have a minimum resolution of 0.25V. The PIC17C7XX uses an intelligent algorithm. The algorithm calls for program verification at VDDmin as well as VDDmax. Verification at VDDmin guarantees good "erase margin". Verification at VDDmax guarantees good "program margin". Three times (3X) additional pulses will increase program margin then beyond VDDmax and insure safe operation in user system. The actual programming must be done with VDD in the VDDP range (4.75 - 5.25V). VDDP = VDD range required during programming. VDDmin. = minimum operating VDD spec. for the part. VDDmax. = maximum operating VCC spec for the part. Programmers must verify the PIC17C7XX at its specified VDDmax and VDDmin levels. Since Microchip may introduce future versions of the PIC17C7XX with a broader VDD range, it is best that these levels are user selectable (defaults are ok). Note: Any programmer not meeting these requirements may only be classified as "prototype" or "development" programmer but not a "production" quality programmer.
1.0
PROGRAMMING THE PIC17C7XX
The PIC17C7XX is programmed using the TABLWT instruction. The table pointer points to the internal EPROM location start. Therefore, a user can program an EPROM location while executing code (even from internal EPROM). This programming specification applies to PIC17C7XX devices in all packages. For the convenience of a programmer developer, a "program & verify" routine is provided in the on-chip test program memory space. The program resides in ROM and not EPROM, therefore, it is not erasable. The "program/verify" routine allows the user to load any address, program a location, verify a location or increment to the next location. It allows variable programming pulse width. The PIC17C7XX group of the High End Family has added a feature that allows the serial programming of the device. This is very useful in applications where it is desirable to program the device after it has been manufactured into the users system (In-circuit Serial Programming (ISP)). This allows the product to be shipped with the most current version of the firmware, since the microcontroller can be programmed just before final test as opposed to before board manufacture. Devices may be serialized to make the product unique, "special" variants of the product may be offered, and code updates are possible. This allows for increased design flexibility.
1.1
Hardware Requirements
Since the PIC17C7XX under programming is actually executing code from "boot ROM," a clock must be provided to the part. Furthermore, the PIC17C7XX under programming may have any oscillator configuration (EC, XT, LF or RC). Therefore, the external clock driver must be able to overdrive pulldown in RC mode. CMOS drivers are required since the OSC1 input has a Schmitt trigger input with levels (typically) of 0.2 VDD and 0.8 VDD. See the PIC17C5X data sheet (DS30264) for exact specifications.
(c) 1997 Microchip Technology Inc.
DS30274A-page 1
PIC17C7XX
Pin Diagram
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 RD1/AD9 RD0/AD8 RE0/ALE RE1/OE RE2/WR RE3/CAP4 MCLR/VPP TEST NC VSS VDD RF7/AN11 RF6/AN10 RF5/AN9 RF4/AN8 RF3/AN7 RF2/AN6 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 RA0/INT RB0/CAP1 RB1/CAP2 RB3/PWM2 RB4/TCLK12 RB5/TCLK3 RB2/PWM1 VSS NC OSC2/CLKOUT OSC1/CLKIN VDD RB7/SDO RB6/SCK RA3/SDI/SDA RA2/SS/SCL RA1/T0CKI
TABLE 1-1:
PIN DESCRIPTIONS (DURING PROGRAMMING IN PARALLEL MODE): PIC17C7XX
During Programming
Pin Name RA4:RA0 TEST PORTB<7:0> PORTC<7:0> MCLR/VPP VDD VSS
Pin Name RA4:RA0 TEST DAD15:DAD8 DAD7:DAD0 VPP VDD VSS
RF1/AN5 RF0/AN4 AVDD AVSS RG3/AN0/VREF+ RG2/AN1/VREFRG1/AN2 RG0/AN3 NC VSS VDD RG4/CAP3 RG5/PWM3 RG7/TX2/CK2 RG6/RX2/DT2 RA5/TX1/CK1 RA4/RX1/DT1
RD2/AD10 RD3/AD11 RD4/AD12 RD5/AD13 RD6/AD14 RD7/AD15 RC0/AD0 VDD NC VSS RC1/AD1 RC2/AD2 RC3/AD3 RC4/AD4 RC5/AD5 RC6/AD6 RC7/AD7 Top View 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Pin Type I I I/O I/O P P P
Pin Description Necessary in programming mode Must be set to "high" to enter programming mode Address & data: high byte Address & data: low byte Programming Power Power Supply Ground
Legend: I = Input, O = Output, P = Power
DS30274A-page 2
(c) 1997 Microchip Technology Inc.
PIC17C7XX
2.0 PARALLEL MODE PROGRAM ENTRY
2.1 Program/Verify Mode
To execute the programming routine, the user must hold TEST pin high, RA2, RA3 must be low and RA4 must be high (after power-up) while keeping MCLR low and then raise MCLR pin from VIL to VDD or VPP. This will force FFE0h in the program counter and execution will begin at that location (the beginning of the boot code) following reset. Execution is forced to Internal mode by overriding the fuse configuration. The code protect bit is not overwritten. The program immediately polls PORTB<7:0> to determine a branch address. Presenting E1h on PORTB will cause the program to jump to and execute the "program/verify" routine. The program/verify mode is intended for full-feature programmers. This mode offers the following capabilities: a) b) c) d) Load any arbitrary 16-bit address to start program and/or verify at that location. Increment address to program/verify the next location. Allows arbitrary length programming pulse width. Following a "verify" allows option to program the same location or increment and verify the next location. Following a "program" allows options to program the same location again, verify the same location or to increment and verify the next location.
e)
Note:
The Oscillator must not have 72 OSC clocks while the device MCLR is between VIL and VIHH.
All unused pins during programming are in hi-impedance state. PORTB (RB pins) has internal weak pull-ups which are active during the programming mode. When the TEST pin is high, the Power-up timer (PWRT) and Oscillator Start-up Timers (OST) are disabled.
FIGURE 2-1:
PROGRAMMING/VERIFY STATE DIAGRAM
Pulse RA1 Increment Address
Reset
Jump to Program Routine
Pulse RA1 Load Address Reset
Pulse RA1
Pulse RA1 (Raise RA1 after RA0)
RA0
Raise RA1 before RA0
Program
Pulse RA0 (RA0 pulse width is programming time)
(c) 1997 Microchip Technology Inc.
DS30274A-page 3
PIC17C7XX
2.1.1 LOADING NEW ADDRESS 2.1.3 PROGRAM CYCLE The program allows new address to be loaded right out of reset. A 16-bit address is presented on ports B (high byte) and C (low byte) and the RA1 is pulsed (0 1, then 1 0). The address is latched on the rising edge of RA1. See timing diagrams for details. After loading an address, the program automatically goes into a "verify cycle." To load a new address at any time, the PIC17C7XX must be reset and the programming mode re-entered. 2.1.2 VERIFY (OR READ) MODE "Program cycle" is entered from "verify cycle" or program cycle" itself. After a verify, pulsing RA0 will begin a program cycle. 16-bit data must be presented on PORTB (high byte) and PORTC (low byte) before RA0 is raised. The data is sampled 3 TCY cycles after the rising edge of RA0. Programming continues for the duration of RA0 pulse. At the end of programming, the user can choose one of three different routes. If RA1 is kept low and RA0 is pulsed again, the same location will be programmed again. This is useful for applying over programming pulses. If RA1 is raised before RA0 falling edge, then a verify cycle is started without address increment. Raising RA1 after RA0 goes low will increment address and begin verify cycle on the next address.
"Verify mode" can be entered from "Load address" mode, "program mode" or "verify mode." In verify mode pulsing RA1 will turn on PORTB and PORTC output drivers and output the 16-bit value from the current location. Pulsing RA1 again will increment location count and be ready for the next verify cycle. Pulsing RA0 will begin a program cycle.
FIGURE 2-2:
0000h
PIC17C7XX PROGRAM MEMORY MAP
On chip Program EPROM 7FFFh
FOSC0 FOSC1 WDTPS0 WDTPS1 PM0 Reserved PM1 Reserved Reserved
FE00h FE01h FE02h FE03h FE04h FE05h FE06h FE07h FE08h FE09h FE0Eh FE0Fh
FE00h FE0Fh
Configuration Word
Reserved BODEN PM2
FFFFh
DS30274A-page 4
(c) 1997 Microchip Technology Inc.
PIC17C7XX
3.0 PARALLEL MODE PROGRAMMING SPECIFICATIONS
PROGRAMMING ROUTINE FLOWCHART
Reset Reset No
FIGURE 3-1:
RA2 = 0 RA2 = 0 RA3 = 0 RA3 = 0 RA4 = 1 RA4 = 1
RA1 =0 Yes
MCLR MCLR==11 PORTB = 0xE1 B port 0xE1 (hold for 10 Tcy) (hold for 10TCY)
No
RA1 =1 Yes
Present address on ports Present address on ports RB, RC hold TCY RC hold Tcy after RA1 changes to after RA1 changes to 1 1
No
RA1 =0 Yes
No
RA1 RA1 = 0? =0 Yes
Read MSB of data from port-B. Read LSB of data from port-C. Enable RA0 to end prog cycle
B & C ports not driven by part
No
RA1 =1 Yes Program 16 bit data
If programming is desired, force port B = MSB of data force port C = LSB of data (hold 10Tcyc after RA0 is raised)
No
RA0 = 0 Yes RA1 =0 Yes Yes RA0= 1
Yes
RA0= 1 No RA1 =1 No Yes
Stop driving address on port
No
No Increment Address
Yes No RA1 =0 Yes No RA1 =1
No
RA1 =1 Yes
B port = xxx
- B port is forced by the part
B port = MSB of Data C port = LSB of Data
B port = xxx
- B port is tri-state, should be forced by user
Min RA1 high or low = 10 Tcy
(c) 1997 Microchip Technology Inc.
DS30274A-page 5
PIC17C7XX
FIGURE 3-2: RECOMMENDED PROGRAMMING ALGORITHM FOR USER EPROM
Start
Load new address Pulse-count = 0
Set VDD = VDD min
Verify blank
Pass Blank check?
No
Issue "Blank check fail" error message
Yes Load new data Programming error: Issue error message "Fail VDDmin/max" "Fail verify @ VDD min/max"
Set VDD = VDDmin
Set VDD = VDDP
Yes Program using 100s pulse increment pulse-count Pass? No
Set VDD = VDDmax Set VDD VDD max. Verify location(s)
Verify location for correct data
Set VDD = VDD min Set VDD = VDDmin Verify location
Yes Pass?
Apply (3 x Pulse-count) more 100 s programming pulses for margin (Over programming)
No
No
Pulsecount >25
Location fails programming, issue error message "Unable to program location"
DS30274A-page 6
(c) 1997 Microchip Technology Inc.
PIC17C7XX
FIGURE 3-3: RECOMMENDED PROGRAMMING ALGORITHM FOR CONFIGURATION WORDS
Start
Load new address Pulse-count = 0
Set VDD = VDDmin
Verify blank
Pass Blank check? Yes
No
Issue "blank check fail" error message
Load new data
Set VDD = VDDmin
Programming error: Issue error message "Fail verify @ VDDmin/max"
Set VDD = VDDP Yes Program using 100 s pulse increment pulse-count Pass? No
Yes
Pulse count <100 No
Set VDD = VDDmax Verify location(s)
Verify location for correct data
Set VDD = VDDmin Set VDD = VDDmin Verify location
Yes Pass? No
Location fails programming, issue error message "Unable to program location"
(c) 1997 Microchip Technology Inc.
DS30274A-page 7
PIC17C7XX
4.0
4.1
SERIAL MODE PROGRAM ENTRY
Hardware Requirements
4.2
Serial Program Mode Entry
Certain design criteria must be taken into account for ISP. Seven pins are required for the interface. These are shown in Table 4-1.
To place the device into the serial programming test mode, two pins will need to be placed at VIHH. These are the TEST pin and the MCLR/VPP pins. Also, the following sequence of events must occur: 1. 2. The TEST pin is placed at VIHH. The MCLR/VPP pin is placed at VIHH.
There is a setup time between step 1 and step 2 that must be meet (See "Electrical Specifications for Serial Programming Mode" on page 22.) After this sequence the Program Counter is pointing to Program Memory Address 0xFF60. This location is in the Boot ROM. The code initializes the USART/SCI so that it can receive commands. For this the device must be clocked. The device clock source in this mode is the RA1/T0CKI pin. Once the USART/SCI has been initialized, commands may be received. The flow is show in these 3 steps: 1. 2. 3. The device clock source starts. Wait 80 device clocks for Boot ROM code to configure the USART/SCI. Commands may be sent now.
Table 4-1:
ISP Interface Pins
During Programming
Name RA4/RX/DT RA5/TX/CK RA1/T0CKI TEST MCLR/VPP VDD VSS
Function DT CK OSCI TEST MCLR/VPP VDD VSS
Type I/O I I I P P P
Description Serial Data Serial Clock Device Clock Source Test mode selection control input. Force to VIHH, Master Clear reset and Device Programming Voltage Positive supply for logic and I/O pins Ground reference for logic and I/O pins
DS30274A-page 8
(c) 1997 Microchip Technology Inc.
PIC17C7XX
4.3 Software Commands
4.3.1 RESET PROGRAM MEMORY POINTER This feature is similar to that of the PIC16CXXX midrange family, but the programming commands have been implemented in the device Boot ROM. The Boot ROM is located in the program memory from 0xFF60 to 0xFFFF. The ISP mode is entered when the TEST pin has a VIHH voltage applied. Once in ISP mode, the USART/SCI module is configured as a synchronous slave receiver, and the device waits for a command to be received. The ISP firmware recognizes eight commands. These are shown in Table 4-1. This is used to clear the address pointer to the Program Memory. This ensures that the pointer is at a known state as well as pointing to the first location in program memory. 4.3.2 INCREMENT ADDRESS
This is used to increment the address pointer to the Program Memory. This is used after the current location has been programmed (or read).
TABLE 4-1:
ISP COMMANDS
Value 0000 0000 0000 0000 0000 0000 0000 0000 0000 0010 0100 0110 1000 1010 1100 1110
Command RESET PROGRAM MEMORY POINTER LOAD DATA READ DATA INCREMENT ADDRSS BEGIN PROGRAMMING LOAD ADDRESS READ ADDRESS END PROGRAMMING
FIGURE 4-1:
RESET ADDRESS POINTER COMMAND (PROGRAM/VERIFY)
RA1/OSCIN
VIHH
Test
VIHH
P2
MCLR/VPP
P1 1
P3 2 3 4 5 6 7 8
(NEXT COMMAND) 1 2
RA5 (Clock)
P6 P4 P5 0 0 0 0 0 0 0 0
RA4 (Data)
RA4 = Input
Reset
Program/Verify Test Mode
FIGURE 4-2:
INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)
RA1/OSCIN
VIHH
Test
VIHH
P2
MCLR/VPP
P1 1 2 3
P3 4 5 6 7 8
(NEXT COMMAND) 1 2
RA5 (Clock)
P6 P4 P5 0 1 1 0 0 0 0 0
RA4 (Data)
RA4 = Input
Reset
Program/Verify Test Mode
(c) 1997 Microchip Technology Inc.
DS30274A-page 9
PIC17C7XX
4.3.3 LOAD ADDRESS 4.3.4 READ ADDRESS This is used to load the address pointer to the Program Memory with a specific 16-bit value. This is useful when a specific range of locations are to be accessed. This is used so that the current address in the Program Memory pointer can be determined. This can be used to increase the robustness of the ISP programming (ensure that the Program Memory pointers are still in sync).
FIGURE 4-3:
RA1/OSCIN
VIHH
LOAD ADDRESS COMMAND
Test
VIHH
P2
MCLR/VPP
P1 1
P3 2 3 4 5 6 7 8 1 2 3 15 16
(NEXT COMMAND) 1
RA5 (Clock)
P7 P4 P5 0 1 0 1 0 0 0 0 P6
RA4 (Data)
RA4 = Input
Reset
Program/Verify Test Mode
FIGURE 4-4:
RA1/OSCIN
VIHH
READ ADDRESS COMMAND
Test
VIHH
P2
MCLR/VPP
P1 1 2
P3 3 4 5 6 7 8 1 2 3 15 16
(NEXT COMMAND) 1
RA5 (Clock)
P8 P4 P5 P9 P6
RA4 (Data)
0
0
1
1
0
0
0
0
RA4 = Input
Reset
RA4 = Output Program/Verify Test Mode
DS30274A-page 10
(c) 1997 Microchip Technology Inc.
PIC17C7XX
4.3.5 LOAD DATA 4.3.6 READ DATA This is used to load the 16-bit data that is to be programmed into the Program Memory location. The Program Memory address may be modified after the data is loaded. This data will not be programmed until a BEGIN PROGRAMMING command is executed. This is used to read the data in Program Memory that is pointed to by the current address pointer. This is useful for doing a verify of the programming cycle and can be used to determine the number for programming cycles that are required for the 3X overprogramming.
FIGURE 4-5:
RA1/OSCIN
VIHH
LOAD DATA COMMAND
Test
VIHH
P2 (NEXT COMMAND) 3 4 5 6 7 8 1 2 3 15 16 1
MCLR/VPP
P1 1
P3 2
RA5 (Clock)
P7 P4 P5 0 1 0 0 0 0 0 0 P6
RA4 (Data)
RA4 = Input
Reset
Program/Verify Test Mode
FIGURE 4-6:
RA1/OSCIN
VIHH
READ DATA COMMAND
Test
VIHH
P2
MCLR/VPP
P1 1 2
P3 3 4 5 6 7 8 1 2 3 15 16
(NEXT COMMAND) 1
RA5 (Clock)
P8 P4 P5 P9 0 0 1 0 0 0 0 0 P6
RA4 (Data)
RA4 = Input
Reset
RA4 = Output Program/Verify Test Mode
(c) 1997 Microchip Technology Inc.
DS30274A-page 11
PIC17C7XX
4.3.7 BEGIN PROGRAMMING 4.3.8 3X OVERPROGRAMMING This is used to program the current 16-bit data (last data sent with LOAD DATA Command) into the Program Memory at the address specified by the current address pointer. The programming cycle time is specified by specification P10. After this time has elasped, any command must be sent, which wakes the processor from the Long Write cycle. This command will be the next executed command. Once a location has been both programmed and verified over a range of voltages, 3X overprogramming should be applied. In other words, apply three times the number of programming pulses that were required to program a location in memory, to ensure a solid programming margin. This means that every location will be programmed a minimum of 4 times (1 + 3X overprogramming).
FIGURE 4-7:
BEGIN PROGRAMMING COMMAND (PROGRAM)
RA1/OSCIN
VIHH
Test
VIHH
P2
MCLR/VPP
P1 1 2 3
P3 4 5 6 7 8
(NEXT COMMAND) 1 2 7 8
RA5 (Clock)
P10 P4 P5 0 0 0 1 0 0 0 0
RA4 (Data)
RA4 = Input
Reset
Program/Verify Test Mode
DS30274A-page 12
(c) 1997 Microchip Technology Inc.
PIC17C7XX
FIGURE 4-8: RECOMMENDED PROGRAMMING FLOWCHART
START TEST = MCLR = VSS 4.75V < VDD < 5.25V
TEST = VIHH
MCLR = VIHH
Start Device Clock (on RA0), Wait x Instruction Cycles
ISP Command RESET ADDRESS ISP Command INCREMENT ADDRESS or LOAD ADDRESS
N=1
ISP Command LOAD DATA
ISP Command BEGIN PROGRAMMING
No N > 25?
Yes
Report Programming Failure
Wait approx 100 s
ISP Command READ DATA No N=N+1
Data Correct? Yes N = 3N
ISP Command BEGIN PROGRAMMING Verify all Locations @ VDDMIN No N=N-1 No Data Correct? Yes N = 0? Yes No Programmed all required locations? Yes Verify all Locations @ VDDMAX Yes Data Correct? No Report Verify Error @ VDDMAX Report Verify Error @ VDDMIN
Wait approx 100 s
DONE
(c) 1997 Microchip Technology Inc.
DS30274A-page 13
PIC17C7XX
5.0 CONFIGURATION WORD
Configuration bits are mapped into program memory. Each bit is assigned one memory location. In erased condition, a bit will read as '1'. To program a bit, the user needs to write to the memory address. The data is immaterial; the very act of writing will program the bit. The configuration word locations are shown in Table 5-3. The programmer should not program the reserved locations to avoid unpredictable results and to be compatible with future variations of the PIC17C4X. It is also mandatory that configuration locations are programmed in the strict order starting from the first location (0xFE00) and ending with the last (0xFE0F). Unpredictable results may occur if the sequence is violated. the configuration word (Table 5-2) into DAD<7:0> (PORTC). DAD<15:8> (PORTD) will be set to 0xFF. Reading a configuration location between 0xFE08 and 0xFE0F will place the high byte of the configuration word into DAD<7:0> (PORTC). DAD<15:8> (PORTD) will be set to 0xFF.
TABLE 5-1:
CONFIGURATION BIT PROGRAMMING LOCATIONS
Address 0xFE00 0xFE01 0xFE02 0xFE03 0xFE04 0xFE06 0xFE0E 0xFE0F
Bit FOSC0 FOSC1 WDTPS0 WDTPS1 PM0 PM1 BODEN PM2
5.1
Reading Configuration Word
The PIC17C5X has seven configuration locations (Table 5-1). These locations can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. Any write to a configuration location, regardless of the data, will program that configuration bit. Reading any configuration location between 0xFE00 and 0xFE07 will place the low byte of
TABLE 5-2:
15 1 15 1 14 1 14 1
READ MAPPING OF CONFIGURATION BITS
13 1 13 1 12 1 12 1 11 1 11 1 10 1 10 1 9 1 9 1 8 1 8 1 7 -- 7 PM2 6 PM1 5 -- 4 3 2 1 0 PM0 WDTPS1 WDTPS0 FOSC1 FOSC0 5 -- 4 -- 3 -- 2 -- 1 -- 0 --
6 BODEN
--=Unused PM<2:0>, Processor Mode Select bits 111 = Microprocessor mode 110 = Microcontroller mode 101 = Extended Microcontroller mode 000 = Code protected microcontroller mode BODEN, Brown-out Detect Enable 1 = Brown-out Detect Circuitry enabled 0 = Brown-out Detect Circuitry disabled WDTPS1:WDTPS0, WDT Prescaler Select bits. 11 = WDT enabled, postscaler = 0 10 = WDT enabled, postscaler = 256 01 = WDT enabled, postscaler = 64 00 = WDT disabled, 16-bit overflow timer FOSC1:FOSC0, Oscillator Select bits 11 = EC oscillator 10 = XT oscillator 01 = RC oscillator 00 = LF oscillator
DS30274A-page 14
(c) 1997 Microchip Technology Inc.
PIC17C7XX
5.2 Embedding Configuration Word Information in the Hex File
To allow portability of code, a PIC17C7XX programmer is required to read the configuration word locations from the hex file when loading the hex file. If the configuration word information was not present in the hex file, then a simple warning message may be issued. Similarly, while saving a hex file, all configuration word information must be included. An option to not include the configuration word information may be provided. When embedding configuration word information in the hex file, it should be to address FE00h. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.
TABLE 5-3:
CONFIGURATION WORD
PIC17C752 To code protect: * Protect all memory
0XXXXXXX0X0XXXX R/W in Protected Mode Read Scrambled, Write Enabled Read Scrambled, Write Disabled* R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
Program Memory Segment Configuration Word (0xFE00) All memory PIC17C756 To code protect: * Protect all memory
0XXXXXXX0X0XXXX R/W in Protected Mode Read Scrambled, Write Enabled Read Scrambled, Write Disabled* R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
Program Memory Segment Configuration Word (0xFE00) All memory
Legend: X = Don't care *Write to on-chip EPROM memory is disabled. The only way these locations can be programmed is if a TABLWT instruction is issued from an "on-chip" program memory space to program an on-chip memory location.
(c) 1997 Microchip Technology Inc.
DS30274A-page 15
PIC17C7XX
5.3 CHECKSUM COMPUTATION
The checksum is calculated by summing the following: * The contents of all program memory locations * The configuration word, appropriately masked * Masked ID locations (when applicable) The least significant 16 bits of this sum is the checksum. Table 5-4 describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently, depending on the code protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. Note: Some older devices have an additional value added in the checksum. This is to maintain compatibility with older device programmer checksums.
TABLE 5-4:
CHECKSUM COMPUTATION
Code Protect MP mode MC mode EMC mode PMC mode MP mode MC mode EMC mode PMC mode Blank Value 0xA05F 0xA04F 0xA01F 0x200F 0x805F 0x804F 0x801F 0x000F 0xC0DE at 0 and max address 0x221D 0x220D 0x21DD 0xE3D3 0x021D 0x020D 0x01DD 0xC3D3
Device PIC17C752
Checksum* SUM[0x0000:0x1FFF] + (CONFIG & 0xC05F) SUM[0x0000:0x1FFF] + (CONFIG & 0xC05F) SUM[0x0000:0x1FFF] + (CONFIG & 0xC05F) SUM_XNOR8[0x0000:0x1FFF] + (CONFIG & 0xC05F) SUM[0x0000:0x3FFF] + (CONFIG & 0xC05F) SUM[0x0000:0x3FFF] + (CONFIG & 0xC05F) SUM[0x0000:0x3FFF] + (CONFIG & 0xC05F) SUM_XNOR8[0x0000:0x3FFF] + (CONFIG & 0xC05F)
PIC17C756
Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a to b inclusive] SUM_XNOR8(a:b) = [Sum of 8-bit wide XNOR copied into upper and lower byte, of locations a to b inclusive] *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND
DS30274A-page 16
(c) 1997 Microchip Technology Inc.
PIC17C7XX
6.0 PARALLEL MODE AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE
+10C TA +70C, unless otherwise stated, (25C is recommended) 4.5V VDD 5.25V, unless otherwise stated. Characteristic Supply voltage during programming Supply current during programming Supply voltage during verify Min. 4.75 -- VDD min. 12.75 Typ. 5.0 -- -- Max. 5.25 50 VDD max. 13.25 Units V mA V Freq = 10MHz, VDD = 5.5V Note 3 Note 2 Conditions/Comments
Standard Operating Conditions Operating Temperature: Operating Voltage: Parameter No. PD1 PD2 PD3 PD4 PD6 P1 P2 P3 P4 P5 Sym. VDDP IDDP VDDV VPP
P6
P7 P8 P9 P10 P11 P12
P13
P14 P15 P16 P17 P18 P19 Note 1: 2: 3:
Voltage on VPP/MCLR pin -- V Note 1 during programming IPP Programming current on -- 25 50 mA Note 3 VPP/MCLR pin FOSCP Osc/clockin frequency dur4 -- 10 MHz ing programming TCY Instruction cycle 1 -- 0.4 s TCY = 4/FOSCP TIRV2TSH RA0, RA1, RA2, RA3, RA4 1 -- -- s setup before TEST TTSH2MCH TEST to MCLR 1 -- -- s TBCV2IRH RC7:RC0, RB7:RB0 valid 0 -- -- s ?PORTD vs. PORTB? AL? to RA1 or RA0:Address/ Data input setup time RA1 or RA0 to RB7:RB0, 10 TCY -- -- s ?PORTD vs. PORTB? AL? TIRH2BCL RC7:RC0 invalid; Address data hold time; -- -- 8TCY ?PORTD vs. PORTB? AL? T0CKIL2RBCZ RT to RB7:RB0, RC7:RC0 hi-impedance T0CKIH2BCV RA1 to data out valid -- -- 10 TCY TPROG Programming pulse width 10 100 1000 s TIRH2IRL RA0, RA1 high pulse width 10 TCY -- -- s TIRL2IRH RA0, RA1 low pulse width 10 TCY -- -- s T0CKIV2INL RA1 before INT (to go 0 -- -- s from prog cycle to verify w/o increment) 10 TCY -- RA1 valid after RA0 (to -- s TINL2RTL select increment or no increment going from program to verify cycle VPP setup time before RA0 100 -- -- s Note 1 TVPPS TVPPH VPP hold time after INT 0 -- -- s Note 1 TVDV2TSH VDD stable to TEST 10 -- -- ms TRBV2MCH RB input (E1h) valid to VPP/ 0 -- -- s MCLR TMCH2RBI RB input (E1h) hold after -- ns 10TCY -- VPP/MCLR TVPL2VDL VDD power down after VPP 10 -- -- ms power down VPP/MCLR pin must only be equal to or greater than VDD at times other than programming. Program must be verified at the minimum and maximum VDD limits for the part. These parameters are for design guidance only and are not tested nor characterized.
(c) 1997 Microchip Technology Inc.
DS30274A-page 17
FIGURE 6-1:
DS30274A-page 18
tvpps P14 tvppH
P15 P9
Test
13V
PIC17C7XX
VPP/MCLR
5V
P4
ttsH2mcH tirH2lrL P11 P10 tprog tirL2lrH INC ADDR
P3
tirV2tsH
RA1
P8 P7
P18
tra1H2bcV tra1L2bcZ
RA0
tmcH2rbL
P17
trbV2mcH ADDR_HI DATA_HI OUT DATA_HI OUT DATA_HI_IN DATA_HI OUT
RB<7:0>
E1H Jump Address Input ADDR_LO DATA_LO OUT DATA_LO OUT tbcV2irH
RC<7:0>
DATA_LO_IN
P5 P6
DATA_LO OUT
tirH2bcI
PARALLEL MODE PROGRAMMING AND VERIFY TIMINGS I
Verify location X + 1 Verify location X + 1
Programming Mode entry Load address X
Verify location X Increment address to X + 1 by pulsing RA1
Program location X + 1 Do not increment PC by raising RA1 before RA0
(c) 1997 Microchip Technology Inc.
Note: RA2 = 0 RA3 = 0 RA4 = 1
FIGURE 6-2:
Test
(c) 1997 Microchip Technology Inc.
P14 P15
13V 5V tvpps
P9 P9 P9
VPP/MCLR
tvppH
tprog
tprog
tprog
RA1
RA0
RB<7:0> ADDR_HI DATA_HI OUT DATA_HI_IN DATA_HI_IN
E1H Jump Address Input ADDR_LO DATA_LO_IN DATA_LO OUT DATA_LO_IN
DATA_HI_IN
DATA_HI OUT
RC<7:0>
DATA_LO_IN
DATA_LO OUT
PARALLEL MODE PROGRAMMING AND VERIFY TIMINGS II
Programming mode entry Load address X Verify location X
Program location X
Program location X Move to verify cycle Prevent increment of PC by raising RA1 before RA0
Verify location X
Note: RA2 = 0 RA3 = 0 RA4 = 1
PIC17C7XX
DS30274A-page 19
FIGURE 6-3:
DS30274A-page 20
P13 tinL2ra1l
tinL2ra1l tra1V2inL
P13
PIC17C7XX
P12
RA1 INC PC INC PC
INC PC
RA0
RB<7:0> DATA_HI OUT DATA_HI IN DATA_HI OUT DATA_HI IN
DATA_HI OUT
DATA_HI OUT
RC<7:0>
DATA_LO OUT
DATA_LO IN
DATA_LO OUT
DATA_LO IN
DATA_LO OUT
DATA_LO OUT
PARALLEL MODE PROGRAMMING AND VERIFY TIMINGS III
Verify location X
Program location X Do not increment PC Raise RA1 before RA0 to do this Verify location X
Program location X Raise RA1 after RA0 to increment to location X +1
Verify location X +1 Pulse RA1 to increment address to X +2
Verify location X +2
Note: Device in PGM mode Test = +5 VPP/MCLR = VPP RA2 = 0 RA3 = 0 RA4 = 1
(c) 1997 Microchip Technology Inc.
PIC17C7XX
FIGURE 6-4: POWER-UP/DOWN SEQUENCE FOR PROGRAMMING
VDD tvcV2tsH P16 VPP/MCLR
tvpL2vcL P19
TEST
RA4
RA2
RA3
RA0
P3
tirV2tsH RB<7:0> trbV2mcH E1H
P17 P18 tmcH2rbI
(c) 1997 Microchip Technology Inc.
DS30274A-page 21
PIC17C7XX
7.0 ELECTRICAL SPECIFICATIONS FOR SERIAL PROGRAMMING MODE
Sym VIHH IPP FOSC TCY P1 P2 P3 P4 P5 P6 P7 TVH2VH TSER TSCLK TSET1 THLD1 TDLY1 TDLY2 Characteristic Programming Voltage on VPP/ MCLR pin and TEST pin. Programming current on MCLR pin Input OSC frequency on RA1 Instruction Cycle Time Setup time between TEST = VIHH and MCLR = VIHH Serial setup time Serial Clock period Input Data Setup Time to serial clock Input Data Hold Time from serial clock Delay between last clock to first clock of next command Delay between last clock of command byte to first clock of read of data word Delay between last clock of command byte to first clock of write of data word Data input not driven to next clock input Delay between last begin programming clock to last clock of next command (minimum programming time) Min 12.5 -- -- -- 1 20 1 15 15 20 20 Typ -- 25 -- 4/FOSC -- -- -- -- -- -- -- Max 13.5 50 8 -- -- -- -- -- -- -- -- s TCY TCY ns ns TCY TCY Units V mA MHz Conditions Parameter No.
P8
TDLY3
30
--
--
TCY
P9 P10
TDLY4 TDLY5
1 100
-- --
-- --
TCY s
*
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30274A-page 22
(c) 1997 Microchip Technology Inc.
PIC17C7XX
FIGURE 7-1: RESET ADDRESS POINTER COMMAND (PROGRAM/VERIFY)
RA1/OSCIN
VIHH
Test
VIHH
P2
MCLR/VPP
P1 1
P3 2 3 4 5 6 7 8
(NEXT COMMAND) 1 2
RA5 (Clock)
P6 P4 P5 0 0 0 0 0 0 0 0
RA4 (Data)
RA4 = Input
Reset
Program/Verify Test Mode
FIGURE 7-2:
INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)
RA1/OSCIN
VIHH
Test
VIHH
P2
MCLR/VPP
P1 1 2 3
P3 4 5 6 7 8
(NEXT COMMAND) 1 2
RA5 (Clock)
P6 P4 P5 0 1 1 0 0 0 0 0
RA4 (Data)
RA4 = Input
Reset
Program/Verify Test Mode
(c) 1997 Microchip Technology Inc.
DS30274A-page 23
PIC17C7XX
FIGURE 7-3:
RA1/OSCIN
VIHH
LOAD ADDRESS COMMAND
Test
VIHH
P2
MCLR/VPP
P1 1
P3 2 3 4 5 6 7 8 1 2 3 15 16
(NEXT COMMAND) 1
RA5 (Clock)
P7 P4 P5 0 1 0 1 0 0 0 0 P6
RA4 (Data)
RA4 = Input
Reset
Program/Verify Test Mode
FIGURE 7-4:
RA1/OSCIN
VIHH
READ ADDRESS COMMAND
Test
VIHH
P2
MCLR/VPP
P1 1 2
P3 3 4 5 6 7 8 1 2 3 15 16
(NEXT COMMAND) 1
RA5 (Clock)
P8 P4 P5 P9 P6
RA4 (Data)
0
0
1
1
0
0
0
0
RA4 = Input
Reset
RA4 = Output Program/Verify Test Mode
DS30274A-page 24
(c) 1997 Microchip Technology Inc.
PIC17C7XX
FIGURE 7-5:
RA1/OSCIN
VIHH
LOAD DATA COMMAND
Test
VIHH
P2 (NEXT COMMAND) 3 4 5 6 7 8 1 2 3 15 16 1
MCLR/VPP
P1 1
P3 2
RA5 (Clock)
P7 P4 P5 0 1 0 0 0 0 0 0 P6
RA4 (Data)
RA4 = Input
Reset
Program/Verify Test Mode
FIGURE 7-6:
RA1/OSCIN
VIHH
READ DATA COMMAND
Test
VIHH
P2
MCLR/VPP
P1 1 2
P3 3 4 5 6 7 8 1 2 3 15 16
(NEXT COMMAND) 1
RA5 (Clock)
P8 P4 P5 P9 0 0 1 0 0 0 0 0 P6
RA4 (Data)
RA4 = Input
Reset
RA4 = Output Program/Verify Test Mode
FIGURE 7-7:
BEGIN PROGRAMMING COMMAND (PROGRAM)
RA1/OSCIN
VIHH
Test
VIHH
P2
MCLR/VPP
P1 1 2 3
P3 4 5 6 7 8
(NEXT COMMAND) 1 2 7 8
RA5 (Clock)
P10 P4 P5 0 0 0 1 0 0 0 0
RA4 (Data)
RA4 = Input
Reset
Program/Verify Test Mode
(c) 1997 Microchip Technology Inc.
DS30274A-page 25
WORLDWIDE SALES & SERVICE
AMERICAS
Corporate Office
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ASIA/PACIFIC
Hong Kong
Microchip Asia Pacific RM 3801B, Tower Two Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431
EUROPE
United Kingdom
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France
Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Atlanta
Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307
India
Microchip Technology India No. 6, Legacy, Convent Road Bangalore 560 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062
Boston
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Korea
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Germany
Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Muchen, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Chicago
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Italy
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Shanghai
Microchip Technology RM 406 Shanghai Golden Bridge Bldg. 2077 Yan'an Road West, Hongiao District Shanghai, PRC 200335 Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
Dallas
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Singapore
Microchip Technology Taiwan Singapore Branch 200 Middle Road #10-03 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850
JAPAN
Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shin Yokohama Kohoku-Ku, Yokohama Kanagawa 222 Japan Tel: 81-4-5471- 6166 Fax: 81-4-5471-6122 5/8/97
Dayton
Microchip Technology Inc. Two Prestige Place, Suite 150 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175
Los Angeles
Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 714-263-1888 Fax: 714-263-1338
Taiwan, R.O.C
Microchip Technology Taiwan 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886 2-717-7175 Fax: 886-2-545-0139
New York
Microchip Technology Inc. 150 Motor Parkway, Suite 416 Hauppauge, NY 11788 Tel: 516-273-5305 Fax: 516-273-5335
San Jose
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
Toronto
Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253
All rights reserved. (c) 1997, Microchip Technology Incorporated, USA. 6/97 Printed on recycled paper.
M
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS30274A-page 26
(c) 1997 Microchip Technology Inc.

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