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| IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT FEATURES: - - - - - - - - - - - - - IDT49C465 IDT49C465A DESCRIPTION: The IDT49C465/A is a 32-bit, two-data bus, Flow-thruEDC unit. The chip provides single-error correction and two and three bit error detection of both hard and soft memory errors. It can be expanded to 64-bit widths by cascading two units, without the need for additional external logic. The Flow-thruEDC has been optimized for speed and simplicity of control. The EDC unit has been designed for use in either of two configurations in an error correcting memory system. The bidirectional configuration is most appropriate for systems using bidirectional memory buses. A second system configuration utilizes external octal buffers, and is well-suited for systems using memory with separate I/O buses. The IDT49C465/A supports partial word writes, pipelining, and error diagnostics. It also provides parity protection for data on the system side. 32-bit wide Flow-thruEDCTM unit, cascadable to 64 bits Single-chip 64-bit Generate Mode Separate system and memory buses On-chip pipeline latch with external control Supports bidirectional and common I/O memories Corrects all single-bit errors Detects all double-bit errors and some multiple bit errors Error Detection Time -- 12ns Error Correction Time -- 14ns On chip diagnostic registers Parity generation and checking on system data bus Low power CMOS -- 100mA typical at 20MHz 144-pin PGA and PQFP packages SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM M D0-31 Correct Logic MD Latch M em ory Checkbit Generator Syndrom e G enerator MLE CBI0-7 Checkbit Latch ERR Expansion Logic Mux Detect Logic MERR PCBI0-7 SD0-31 Pipeline Latch CONTROL CONTROL Byte M ux SD Latch SLE System Checkbit Generator M ux CBO0-7 PLE CONTROL CONTROL COMMERCIAL TEMPERATURE RANGE 1 c 1999 Integrated Device Technology, Inc. The IDT logo is a registered trademark of Integrated Device Technology, Inc. NOVEMBER 2000 DSC-2552/9 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION 72 Vcc SD 5 SD 6 SD 7 SD 8 SD 9 SD 10 SD 11 GND BE1 SD 12 SD 13 SD 14 SD 15 SLE PLE SO E GND SD 16 SD 17 SD 18 SD 19 BE2 SD 20 SD 21 SD 22 GND SD 23 SD 24 SD 25 SD 26 SD 27 BE3 SD 28 Vcc Vcc 73 Vcc SD 4 BE0 SD 3 SD 2 SD 1 SD 0 PC BI7 PC BI6 PC BI5 PC BI4 PC BI3 PC BI2 PC BI1 PC BI0 CODE ID 1 CODE ID 2 GND GND M OD E 1 M OD E 0 M ERR ER R SYO7 SYO6 SYO5 SYO4 GND SYO3 SYO2 SYO1 SYO0 MD0 MD1 MD2 Vcc 37 36 Vcc Vcc MD3 MD4 MD5 MD6 MD7 MD8 MD9 GND M D 10 M D 11 M D 12 M D 13 M D 14 M D 15 M LE MOE GND M D 16 M D 17 M D 18 M D 19 M D 20 M D 21 M D 22 M D 23 GND M D 24 M D 25 M D 26 M D 27 M D 28 M D 29 M D 30 Vcc 49C465Y PQ144-2 108 109 144 1 Vcc SD 29 SD 30 SD 31 CBO 0 CBO 1 CBO 2 CBO 3 CBOE CBO 4 CBO 5 CBO 6 CBO 7 PSEL PE RR P3 P2 GND GND P1 P0 M OD E 2 SYN CLK SCLKE N CLEAR CBI0 CBI1 CBI2 CBI3 GND CBI4 CBI5 CBI6 CBI7 M D 31 Vcc PQFP TOP VIEW 2 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION 15 Vcc SD 2 PC BI6 PC BI5 PC BI3 COD E CO D E M OD E ME RR ER R ID 1 ID 2 1 M OD E SYO 6 0 G ND SYO 7 SYO 5 SYO 3 SYO 1 MD 1 Vcc 14 SD 6 SD 4 SD 1 PC BI7 PC BI4 PC BI1 PC BI0 SYO4 SY O2 M D 0 MD 2 Vcc MD5 13 SD 9 SD 5 BE0 SD 3 SD 0 PC BI2 G ND G ND SYO 0 Vcc MD 3 MD 6 MD9 12 SD 11 SD 7 Vcc MD 4 MD8 G ND 11 SD 12 SD 10 SD 8 MD 7 M D 10 MD 11 10 SD 15 BE1 G ND M D 12 M D 13 MD 15 9 SLE SO E SD 13 PLE SD 14 G ND G 144-2 MO E M D 14 G ND M D 17 MLE 8 MD 16 7 SD 17 SD 19 SD 16 M D 20 M D 21 MD 18 6 SD 18 BE2 SD 20 G ND M D 23 MD 19 5 SD 21 SD 22 SD 25 NC* M D 27 M D 25 MD 22 4 G ND SD 24 BE3 Vcc SC LK G ND EN M D 28 MD 24 3 SD 23 SD 26 SD 28 Vcc CB 00 CBO E CB07 G ND GND CB16 CB17 M D 30 MD 26 2 SD 27 Vcc SD 29 SD 31 CB 02 CB 04 CB06 P3 M O D E SYN CB10 2 CLK P1 J P0 K CB13 CB14 M D 31 MD 29 1 Vcc A SD 30 B CB 01 C CB03 CB 05 D E PSEL PERR F G P2 CLEAR CB11 L M CB12 CB15 N P Vcc R H * = Tied to Vcc internally PGA (CAVITY UP) TOP VIEW 3 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE DETAILED FUNCTIONAL BLOCK DIAGRAM D ash ed L ine = Diagnostic path PCB I0-7 ERR M ERR ER RO R DETECT 8 M U X INTERNAL FINA L SYN DR O M E 8 8 8 8 SYO 0-7 8 M U X SYN DR OM E G ENERATO R 8 8 M U X CH ECK BIT LATC H 8 M U X 8 CBI0-7 PLE SO E BE0-3 8 MD C HECKBIT G ENE RATO R MD LATCH M LE ERRO R CO RR ECT M U X 1 OF 4 BYTES PIPE LATCH ERRO R D ATA LATCH CLEAR M D0-31 DIAG NO STIC LATCH ES INTERN AL SYN CL K SD0-31 BYTE M U X SD LATCH MOE SL E PS EL BE0-3 4 4 4 4 PAR ITY GEN P0-3 SD CHE CKB IT GENERATOR 8 PAR ITY CHE CK M U X SD C HECKBIT G ENE RATO R M U X 8 8 CBO 0-7 CBO E PE RR 8 /ER R 8 INTERN AL SYN CLK SYN CLK SC LKE N CLEAR PCBI0-7 COD E ID 0,1 M O DE0-2 2 3 CONTRO L LO G IC 4 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE SYSTEM CONFIGURATIONS The IDT49C465 EDC unit can be used in various configurations in an EDC system. The basic configurations are shown below. Figure 1 illustrates a bidirectional configuration, which is most appropriate for systems using bidirectional memory buses. It is the simplest configuration to understand and use. During a correction cycle, the corrected data word can be simultaneously output on both the system bus and memory bus. During partial-word-write operations, the new bytes are internally combined with the corrected old bytes for checkbit memory. Partial word-write bytes are combined externally for writing and checkbit generation. Figure 3 illustrates a third configuration which uses external buffers and is also well-suited for systems using memory with separate I/O MEMORY INPUT BUS CHECKBIT I/O MEMORY OUTPUT BUS CPU I/O SD MD M EM ORY I/O CBO SD CBI MD EDC EDC CBI CHECKBITS CBO EXT. BUFFER CPU BUS EXT. BUFFER Figure 1. Common I/O Configuration Figure 3. Bypassed Separate I/O Configuration generation and writing to memory. Figure 2 illustrates a separate I/O configuration. This is appropriate for systems using separate I/O memory buses. This configuration allows separate input and output memory buses to be used. Corrected data is output on the SD outputs for the system and for re-write to EXT. BUFFER buses. Since data from memory does not need to pass through the part on every cycle, the EDC system may operate in "bus-watch" mode. As in the separate I/O configuration, corrected data is output on the SD outputs. Figure 4 illustrates the single-chip generate-only mode for the very fast 64-bit checkbit generation in systems that use separate checkbitgenerate and detect-correct units. If this is not desired, 64-checkbit generation and correction can be done with just two EDC units. 64-bit correction is also straightforward, fast, and requires no extra hardware for the expansion. CHECK BITS OUT MEMO RY INPUT BUS CBO CBI MEMO RY INPUT BUS CHECK BITS IN MEMO RY OUTPUT BUS CPU M EMORY INPUTS SD MD EDC BUFFER MEMO RY OUTPUTS 64-BIT G EN. ONLY LOW ER DATA UPPER DATA EDC EDC BUFFER BUFFER EDC BUFFER CBI CBO Figure 2. Separate I/O Configuration CHECKBITS CPU BUS Figure 4. Separate generate/Correction Units with 64-Bit Checkbit Generation 5 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE FUNCTIONAL DESCRIPTION The error detection/correction codes consist of a modified Hamming code; it is identical to that used in the IDT49C460. 32-BIT MODE (CODE ID 1,0 = 00) Vcc 8 PCBI CBI7 CHECKBITS-IN 7 CBI0-6 SYO 7 SYND ROME-OUT CBO 7 CHECKBITS-OUT EDC Figure 5. 32-Bit Mode 64-BIT MODE (CODE ID 1,0 = 10 & 11) The expansion bus topology is shown in Figure 6. This topology allows the syndrome bits used by the correction logic to be generated simultaneously in both parts used in the expansion. During a 64-bit detection or correction operation, "Partial-Checkbit" data and "PartialSyndrome" data is simultaneously exchanged between the two EDC units in opposite directions on dedicated expansion buses. This results in very short 64-bit detection and correction times. 8 PAR TIAL-CHECKBITS-OUT (11) (CORRECTION ONLY) PC BI CBO PCBI CBO 8 PAR TIAL-CHECKBITS-OUT (10) (GENERATE ONLY) 8 PAR TIAL-SYNDROM E (DETECT/COR RECT ONLY) 8 FINAL CHEC KBITS-OUT CHECKBITS-IN 8 CBI SYO CBI SYO ERR (DETECT AN D CORRECT) LOW ER EDC (CODE ID 1,0 = 10) UPPER ED C (C OD E ID 1,0 = 11) Figure 6. 64-Bit Mode -- 2 Cascaded IDT49C465 Devices 64-BIT GENERATE-ONLY MODE (CODE ID 1,0 = 01) If the identity pins CODE ID 1,0 = 01, a single EDC is placed in the 64bit "Generate-only" mode. In this mode, the lower 32 bits of the 64-bit data word enter the device on the MD0-31 inputs and the upper 32-bits of the 64-bit data word enter the device on the SD0-31 inputs. This provides the device with the full 64-bit word from memory. The resultant generated checkbits are output on the CBO0-7 outputs. The generate time is less than that resulting from using a two-chip cascade. LOW ER 32 BITS (0-31) 32 M D0-31 CBO 8 CHECKBITS-OUT UPPER 32 BITS (32-63) 32 SD0-31 EDC Figure 7. 64-Bit "Generate Only" Mode (Single Chip) 6 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTIONS Symbol SD0-7 SD8-15 SD16-23 SD24-31 I/O I/O Name and Function System Data Bus: Data from the MD0-31 appears at these pins corrected if MODE 2-0 = x11, or uncorrected in the other modes. The BEn inputs must be HIGH and the SOE pin must be LOW to enable the SD output buffers during a read cycle. (Also, see diagnostic section.) Separate I/O Memory Systems: In a write or partial-write cycle, the byte not-to-be-modified is output on SDn to n+7 for rewriting to memory, if BEn is HIGH and SOE is LOW. The new bytes to be written to memory are input on the SDn pins, for writing checkbits to memory, if BEn is LOW. Separate I/O Memory Systems: In a write or partial-write cycle, the byte not-to-be-modified is re-directed to the MS I/O pins, if BEn is HIGH, for checkbit generation and rewriting to memory by the MS I/O pins. SOE must be HIGH to avoid enabling the outputs drivers to the system bus in this more. The new bytes to be written are input on the SDn pins for checkbit generation and writing to memory. BEn must be LOW to direct input data from the System Data bus to the MD I/O pins for checkbit generation and writing to the checkbit memory. SLE PLE SOE BE0-3 I I I I System Latch Enable: SLE is an input used to latch data at the SD inputs. the latch is transparent when SLE is HIGH: the data is latched when SLE is LOW. Pipeline Latch Enable: PLE is an input which controls a pipeline latch, which controls data to be output on the SD bus and the MD bus during byte merges. Use of this latch is optional. The latch is transparent when PLE is LOW: the data is latched when PLE is HIGH. System Output Enable: When LOW, enables System output drivers and Parity outputs drivers if corresponding Byte Enable inputs are HIGH. Byte Enables: In systems using separate I/O memory buses, BEn is used to enable the SD and Parity outputs for byte n. The BEn pins also control the "Byte mux". When BEn is HIGH, the corrected or uncorrected data from the Memory Data latch is directed to the MD I/O pins and used for the checkbit generation for byte n. This is used in partial-word-write operations or during correction cycles. When BEn is LOW, the data from the System Data latch is directed to the MD I/O pins and used for the checkbit generation for byte n. BE0 controls SD0-7 BE1 controls SD8-15 MD0-31 MLE I/O I BE0 controls SD16-23 BE1 controls SD24-31 I/O Buses and Controls Memory Data Bus: These I/O pins accept a 32-bit data word from main memory for error detection and/or correction. They also output corrected old data or new data to be written to main memory when the EDC unit is used in a bidirectional configuration. Memory Latch Enable: MLE is used to latch data from the MD inputs and checkbits from the CBI inputs. The latch is transparent when the MLE is HIGH: data is latched when MLE is LOW. When identified as the upper slice in a 64-bit cascade, the checkbit latch is bypassed. Memory Output Enable: MOE enables Memory Data Bus output drivers when LOW. Parity I/O: The parity I/O pins for Bytes 0 to 3. These pins output the parity of their respective bytes when that byte is being output on the SD bus. These pins also serve as parity inputs and are used in generating the parity ERRor (PERR) signal under certain conditions (see Byte Enable definition). The parity is odd or even depending on the state of the Parity SELect pin (PSEL). Parity SELect: If the Parity SELect pin is LOW, the parity is even. If the Parity SELect pin is HIGH, the parity is odd. CheckBits-In (00) CheckBits-In-1 (10) Partial-Syndrome-In (11) MOE P0-3 I I/O PSEL Inputs CBI0-7 I I PCBI0-7 I In a single EDC system or in the lower slice of a cascaded EDC system, these inputs accept the checkbits from the checkbit memory. In the upper slice in a cascaded EDC system, these inputs accept the "Partial-Syndrome" from the lower slice (Detect/Correct path). Partial-CheckBits-In (11) Partial-CheckBits-In (10) In a single EDC system, these inputs are unused but should not be allowed to float. In a cascaded EDC system, the "Partial-checkbits" used by the lower slice are accepted by these inputs (Correction path only). In the upper slice of a cascaded EDC system, "Partial Checkbits" generated by the lower slice are accepted by these inputs (Generate path). CODE ID 1,0 I CODE IDentity: Inputs with identify the slice position/ functional mode of the IDT49C465. (00) Single 32-bit EDC unit (01) 64-bit "Checkbit-generate-only" unit (10) Lower slice of a 64-bit cascade (11) Upper slice of a 64-bit cascade 7 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTIONS (continued) Symbol I/O Name and Function Inputs (continued) MODE2-0 I (x11) (x10) (000) MODE Select: Selects one of the five operating modes. "Normal" Mode: Normal EDC operation (Flow-thru correction and generation). "Generate-Detect" Mode: In this mode, error correction is disabled. Error generation and detection are normal. "Error-Data-Output" Mode: Allows the uncorrected data from an error event by the Error-Data register to be read by the system for diagnostic purposes. The Error-Data Register is cleared by toggling CLEAR LOW. The Syndrome Register and Error Data Register record the syndrome and uncorrected data from the first error that occurs after they are reset by the CLEAR pin. The Syndrome Register and Error-Data Register are updated when there is a positive edge on SYNCLK, an error condition is indicated (ERR = LOW), and the Error Counter indicates zero. All-Zero-Data Source: In Error-Data-Output Mode, clearing the Error-Data Register provides a source of all-zero-data for hardware initialization of memory, if this is desired. (x01) Diagnostic-output Mode: In this mode, the contents of the Syndrome Register, Error Counter and Error-Type Register are output on the SD bus. This allows the syndrome bytes for an indicated error to be read by the system for error-logging purposes. The Syndrome Register and the Error-Data Register are updated when there is a positive edge an SYNCLK, and error condition is indicated, and the Error Counter indicates zero errors. Thus, the Syndrome Register saves the syndrome that was present when the first error occurred after the Error Counter was cleared. The Syndrome Register and the Error Counter are cleared by toggling CLEAR LOW. The Error Counter lets the system tell if more than one error has occurred since the last time the Syndrome Register or Error Data Register was read. Checkbit-Injection Mode: In "Checkbit-Injection" Mode, diagnostic checkbits may be input on the System Data Bus bits 0-7 (see Diagnostic Features - Detailed Description). CLEAR: When the CLEAR pin is taken LOW, the Error-Data Register, the Syndrome Register, the Error Counter, and the ErrorType Register are cleared. SYNdrome CLocK: If ERR is LOW, and the Error Counter indicates zero errors, syndrome bits are clocked into the Syndrome Register and data from the outputs of the Memory Data input latch are clocked into the Error-Data Register on the LOW-toHIGH edge of SYNCLK. If ERR is LOW, the Error Counter will increment on the LOW-to-HIGH edge of SYNCLK, unless the Error Counter indicated fifteen errors. SynCLK ENable: The SCLKEN enables the SYNCLK signal. SYNCLK is ignored if SCLKEN is HIGH. CheckBits-Out (00, 01) Partial CheckBits-Out (10): CheckBits-Out (11): (100) CLEAR SYNCLK I I SCLKEN CBO0-7 I Outputs and Enables O In a single EDC system, the checkbits are output to the checkbit memory on the outputs. In the lower slice in a cascaded EDC system, the "Partial-checkbits" used by the upper slice are generated by the lower slice CBO0-7 bits (Generate path only). In the upper slice of a cascade, the "Final-Checkbits" appear at these outputs (Generate path only). CBOE SYO0-7 I O CheckBits Out Enable: Enables CheckBit Output driver when LOW. Partial SYndrome-Out(10): SYndrome-Out (00) Partial CheckBits-Out (11): In a 32-bit EDC system, the syndrome bits are output on these pins. In the lower slice in a 64-bit cascaded system, the "PartialSyndrome" bits appear at these outputs (Detect/Correct path). In the upper slice in a cascaded EDC system, the "PartialCheckbits" appear at these outputs (Correct path only). In a 64-bit cascaded system, the "Final-Syndrome" may be accessed in the "Diagnostic-Output" Mode from either the lower or the upper slice since the final syndrome is contained in both. ERR MERR PERR O O O ERROR: When in "Normal" and "Detect only" modes, a LOW on this pin indicates that one or more errors have been detected. ERR is not gated or latched internally. Multiple ERRor: When in "Normal" and "Detect only" modes, a LOW on this pin indicates that one or more errors have been detected. MERR is not gated or latched internally. Parity ERRor: A LOW on this pin indicates a parity error which has resulted from the active bytes defined by the 4 Byte Enable pins. Parity ERRor (PERR) is not gated or latched internally (see Byte Enable definition). +5 Volts Ground Power Supply Pins Vcc 1-10 GND 1-12 P P 8 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE DIAGNOSTIC DATA FORMAT (SYSTEM BUS) Latched Data Error Type S 31 M 30 Reserved Byte 3 23 27 22 21 20 7 6 5 Byte 2 4 3 2 1 0 Error Counter Syndrome Bits Data Out (Unlatched) Partial Checkbits Byte 1 7 6 5 4 3 2 1 0 8 7 7 6 5 Checkbits Byte 0 4 3 2 1 0 0 24 23 16 15 DIAGNOSTIC FEATURES -- DETAILED DESCRIPTION Mode 2-0 x11 x10 "NORMAL" Mode In this mode, operation is "Normal" or non-diagnostic. "GENERATE-DETECT" Mode When the EDC unit is in the "Generate-Detect" Mode, data is not corrected or altered by the error correction network. (Also referred to as the "Detect-only" mode.) 000 "ERROR-DATA-OUTPUT" Mode In this mode, the 32-bit data from the Error-Data Register is output on the SD bus. Error Data Register: The uncorrected data from the Memory Data bus input latch is stored in the Error-Data Register if the error counter contents indicates "0" and there is a positive transition on the SYNCLK input when the ERR signal is LOW. Thus, the Error-Data Register contains memory data corresponding to the first error to occur since the register was cleared. This register is cleared by pulling the CLEAR input LOW. The register is read by the System Data bus by entering the "Error-Data-Output" Mode and enabling the System Data bus output drivers. All-Zero-Data: The Error-Data Register can be used as an "all-zero-data" source for memory initialization in systems where the initialization process is to be done entirely by hardware. x01 "DIAGNOSTIC-OUTPUT" Mode In this mode, data from the diagnostic registers, the PCBI bus, and the CBI bus is output on the SD bus. Direct Checkbit Readback: Internal data paths allow both the "Partial-Checkbit-Input" bus and the data in the "Checkbit-Input" latch to be read directly by the system bus for diagnostic purposes. Both the Checkbit Input Bus and the Partial Checkbit Input Bus are read via the System bus by entering the "Diagnostic-Output" Mode and enabling the System Data bus output drivers. The checkbits are output on the System Data bus bits 0-7; the Partial Checkbits are output on bits 8-15. Syndrome Register: After an error has been detected, the syndrome bits generated are clocked into the internal Syndrome Register if the error counter contents indicates "0" and there is a positive transition on the SYNCLK input when the ERR signal is LOW. This register is cleared by pulling the CLEAR input LOW. The register is read by the System Data bus by entering the "Diagnostic-Output" Mode and enabling the System Data bus output drivers. This data is output on SD bits 16-23. Error Counter: The 4-bit on-board error counter is incremented if the error counter contents do not indicate FF HEX, which corresponds to a count of 15, and there is a positive transition on the SYNCLK input where the ERR signal is LOW. This counter is cleared by pulling the CLEAR input LOW. The counter is read by the System Data bus by entering the "Diagnostic-Output" Mode and enabling the System Data bus output drivers. The data is output on SD bits 24-27. Test Register: These two bits are reserved for factory diagnostics only and must not be used by system software. This data is output on System Data bus bits 28-29. Error-Type Register: The Error-Type Register, clocked by the SYNCLK input, saves two bits which indicate whether a recorded error was a single or a multiple-bit error. This register holds only the first error type to occurs after the last Clear operation. This data is output on System Data bus bits 30-31. 100 Direct Read-Path Checkbit Injection: In the "Checkbit-Injection" Mode, bits 0-7 of the System Data input latch are presented to the inputs of the Checkbit Input Latch. If MLE is strobed, the checkbit latch will be loaded with this value in place of the checkbits from memory. By inserting various checkbit values, operation of the correction function of the EDC can be verified "on-board". Except for the "CheckbitInjection" function, operation in this mode is identical to "Normal" Mode operation. 9 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE OPERATING MODE CHARTS SLICE IDENTIFICATION CODE ID 1 0 0 1 1 CODE 1D 0 0 1 0 1 Slice Definition 32-bit Flow-Thru EDC 64-bit GENERATE Only EDC 64-bit EDC- Lower 32 bits (0-31) 64-bit EDC- Upper 32 bits (32-63) SLICE POSITION CONTROL Slice Position/ CODE ID 10 00 Functional Operation SOE Width = Single 32-bit EDC unit Generate(1) Detect/Correct(2) "64-bit Generate Only" Lower word, 64-bit bus Generate(1) Detect/Correct(2) Upper word, 64-bit bus Generate(1) Detect/Correct(2) SD Bus 32 Sys. 0-31 Pipe. latch Sys. 32-63 Sys. 0-31 Pipe. latch Sys. 32-63 Pipe. latch MOE MD Bus 32 Sys. Byte Mux MD 0-31 Sys. 0-31 MD 0-31 MD 0-31 MD 32-63 MD 32-63 PCBI Bus 8 -- -- -- -- U-SYOout Checkbit Buses CBI Bus 8 -- CBs in -- -- CBs in CBO Bus 8 CBs out -- CBs out SYO Bus 8 -- Syn. out -- P Bus 4 P in P out -- P in P out P in P out PERR 1 active -- -- active -- active -- 01 10 1 0 1 1 0 1 0 0 1 1 0 1 0 1 PCBs out -- -- Par.Synd 11 -- -- F.CBs out -- L-CBOout L-SYOout -- Par.Cbits NOTES: 1. Checkbits generated from the data in the SD Latch. 2. Corrected data residing in the Pipe Latch. FUNCTIONAL MODE CONTROL Functional Mode of SD Bus MODE 210 x11 Width = "Normal" Generate Correct "Generate-Detect" Generate Correct "Error-Data-Output" "Diagnostic-Output" SOE SD Bus 32 1 0 1 0 0 0 CPU Data Pipe. latch CPU Data Pipe. latch Err. D. latch CBin latch PCBlin bus Syn. register Err counter Er. type reg. Sys. 32-63 Pipe. latch 0 1 0 1 -- -- MOE MD Bus 32 Pipe. Latch RAM Data Pipe. Latch RAM Data -- -- PCBI Bus 8 -- -- -- -- -- PCBI in Checkbit Buses CBI Bus 8 -- CB in -- CB in -- CB in CBO Bus 8 CB out -- CB out -- -- -- SYO Bus 8 -- -- -- -- -- -- P Bus 4 P in P out P in P out -- -- PERR 1 active -- active -- -- -- x01 000 x01 100 "Checkbit-Injection" Generate Inject Checkbits Correct 1 1 0 0 0 1 Pipe. Latch Pipe. Latch RAM Data -- -- -- -- -- CB in CB out -- -- -- -- -- P in -- P out active -- -- 10 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE PRIMARY DATA PATH vs. MEMORY CONFIGURATION SEPARATE I/O MEMORIES COMMON I/O MEMORIES 1. C h eckb it G en eratio n W rite N ew W o rd to M em ory 1. C heckb it G en eratio n W rite N ew W o rd to M em o ry BUFFER CP U DIN M AIN M EM OR Y SD MD P CBO DOUT CHE CKB IT M EM O R Y CP U SD P CBO IDT49C465 CBI MD I/O MAIN M EM O R Y CHE CKB IT M EM O R Y IDT49C465 C BI 2. D ata C o rre ction R ead M em o ry W o rd 2. D ata C orrectio n R ead M em o ry W o rd CP U CORR ECTED DIN MAIN M EM O R Y DOUT CH EC KB IT MEM OR Y CORR ECTED CP U SD P CBO MD I/O MAIN M EM O R Y CHE CKB IT M EM O R Y IDT49C465 3. M em ory G en eration R e-w rite C o rrecte d W o rd to M em o ry BUFFER BUFFER SD M D P CBO CBI IDT49C465 CBI 3. M em ory G en eratio n R e-w rite C o rrecte d W ord to M em ory CP U CORR EC TED DIN M AIN MEM OR Y DOUT CHE CKB IT MEM OR Y CO RR ECTED CP U SD P CBO IDT49C465 CBI MD CORR ECTED I/O MAIN M EM O R Y CHE CKB IT M EM O R Y SD MD P CBO IDT49C465 CBI 11 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE PARTIAL-WORD-WRITE OPERATIONS FOR COMMON I/O MEMORIES M D LATCH CORR EC TIO N BLO C K B3 PIPE LATC H B2 M D BU S BYTE 3 B1 BYTE 2 B0 BYTE 1 BYTE MUX BYTE 0 M AIN M EM OR Y SD BU S BYTE 3 BYTE 2 BYTE 1 BYTE 0 8 SD LATCH 8 8 A3 A2 A1 A0 CHE CKBIT GENER ATOR C BO 8 B3 B2 B1 B0 = = = = 1 1 1 0 ID T4 9C 465 C BI CHE CKBIT MEM OR Y In order to perform a partial-word-write operation, the complete word in question must be read from memory. This must be done in order to correct any error which may have occurred in the old word. Once the complete, corrected word is available, with all bytes verified, the new word may be assembled in the byte mux and the new checkbits generated. The example shown above illustrates the case of combining three bytes from an old word with a new lower order byte to form a new word. The new word, along with the new checkbits, may now be written to memory. In the separate I/O memory configuration, the situation is similar except that the new word is output on the SD Bus instead of the MD Bus (refer to previous page.) 12 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE 32-BIT DATA WORD CONFIGURATION A single IDT49C465 EDC unit, connected as shown below, provides all the logic needed for single-bit error correction, and double-bit error detection, of a 32-bit data field. The identification code (00) indicates seven checkbits are required. the CBI7 pin should be tied high. The 39-bit data format for bytes of data and seven checkbits is indicated below. 32-BIT DATA FORMAT DATA BYTE 3 31 24 23 BYTE 2 16 15 BYTE 1 8 7 BYTE 0 0 C6 C5 CH ECKBITS C4 C3 C2 C1 C0 Syndrome bits are generated by an exclusive-OR of the generated checkbits with the checkbits read from memory. For example, Sn is the XOR of checkbits from those read with those generated. During Data Correction, the syndrome bits are used to complement (correct) singlebit errors in the data bits. 32-BIT HARDWARE CONFIGURATION Vcc 8 PCBI0-7 CBO0-6 7 CHECKBITS-O UT CBI7 CBI0-6 SYO0-6 CHEC KBITS-IN 7 7 SYNDROM E-OUT ER R P0-3 M ERR SYSTEM DATA I/O 32 SD0-31 M D0-31 32 M EM O RY DATA I/O IDT49C465 CO DE ID 1,0 = 00 13 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE 64-BIT DATA WORD CONFIGURATION Two IDT49C465 EDC units, connected as shown below, provide all the logic needed for single-bit error correction, and double-bit error detection, of a 64-bit data field. The "Slice Identification" table gives the CODE ID 1, 0 values needed for distinguishing the upper 32 bits from the lower 32 bits. Final generated Checkbits, ERR and MERR (indicates multiple errors) signals come from the upper slice, the IC with CODE ID 1, 0 = 11. Control signals not shown are connected to both units in parallel. Data-In bits 0 through 31 are connected to the same numbered inputs of the EDC with CODE ID 1, 0 = 10 while Data-In bits 32 through 63 are connected to data inputs 0 to 31, respectively, for the EDC unit with CODE ID 1, 0 = 11. The 72-bit data format of data and checkbits is indicated below. Correction of single-bit errors in the 64-bit configuration requires a simultaneous exchange of partial checkbits and partial syndrome bits between the upper and lower units. Syndrome bits are generated by an exclusive-OR of the generated checkbits with the checkbits read from memory. For example, Sn is the XOR of checkbits from those read with those generated. During Data Correction, the syndrome bits are used to complement (correct) singlebit errors in the data bits. For double or multiple-bit error detection, the data available as output by the Pipeline Latch is not defined. Critical AC performance data is provided in the table "Key AC Calculations", which illustrates the delays that are critical to 64-bit cascaded performance. As indicated, a summation of propagation delays is required when cascading these units. 64-BIT DATA FORMAT DATA BYTE 7 63 BYTE 7 BYTE 5 BYTE 4 BYTE 3 BYTE 2 BYTE 1 87 BYTE 0 0 C7 C6 C5 CHE CKB ITS C4 C3 C2 C1 C0 56 55 48 47 40 39 32 31 24 23 16 15 64-BIT HARDWARE CONFIGURATION 8 PARTIAL-CHECKBITS (CORRECT ONLY) PCB I0-7 CHEC KBITS-IN 8 CBI0-7 CBO0-7 8 PCB I0-7 PARTIA L-CHEC KBITS (GENERATE ONLY) CBI0-7 PAR TIA L-S YNDROM E (DETE CT/CO RRECT) P0-3 CBO0-7 8 FINA L C HECKBITS (GEN ERATE ON LY) SYO0-7 8 SYO0-7 ER R (DETECT AND CORRECT) M ERR P0-3 SYS TEM DATA 0-31 SD0-31 SD0-31 MD0-31 MEM ORY DATA 32-63 IDT49C465 LOW E R ED C (COD E ID 1,0 = 10) SYS TEM DA TA 32-63 IDT49C465 UPP ER EDC (CODE ID 1,0 = 11) MEM ORY DATA 0-31 14 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE DEFINITIONS OF TERMS D0 - D31 CBI0 - CBI7 PCBI0 - PCBI7 FS0 - FS7 = System Data and/or Memory Data Inputs = Checkbit Inputs = Partial Checkbit Inputs = Final Internal Syndrome Bits CMOS TESTING CONSIDERATIONS Special test board considerations must be taken into account when applying high-speed CMOS products to the automatic test environment. Large output currents are being switched in very short periods and proper testing demands that test set-ups have minimized inductance and guaranteed zero voltage grounds. The techniques listed below will assist the user in obtaining accurate testing results. 1. All input pins should be connected to a voltage potential during testing. If left floating, the device may oscillate, causing improper device operation and possible latchup. 2. Placement and value of decoupling capacitors is critical. Each physical set-up has different electrical characteristics and it is recommended that various decoupling capacitor sizes be experimented with. Capacitors should be positioned using the minimum lead lengths. They should also be distributed to decouple power supply lines and be placed as close as possible to the DUT power pins. 3. Device grounding is extremely critical for proper device testing. The use of multi-layer performance boards with radial decoupling between power and ground planes is necessary. The ground plane must be sustained from the performance board to the DUT interface board. Wiring unused interconnect pins to the ground plane is recommended. Heavy gauge stranded wire should be used for power wiring, with twisted pairs being recommended for minimized inductance. 4. To guarantee data sheet compliance, the input thresholds should be tested per input pin in a static environment. To allow for testing and hardware-induced noise, IDT recommends using the VIL 0V and VIH 3V for AC tests. FUNCTIONAL EQUATIONS The equations below describe the terms used in the IDT49C465 to determine the values of the partial checkbits, checkbits, partial syndromes, and final internal syndromes. NOTE: All "" symbols below represent the "EXCLUSIVE-OR" function PA = D0 D1 D2 D4 D6 D8 D10 D12 D16 D17 D18 D20 D22 D24 D26 D28 PB = D0 D3 D4 D7 D9 D10 D13 D15 D16 D19 D20 D23 D25 D26 D29 D31 PB = D0 D1 D5 D6 D7 D11 D12 D13 D16 D17 D21 D22 D23 D27 D28 D29 PD = D2 D3 D4 D5 D6 D7 D14 D15 D18 D19 D20 D21 D22 D23 D30 D31 PE = D8 D9 D10 D11 D12 D13 D14 D15 D24 D25 D26 D27 D28 D29 D30 D31 PF = D0 D1 D2 D3 D4 D5 D6 D7 D24 D25 D26 D27 D28 D29 D30 D31 PG = D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 PH0 = D0 D4 D6 D7 D8 D9 D11 D14 D17 D18 D19 D21 D26 D28 D29 D31 PH1 = D1 D2 D3 D5 D8 D9 D11 D14 D17 D18 D19 D21 D24 D25 D27 D30 PH2 = D0 D4 D6 D7 D10 D12 D13 D15 D16 D20 D22 D23 D26 D28 D29 D31 15 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE DETAILED DESCRIPTION -- CHECKBIT AND SYNDROME GENERATION vs. CODE ID LOGIC EQUATIONS FOR THE CBO OUTPUTS Checkbit Generation CBO0 CBO1 CBO2 CBO3 CBO4 CBO5 CBO6 CBO7 00 Final Checkbits PH0 PA PB PC PD PE PF -- CODE ID 1,0 10 Partial Checkbits PH1 PA PB PC PD PE PF PF 11 Final Checkbits PH2 PCBI0 PA PCBI1 PB PCBI2 PC PCBI3 PD PCBI4 PE PCBI5 PF PCBI6 PG PCBI7 32-BIT SYNDROME DECODE TO BIT-IN-ERROR (1) SYNDROME BITS HEX S3 S2 S1 S0 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 A 1 0 1 0 B 1 0 1 1 C 1 1 0 0 D 1 1 0 1 E 1 1 1 0 F 1 1 1 1 HEX S6 S5 S4 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 T 14 M T 15 T T M M T T M T M M T 4 1 0 0 C6 T T M T M M T T M 1 T M T T 0 5 1 0 1 T M 2 T 3 T T 4 5 T T 6 T 7 M T 6 1 1 0 T M 24 T 25 T T 26 27 T T 28 T 29 M T 7 1 1 1 30 T T M T 31 M T T M M T M T T M LOGIC EQUATIONS FOR THE SYO OUTPUTS Checkbit Generation SYO0 SYO1 SYO2 SYO3 SYO4 SYO5 SYO6 SYO7 00 Final Syndrome PH0 CBI0 PA CBI1 PB CBI2 PC CBI3 PD CBI4 PE CBI5 PF CBI6 -- CODE ID 1,0 10 Partial Syndrome PH1 CBI0 PA CBI1 PB CBI2 PC CBI3 PD CBI4 PE CBI5 PF CBI6 PF CBI7 11 Partial Checkbits PH2 PA PB PC PD PE PF PG * C4 C5 C0 T T C1 T T T 18 8 C2 T T T 19 9 T 20 10 MT T C3 T T T 21 11 T 22 12 17 T T T 23 13 MT T 16 T T TMM NOTE: 1. The table indicates the decoding of the seven syndrome bits to identify the bit-in-error for a single-bit error, or whether a double or triple-bit error was detected. The all-zero case indicattes no error detected. * = No errors detected # = The number of the single bit-in-error T = Two errors detected M = three or more errors detected LOGIC EQUATIONS FOR THE FINAL SYNDROME (FSn) CODE ID 1,0 Checkbit Generation FS0 FS 1 FS 2 FS 3 FS 4 FS 5 FS 6 FS 7 00 Final Syndrome PH0 CBI0 PA CBI1 PB CBI2 PC CBI3 PD CBI4 PE CBI5 PF CBI6 -- 10, 11 Final Internal Syndrome PH1 (L) PH2 (U) CBI0 PA (L) PA (U) CBI1 PB (L) PB (U) CBI2 PC (L) PC (U) CBI3 PD (L) PD (U) CBI4 PE (L) PE (U) CBI5 PF (L) PF (U) CBI6 PF (L) PG (U) CBI7 16 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE DETAILED DESCRIPTION -- 32-BIT CONFIGURATION 32-BIT MODIFIED HAMMING CODE - CHECKBIT ENCODING CHART (1) Generated Checkbits CB0 CB1 CB2 CB3 CB4 CB5 CB6 Generated Checkbits CB0 CB1 CB2 CB3 CB4 CB5 CB6 Parity Even (XOR) Even (XOR) Odd (XNOR) Odd (XNOR) Even (XOR) Even (XOR) Even (XOR) 0 X X X X 1 X X X X X X X X X X 2 X X 3 4 X X X 5 Participating Data Bits 6 7 8 9 X X X X X X X X X X X X X X X X Participating Data Bits 22 23 24 25 X X X X X X X X X X X X 10 X X X X X 11 X 12 X X X X X X X X X X X 13 14 X 15 X X X Parity Even (XOR) Even (XOR) Odd (XNOR) Odd (XNOR) Even (XOR) Even (XOR) Even (XOR) 16 X X X 17 X X X 18 X X 19 X X 20 X X X 21 X 26 X X X 27 28 X X X X X 29 X X X X X 30 31 X X X X X X X X X X X X X X X X X NOTE: 1. The table indicates the data bits participating in the checkbit generation. For example, checkbit C0 is the Exclusive-OR function of the 16 data input bits marked with an X. 17 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE DETAILED DESCRIPTION -- 64-BIT CONFIGURATION 64-BIT MODIFIED HAMMING CODE - CHECKBIT ENCODING CHART (1, 2) Generated Checkbits CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 Generated Checkbits CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 Generated Checkbits CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 Generated Checkbits CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 Parity Even (XOR) Even (XOR) Odd (XNOR) Odd (XNOR) Even (XOR) Even (XOR) Even (XOR) Even (XOR) 0 X X X 1 X X X X X X X X X X X X X X X X 2 X X 3 X X 4 X X X X X X 5 X Participating Data Bits 6 7 8 9 X X X X X X X X X X X X X X X X Participating Data Bits 22 23 24 25 X X X X X X X X X X X X X X X X Participating Data Bits 38 39 40 41 X X X X X X X X X X X X X X X X Participating Data Bits 54 55 56 57 X X X X X X X X X X X X X X X X 10 X X X X X 11 X 12 X X X X X X X X X X X 13 14 X 15 Parity Even (XOR) Even (XOR) Odd (XNOR) Odd (XNOR) Even (XOR) Even (XOR) Even (XOR) Even (XOR) 16 X X X 17 X X X 18 X X 19 X X 20 X X X 21 X 26 X X 27 X 28 X 29 30 X 31 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Parity Even (XOR) Even (XOR) Odd (XNOR) Odd (XNOR) Even (XOR) Even (XOR) Even (XOR) Even (XOR) 32 X X X X 33 X X 34 X 35 X X X X 36 X X X X X 37 42 X X X 43 44 X X X X X 45 X X X X X 46 47 X X X X X X X X X X X X X X X X X X X Parity Even (XOR) Even (XOR) Odd (XNOR) Odd (XNOR) Even (XOR) Even (XOR) Even (XOR) Even (XOR) 48 X X X X 49 X X 50 X 51 X X X 52 X X X X 53 58 X X X 59 60 X X X X X 61 X X X X X 62 63 X X X X X X X X X X X X X X X X X X X X X NOTES: 1. The table indicates the data bits participating in the checkbit generation. For example, checkbit C0 is the Exclusive-OR function of the 64 data input bits marked with an X. 2. The checkbit is generated as either an XOR or an XNOR of the 64 data bits noted by an "X" in the table. 18 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE DETAILED DESCRIPTION -- 64-BIT CONFIGURATION (cont.) 64-BIT SYNDROME DECODE TO BIT-IN-ERROR (1) Syndrome Bits HEX 0 1 2 3 4 5 6 7 8 9 A B C D E F S3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HEX S7 S6 S5 S4 0 0 0 0 0 * C0 C1 T C2 T T M C3 T T 17 T M 16 T 1 0 0 0 1 C4 T T 18 T 19 20 T T 21 22 T 23 T T M 2 0 0 1 0 C5 T T 8 T 9 10 T T 11 12 T 13 T T M 3 0 0 1 0 T 14 M T 15 T T M M T T M T M M T 4 0 1 0 0 C6 T T M T M M T T M 33 T M T T 32 5 0 1 0 1 T M 34 T 35 T T 36 37 T T 38 T 39 M T 6 0 1 1 0 T M 56 T 57 T T 58 59 T T 60 T 61 M T 7 0 1 1 1 62 T T M T 63 M T T M M T M T T M 8 1 0 0 0 C7 T T M T M M T T M 49 T M T T 48 9 1 0 0 1 T M 50 T 51 T T 52 53 T T 54 T 55 M T A 1 0 1 0 T M 40 T 41 T T 42 43 T T 44 T 45 M T B 1 0 1 1 46 T T M T 47 M T T M M T M T T M C 1 1 0 0 T M M T M T T M M T T 1 T M 0 T D 1 1 0 1 M T T 2 T 3 4 T T 5 6 T 7 T T M E 1 1 1 0 M T T 24 T 25 26 T T 27 28 T 29 T T M F 1 1 1 1 T 30 M T 31 T T M M T T M T M M T NOTE: 1. The table indicates the decoding of the seven syndrome bits to identify the bit-in-error for a single-bit error, or whether a double or triple-bit error was detected. The all-zero case indicattes no error detected. * = No errors detected # = The number of the single bit-in-error T = Two errors detected M = three or more errors detected KEY AC CALCULATIONS -- 64-BIT CASCADED CONFIGURATION 64-Bit Propagation Delay Mode Generate Detect From SD Bus MD Bus MD Bus Correct (1) MD BUs To Checkbits out ERR for 64-bits MERR for 64 bits Corrected Data Out Total AC Delay for IDT49C465 in 64-bit Mode (L) = Lower slice (U) = Upper slice SD to CBO (L) + PCBI to CBO (U) t SC (L) + t PCC (U) MD to SYO (L) + CBI to ERR (U) t MSY (L) + t CE (U) MD to SYO (L) + CBI to MERR t MSY (L) + t CME (U) MD to SYO (L) + CBI to SD (U) t MSY (L) + t CS (U) (or) MD to SYO (U) + PCBI to SD (L) t MSY (U) + t PCS (L) NOTE: 1. (or) = Whichever is worse. 19 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS (1) Symbol Vcc VTERM TA TBIAS TSTG IOUT Description Power Supply Voltage Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Com'l. - 0.5 to +7 0 to +70 - 55 to +125 - 55 to +125 30 Unit V V C C C mA CAPACITANCE (TA = +25C, f = 1.0MHZ) Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance NOTE: 1. This parameter is sampled and not 100% tested. Conditions VIN = 0V VOUT = 0V Pkg. PGA PQFP PGA PQFP Typ. 10 5 12 7 Unit pF pF Terminal Voltage with Respect to GND - 0.5 to Vcc +0.5 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to +70C, Vcc = 5V 5% Symbol VIH VIL IIH IIL IOZ IOS VOH VOL VH ICCQ ICCQT ICCD1 ICCD2 Parameter Input HIGH Level(4) Input LOW Level(4) Input HIGH Current Input LOW Current Off State (Hi-Z) Short Circuit Current Output HIGH Voltage Output LOW Voltage Hysteresis Quiescent Power Supply Current CMOS Levels Quiescent Power Supply Current TTL Input Levels Dynamic Power Supply Current f = 10MHz Dynamic Power Supply Current f = 20MHz Test Conditions(1) Guaranteed Logic HIGH Normal Inputs Hysteresis Inputs Guaranteed Logic LOW Vcc = Max, VIN = Vcc Vcc = Max, VIN = GND VCC = 3.6V VCC = Max.(3) Vcc = Min. VIN = VIN or VIL Vcc = Min. VIN = VIN or VIL IOH = - 6mA IOL = 12mA VO = 0V VO = 3V Min. 2 3 -- -- -- -- -- - 20 2.4 -- -- -- -- -- -- Typ.(2) -- -- -- -- -- -- -- -- -- -- 200 -- -- -- -- Max. -- -- 0.8 5 -5 - 10 10 - 150 -- .5 -- 5 1 100 200 mA V V mV mA mA/ Input mA mA V A A A Unit V CLEAR, MLE, PLE, SLE, SYNCLK, SCLKEN VIN = VCC or GND, VCC = Max. All Inputs, Outputs Disabled VIN = 3.4V, VIL = 0V, VCC = Max. All Inputs, Outputs Disabled fCP = 10MHz, 50% Duty Cycle VIH = VCC, VIL = GND, Read Mode, Outputs Disabled fCP = 20MHz, 50% Duty Cycle VIH = VCC, VIL = GND, Read Mode, Outputs Disabled NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified above for the applicable device type. 2. Typical values are at Vcc = 5V, +25C ambient temperature, and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the short-circuit test should not exceed one second. 4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment. 5. Total supply current is the sum of the Quiescent current and the dynamic current and is calculated as follows: ICC = ICCQ + ICCQT (NT x DT) + ICCD (fOP) where: NT = Total # of quiescent TTL inputs DT = AC Duty Cycle - % or time high (TTL) fOP = Operating frequency 20 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE AC PARAMETERS -- 49C465A PROPAGATION DELAY TIMES (1,2) 32-bit System Standalone Slice CODE ID = 00 Number Parameter Name From To Input (edge) Output (edge) CBO MDOUT CBO CBO PERR CBO MDOUT PERR ERR Low MERR Low SYO ERR MERR SYO SDOUT Px SDOUT SYO SDOUT SDOUT SDOUT Max. 15 15 -- -- 12 14 12 12 14 15 12 12 16 16 16 18 14 16 -- 15 15 64-bit "Generate only" Slice CODE ID = 01 Max. -- -- 15 -- -- 14 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 64-bit System Lower Slice CODE ID = 10 Max. 15 15 -- -- 12 14 12 12 -- -- 12 -- -- 12 -- 18 -- 12 13 15 15 Upper Slice CODE ID = 11 Max. 15 15 -- 12 12 14 12 12 12 15 -- 12 16 12 16 18 -- 12 -- 15 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Refer to Timing Diagram Figure -- -- 10 7 -- 7 7 -- 8, 10 8, 10 8, 10 8, 10 8, 10 8, 10 8, 11 8, 11 8, 11 8, 11 11 15 15 GENERATE (WRITE) PARAMETERS 01 tBC BEN 02 tBM BEN MDIN 03 tMC PCBI 04 tPCC 05 tPPE PXIN 06 tSC SDIN 07 tSM 08 tSPE DETECT (READ) PARAMETERS 09 tCE CBI 10 tCME 11 tCSY 12 tME MDIN 13 tMME 14 tMSY CORRECT (READ) PARAMETERS CBI 15 tCS 16 tMP MDIN 17 tMS 18 tMSY PCBI 19 tPCS DIAGNOSTIC PARAMETERS 20 tCLR CLEAR = Low 21 tMIS MODE ID NOTES: 1. Where "edge" is not specified, both HIGH and LOW edges are implied. 2. BOLD indicates critical system parameters. 21 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE AC PARAMETERS -- 49C465A PROPAGATION DELAY TIMES FROM LATCH ENABLES Number 22 23 24 25 26 27 28 29 30 31 Parameter Name tMLC tMLE tMLME tMLP tMLS tMLSY tPLS tPLP tSLC tSLM From Input Parameter Description To (edge) Output CBO ERR HIGH MERR Px SDOUT SYO LOW SDOUT LOW Px HIGH CBO HIGH MDOUT (edge) * * * * * * * * * * Max. 16 13 16 18 18 15 10 13 16 12 Unit ns ns ns ns ns ns ns ns ns ns Refer to Timing Diagram Figure 13 8, 10, 11 8 8, 11 8, 10, 11 8, 10 8, 11 8, 11 7, 9 7, 9 MLE = PLE = PLE = SLE = SLE = NOTE: * = Both HIGH and LOW edges are implied. ENABLE AND DISABLE TIMES Number 32 33 34 35 36 37 38 39 40 41 Parameter Name tBESZx tBESxZ tBEPZx tBEPxZ tCECZx tCECxZ tMEMZx tMEMxZ tSESZx tSESxZ From Input BEN = BEN = CBOE = MOE = SOE = Parameter Description To (edge) Output HIGH SDOUT LOW HIGH POUT LOW LOW CBO HIGH LOW MDOUT HIGH LOW SDOUT HIGH (edge) * Hi-Z * Hi-Z * Hi-Z * Hi-Z * Hi-Z Min. 2 2 2 2 2 2 2 2 2 2 Max. 13 11 13 11 13 11 13 11 13 11 Unit ns ns ns ns ns ns ns ns ns ns Refer to Timing Diagram Figure 8, 10, 11 8, 11 7, 9 7, 9 8, 10 8, 10 7, 9 NOTE: * = Delay to both edges. 22 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE SET-UP AND HOLD TIMES -- 49C465A Number 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Parameter Name tSSLS tSSLH tMMLS tMMLH tCMLS tCMLH tMPLS tMPLH tCPLS tCPLH tCPCLS tCPCLH tCSCS tMSCS tMLSCS tSESCS tSESCH From Input SDIN Set-up SDIN Hold MDIN Set-up MDIN Hold CBI Set-up CBI Hold MDIN Set-up MDIN Hold CBI Set-up CBI Hold PCBI Set-up PCBI Hold CBI Set-up MDIN Set-up MLE Set-up = SCLKEN Set-up = SCLKEN Hold = Parameter Description To (edge) Output * before SLE = * after SLE = * before MLE = * after MLE = * before MLE = * after MLE = * before PLE = * after PLE = * before PLE = * after PLE = * before PLE = * after PLE = * * HIGH LOW LOW (edge) LOW LOW LOW LOW LOW LOW HIGH HIGH HIGH HIGH HIGH HIGH Min. 3 3 3 3 3 3 10 0 10 0 10 0 10 10 10 3 3 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Refer to Timing Diagram Figure 7, 9 7, 9 8, 10, 11 8, 10, 11 8, 10, 11 8, 10, 11 -- -- -- -- -- -- 15 15 15 15 15 DIAGNOSTIC SET-UP AND HOLD TIMES before SYNCLK = after SYNCLK = HIGH HIGH NOTE: * = Where "edge" is not specified, both HIGH and LOW edges are implied. MINIMUM PULSE WIDTH Number 59 60 61 62 63 Parameter name tCLEAR tMLE tPLE tSLE tSYNCLK Minimum Pulse Width Input Min. CLEAR LOW time to clear diag. registers Min. MLE HIGH time to strobe new data Min. PLE HIGH time to strobe new data Min. SLE HIGH time to strobe new data Min. SYNCLK HIGH time to clock in new data Conditions Data = Valid MD, CBI = Valid SD = Valid SD = Valid SCKEN = LOW Min. 8 5 5 5 5 Unit ns ns ns ns ns Refer to Timing Diagram Figure 14 -- -- -- 14 Input Rise Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3V 1V/ns 1.5V 1.5V See Figure 18 23 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE 64-BIT LOWER SLICE APPLICATION EXCEPTION (49C465A) Parameter Name tMEMxZ tPCBI(1) tMLS From Input MOE MOE MLE Parameter Description To (edge) Output (edge) HIGH MDOUT Hi-Z HIGH PCBIN HIGH SDOUT Refer to Timing Diagram Figure 12 12 12 Number 39(a) 26(a) Typ. -- 23 -- Min. -- -- 28 Max. 11 -- -- Unit ns ns ns 64-BIT UPPER SLICE APPLICATION EXCEPTION (49C465A) Parameter Name tMEMxZ tMMLS tMMLH tCMLS tCMLH Parameter Name tMLE From Input MOE MDIN Set-up MDIN Hold CBI Set-up CBI Hold Parameter Description To (edge) Output HIGH MDOUT Refer to Timing Diagram Figure 13 13 13 13 13 Refer to Timing Diagram Figure 13 Refer to Timing Diagram Figure 13 13 Number 39(a) 44(a) 45(a) 46(a) (2) 47(a) (2) (edge) Hi-Z Min. -- 5.5 5.5 -- -- Max. 11 -- -- -- -- Unit ns ns ns ns ns Number 60(a) Minimum Pulse Width Input Conditions Min. MLE HIGH time to MD, CBI = Valid strobe new data Parameter Description To (edge) Output (edge) HIGH CBIN HIGH SDOUT Min. 7.5 Max. -- Unit ns Number 26(a) Parameter Name tCBI(3) tMLS From Input MOE MLE Typ. 23 -- Min. -- 28 Max. -- -- Unit ns ns NOTES: 1. Partial Checkbit input (PCBI) of 64-bit lower slice comes from the Syndrome output of the upper slice unit. Valid input time is shown above as tPCBI. 2. There is no setup and hold time for CBI bus input on 64-bit upper slice operation mode. 3. Valid CBI signal comes from the Syndrome output of lower slice. Typical time of valid CBIN is shown as tCBI. 24 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE AC PARAMETERS -- 49C465 PROPAGATION DELAY TIMES (1,2) 32-bit System Standalone Slice CODE ID = 00 Number Parameter Name Parameter Description From To Input (edge) Output (edge) CBO MDOUT CBO CBO PERR CBO MDOUT PERR ERR Low MERR Low SYO ERR Low MERR Low SYO SDOUT Px SDOUT SYO SDOUT SDOUT SDOUT 64-bit "Generate only" Slice CODE ID = 01 64-bit System Lower Slice CODE ID = 10 Upper Slice CODE ID = 11 Refer to Timing Diagram Figure -- -- 10 7 -- 7 7 -- 8, 10 8, 10 8, 10 8, 10 8, 10 8, 10 8, 11 8, 11 8, 11 8, 11 11 15 15 Max. 20 20 -- -- 15 16 15 15 16 20 15 15 20 18 20 20 16 18 -- 20 20 Max. -- -- 17 -- -- 16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 20 20 -- -- 15 16 15 15 -- -- 12 -- -- 15 -- 20 -- 15 15 20 20 Max. 20 20 -- 15 15 16 15 15 15 20 -- 15 20 15 20 20 -- 15 -- 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns GENERATE (WRITE) PARAMETERS 01 tBC BEN 02 tBM BEN MDIN 03 tMC PCBI 04 tPCC 05 tPPE PXIN 06 tSC SDIN 07 tSM 08 tSPE DETECT (READ) PARAMETERS 09 tCE CBI 10 tCME 11 tCSY 12 tME MDIN 13 tMME 14 tMSY CORRECT (READ) PARAMETERS CBI 15 tCS 16 tMP MDIN 17 tMS 18 tMSY PCBI 19 tPCS DIAGNOSTIC PARAMETERS 20 tCLR CLEAR = Low 21 tMIS MODE ID NOTES: 1. Where "edge" is not specified, both HIGH and LOW edges are implied. 2. BOLD indicates critical system parameters. 25 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE AC PARAMETERS -- 49C465 PROPAGATION DELAY TIMES FROM LATCH ENABLES Number 22 23 24 25 26 27 28 29 30 31 Parameter Name tMLC tMLE tMLME tMLP tMLS tMLSY tPLS tPLP tSLC tSLM From Input Parameter Description To (edge) Output CBO ERR HIGH MERR Px SDOUT SYO LOW SDOUT LOW Px HIGH CBO HIGH MDOUT (edge) * * * * * * * * * * Max. 20 15 20 20 20 18 12 16 20 15 Unit ns ns ns ns ns ns ns ns ns ns Refer to Timing Diagram Figure 13 8, 10, 11 8 8, 11 8, 10, 11 8, 10 8, 11 8, 11 7, 9 7, 9 MLE = PLE = PLE = SLE = SLE = NOTE: * = Both HIGH and LOW edges are implied. ENABLE AND DISABLE TIMES Number 32 33 34 35 36 37 38 39 40 41 Parameter Name tBESZx tBESxZ tBEPZx tBEPxZ tCECZx tCECxZ tMEMZx tMEMxZ tSESZx tSESxZ From Input BEN = BEN = CBOE = MOE = SOE = Parameter Description To (edge) Output HIGH SDOUT LOW HIGH POUT LOW LOW CBO HIGH LOW MDOUT HIGH LOW SDOUT HIGH (edge) * Hi-Z * Hi-Z * Hi-Z * Hi-Z * Hi-Z Min. 2 2 2 2 2 2 2 2 2 2 Max. 15 13 15 13 15 13 15 13 15 13 Unit ns ns ns ns ns ns ns ns ns ns Refer to Timing Diagram Figure 8, 10, 11 8, 11 7, 9 7, 9 8, 10 8, 10 7, 9 NOTE: * = Delay to both edges. 26 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE SET-UP AND HOLD TIMES -- 49C465 Number 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Parameter Name tSSLS tSSLH tMMLS tMMLH tCMLS tCMLH tMPLS tMPLH tCPLS tCPLH tCPCLS tCPCLH tCSCS tMSCS tMLSCS tSESCS tSESCH From Input SDIN Set-up SDIN Hold MDIN Set-up MDIN Hold CBI Set-up CBI Hold MDIN Set-up MDIN Hold CBI Set-up CBI Hold PCBI Set-up PCBI Hold CBI Set-up MDIN Set-up MLE Set-up = SCLKEN Set-up = SCLKEN Hold = Parameter Description To (edge) Output * before SLE = * after SLE = * before MLE = * after MLE = * before MLE = * after MLE = * before PLE = * after PLE = * before PLE = * after PLE = * before PLE = * after PLE = * * HIGH LOW LOW (edge) LOW LOW LOW LOW LOW LOW HIGH HIGH HIGH HIGH HIGH HIGH Min. 4 4 4 4 4 4 12 0 12 0 12 0 12 12 12 4 4 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Refer to Timing Diagram Figure 7, 9 7, 9 8, 10, 11 8, 10, 11 8, 10, 11 8, 10, 11 -- -- -- -- -- -- 15 15 15 15 15 DIAGNOSTIC SET-UP AND HOLD TIMES before SYNCLK = after SYNCLK = HIGH HIGH NOTE: * = Where "edge" is not specified, both HIGH and LOW edges are implied. MINIMUM PULSE WIDTH Number 59 60 61 62 63 Parameter name tCLEAR tMLE tPLE tSLE tSYNCLK Minimum Pulse Width Input Min. CLEAR LOW time to clear diag. registers Min. MLE HIGH time to strobe new data Min. PLE HIGH time to strobe new data Min. SLE HIGH time to strobe new data Min. SYNCLK HIGH time to clock in new data Conditions Data = Valid MD, CBI = Valid SD = Valid SD = Valid SCKEN = LOW Min. 8 5 5 5 5 Unit ns ns ns ns ns Refer to Timing Diagram Figure 14 -- -- -- 14 Input Rise Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3V 1V/ns 1.5V 1.5V See Figure 18 27 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE 64-BIT LOWER SLICE APPLICATION EXCEPTION (49C465) Parameter Name tMEMxZ tPCBI(1) tMLS From Input MOE MOE MLE Parameter Description To (edge) Output (edge) HIGH MDOUT Hi-Z HIGH PCBIN HIGH SDOUT Refer to Timing Diagram Figure 12 12 12 Number 39(a) 26(a) Typ. -- 27 -- Min. -- -- 34 Max. 13 -- -- Unit ns ns ns 64-BIT UPPER SLICE APPLICATION EXCEPTION (49C465) Parameter Name tMEMxZ tMMLS tMMLH tCMLS tCMLH Parameter Name tMLE From Input MOE MDIN Set-up MDIN Hold CBI Set-up CBI Hold Parameter Description To (edge) Output HIGH MDOUT Refer to Timing Diagram Figure 13 13 13 13 13 Refer to Timing Diagram Figure 13 Refer to Timing Diagram Figure 13 13 Number 39(a) 44(a) 45(a) 46(a) (2) 47(a) (2) (edge) Hi-Z Min. -- 6.5 6.5 -- -- Max. 13 -- -- -- -- Unit ns ns ns ns ns Number 60(a) Minimum Pulse Width Input Conditions Min. MLE HIGH time to MD, CBI = Valid strobe new data Parameter Description To (edge) Output (edge) HIGH CBIN HIGH SDOUT Min. 8.5 Max. -- Unit ns Number 26(a) Parameter Name tCBI(3) tMLS From Input MOE MLE Typ. 27 -- Min. -- 34 Max. -- -- Unit ns ns NOTES: 1. Partial Checkbit input (PCBI) of 64-bit lower slice comes from the Syndrome output of the upper slice unit. Valid input time is shown above as tPCBI. 2. There is no setup and hold time for CBI bus input on 64-bit upper slice operation mode. 3. Valid CBI signal comes from the Syndrome output of lower slice. Typical time of valid CBIN is shown as tCBI. 28 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE AC TIMING DIAGRAMS--32-BIT CONFIGURATION to BEN 1 2 3 4 5 Propagation Delay Parameter From Name To M in./ Max. tBESxZ tBESxZ tBESxZ m in. tBESxZ m ax. BEN - Low to SDOUT Disabled BEN - Low to SDOUT Disabled SOE - Low to SDOUT Disabled SOE - Low to SDOUT Disabled min. max. SOE tSESxZ tSESxZ tSESxZ m in. tSESxZ m ax. DATAIN tSSLS tSSLH tSSLH tSSLS min. max. SD0-31 (OUTPUT) SDIN Set-up to SLEIN = Low SDIN Hold to SLEIN = Low min. min. SLE tSPE tSPE SDIN to PERROUT max. PN tPPE tPPE PX to PERROUT max. PERR tSM (1) tSM tSLM (1) SDIN to M DOUT SLE = High to M DOUT max. max. tSLM MOE tM EM Zx tM EM Zx MOE = Low to M DOUT Enabled max. M D0-31 (INPUT) tSC (1) M DATAOUT = S DATAIN tSC tSLC (1) SDIN to CBO SLE = High to CBO max. max. tSLC CBOE tCECZx tCECZx CBOE = Low to CBO Enable max. CBO to 1 2 3 4 5 NOTE: 1. Assumes that System Data is valid at least 3ns (Com.) before SLE goes HIGH. Figure 7. 32-Bit Generate Timing 29 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE AC TIMING DIAGRAMS--32-BIT CONFIGURATION to MOE tMEM xZ 1 2 3 4 5 Propagation Delay Parameter From Name To Min./ Max. tMEMxZ Valid DATAIN MOE - High to M DOUT Disabled max. MD0-31 (OUTPUT) tMM LS tMMLH tMMLS tMMLH MDIN Set-up to M LE = Low MDIN Hold to MLE = Low min. min. CBI Valid Checkbits In tCMLS tCMLH tCMLS tCMLH Checkbit Set-up to MLE = Low Checkbit Hold to MLE = Low min. min. MLE tMSY tCSY tMLSY (1) tMSY tCSY tMLSY (1) M DIN to SYO OUT Checkbits in to SYOOUT M LE = High to S YOOUT MDIN to ER R = Low Checkbits in to ERR = Low (1) max. max. max. SYO tME tCE tMLEx (1) tME tCE tMLEx max. max. max. M LE = High to E RR = Low (1) ERR tM ME tCM E tMLEMx (1) tMME tCME tMLEMx (1) MDIN to M ERR = Low Checkbits in to MERR = Low MLE = H igh to MER R = Low (1) max. max. max. MERR to 1 2 3 4 5 NOTE: 1. Assumes that Memory Data and Checkbits are valid at least 3ns before MLE goes HIGH. Figure 8. 32-Bit Detect Timing 30 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE AC TIMING DIAGRAMS--32-BIT CONFIGURATION Propagation Delay Parameter From Name To Min./ Max. to MOE tMEMxZ 1 2 3 4 5 tMEMxZ Valid DATAIN MOE - High to M DOUT Disabled max. MD0-31 (OUTPUT) tMM LS tMMLH tMMLS tMMLH MDIN Set-up to MLE = Low MDIN Hold to MLE = Low min. min. CBI Valid Checkbits In tCMLS tCMLH tCMLS tCMLH Checkbit Set-up to MLE = Low Checkbit Hold to M LE = Low min. min. MLE tMLS (1) tMLS (1) MLEIN = High to SDOUT (1) max. PLE tPLS (1) tPLS (1) PLE = Low to SDOUT (1) max. BEN tBESZx tBESZx BEN = High to SDOUT Enabled max. SOE tSESZx tCS tMS CORRECTE D DATAOUT tM P tMLP tPLP tBEPZx tSEP tMP tMLP tPLP tBEPZx tSEP Parity Out tSESZx tCS tMS SOE = Low to SDOUT Enabled CBI to Corrected SDOUT MDIN to Corrected SDOUT max. max. max. MDIN to Parity Out MLE = High to Parity Out PLE = Low to Parity Out BEN = High to Parity Out SOE = Low to Parity Out max. max. max. max. max. P0-3 to 1 2 3 4 5 NOTE: 1. Assumes that Memory Data and Checkbits are valid at least 3ns before MLE goes HIGH. Figure 9. 32-Bit Correct Timing 31 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE AC TIMING DIAGRAMS--64-BIT CONFIGURATION BOTH 465s to 1 2 3 4 5 Propagation D elay Parameter From Name To Min./ Max. BEN SOE tSESxZ tSESxZ tSESxZ min. tSESxZ max. DATAIN tSSLS tSSLH tSSLH tSSLS SOE - High to SD OUT D isabled SOE - High to SDOUT D isabled SD IN Set-up to SLEIN = Low SDIN Hold to SLEIN = Low min. max. SD(L & U) (OUTPUT) min. min. SLE PN Parity In tPPE tPPE PX to PERR max. PER R tSM tSM SDIN to MDOUT max. M OE (1) tSLM tMEM Zx tBEM (1) tSLM tMEM Zx tBEM M DATAOUT = S DATAIN tSC (1) SLE = High to MD OUT MOE = Low to M DOUT Enabled BEIN to MD OUT max. max. max. MD(L & U) (INPUT) tSC tSLC (1) SD Low er In to C BO SLEIN = H igh to C BO (1) max. max. tSLC CBOE tCECZx LO WER 465 tCECZx CBOE = Low to CBO Enabled max. CBO Parital Checkbits Out 3 UPPER 465 Inter-chip delay (Design dependent) Parital Checkbits In tPCC tPCC PC BI PCBI to CBO max. CBO Final Checkbits Out to 1 2 3 4 5 NOTE: 1. Assumes that SystemData is valid at least 3ns before SLE goes HIGH. Figure 10. 64-Bit Generate Timing--(64-Bit Cascading System) 32 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE AC TIMING DIAGRAMS--64-BIT CONFIGURATION BOTH 465s to 1 2 3 4 5 Propagation Delay Parameter From Name To Min./ Max. MOE tMEMxZ tMEMxZ MOE = High to MDOUT Disabled max. MD (L) (OUTPUT) Valid DATAIN tMM LS tMMLH tMMLS tMMLH MDIN Set-up to MLE = Low MDIN Hold to MLE = Low min. min. CBI Valid Checkbits In tCMLS tCMLH tCMLS tCMLH CBI Set-up to MLE = Low CBI H old to M LE = Low min. min. MLE tMLS (1) tMLS (1) MLE = High to SDOUT (1) max. BEN tBESZx tBESZx BEN = High to SDOUT Enabled max. SOE tSESZx LOW ER 465 tSESZx SOE = Low to SDOUT Enabled max. SD 0-31 tMSY tCSY tMLSY CORRECTE D DATAOUT tMSY tCSY tMLSY Partial Syndrome Out 3 Partial Syndrome In tCME tMLME (1) MD Lower In to SYOOUT CBI to SYO MLE = H igh to SYO max. max. max. SYO UPPER 465 Inter-chip delay (Design dependent) CBI tCME tMLME (1) CBI to ME RR MLE = H igh to MERR CBI to ERR (1) max. max. MERR tCE tMLE (1) tCE tMLE max. max. MLE = High to ERR ERR tME tM ME tM E tMME MDIN to ERR MDIN to MERR max. max. MD (U) (OUTPUT) Valid DATAIN to 1 2 3 4 5 NOTE: 1. Assumes that SystemData is valid at least 3ns before SLE goes HIGH. Figure 11. 64-Bit Detect Timing 33 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE AC TIMING DIAGRAMS--64-BIT CONFIGURATION 64-BIT U/L Slice to 1 2 3 4 5 Propagation Delay Parameter From Name To Min./ M ax. MOE tMEM xZ tMEMxZ M OE = High to MDOUT Disabled max. MD 0-31 (OUTPUT) Valid DATAIN tMM LS tMMLH tMMLS tMMLH M DIN Set-up to MLE = Low M DIN Hold to MLE = Low min. min. CBI Valid Checkbits In tCMLS tCMLH tCMLS tCMLH CBI Set-up to MLE = Low CBI H old to M LE = Low min. min. M LE tMLS (1) tMLS Partial Checkbits in from Upper (1) MLEIN = High to SDOUT (1) max. PCBI tPCBI PLE tPLS (1) (1) tPLS PLE = Low to S DOUT (1) max. BEN tBESZx tBESZx BEN = High to SDOUT Enabled max. SOE tSESZx tCS tCSY tMS tSESZx tCS tCSY tMS CORRECTED DATAOUT tCSY tMSY tM P tMLP tPLP tBEPZx tSEP tCSY tMS Y tMP tMLP tPLP tBEPZx tSE P Parity Out SOE = Low to SDOUT Enabled CBI to C orrected SDOUT CBI to Syndrome MDIN to Corrected SDOUT CBI to Syndrome M DIN to Syndrome M DIN to P arity Out MLE = High to Parity Out PLE = Low to Parity Out BEN = High to P arity Out SOE = Low to Parity Out max. max. max. max. SD 0-31 max. max. max. max. max. max. max. P0-3 SYO Partial Syndrome Out to 1 2 3 4 5 NOTE: 1. Assumes that Memory Data and Checkbits are valid at least 4ns before MLE goes HIGH. Figure 12. 64-Bit Correct Timing (Lower Slice) 34 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE AC TIMING DIAGRAMS--64-BIT CONFIGURATION 64-BIT U/L Slice to 1 2 3 4 5 Propagation Delay Parameter From Name To Min./ Max. MOE tMEM xZ Valid DATAIN tMEM xZ MOE = High to MDOUT Disabled max. MD0-31 (OUTPUT) tMMLS tMM LH tMM LS tMM LH Valid DATAIN tCMLS MDIN Set-up to MLE = Low MDIN Hold to MLE = Low min. min. CBI tCBI CBI Set-up to MLE = Low CBI H old to M LE = Low min. min. tCMLH M LE tMLS (1) tMLS (1) MLEIN = High to SDOUT (1) max. PLE tPLS (1) tPLS (1) PLE = Low to SDOUT (1) max. BEN tBESZx tBESZx BEN = High to SDOUT Enabled max. SOE tSESZx tCS tMS tMS Y tSESZx tCS tMS tMSY CORRECTE D DATAOUT tMP tMLP tPLP tBEPZx tSEP tMP tMLP tPLP tBEPZx tSEP Parity Out SOE = Low to SDOUT Enabled CBI to Corrected SDOUT MDIN to Corrected SDOUT MDIN to Corrected SDOUT MDIN to Parity Out MLE = High to P arity O ut PLE = Low to Parity Out BEN = High to Parity Out SOE = Low to Parity Out max. max. max. max. SD0-31 max. max. max. max. max. P0-3 SYO Partial Checkbits/Syndrome Out to 1 2 3 4 5 NOTE: 1. Assumes that Memory Data and Checkbits are valid at least 4ns before MLE goes HIGH. Figure 13. 64-Bit Correct Timing (Upper Slice) 35 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE AC TIMING DIAGRAMS--64-BIT CONFIGURATION SINGLE 465 to 1 2 3 4 5 Propagation Delay Parameter From Name To Min./ M ax. SOE SD Bus (SO E = Tied high) ValidDATAIN tSSLS tSSLH tSSLH tSSLS SDIN Set-up to SLEIN = Low SDIN Hold to SLEIN = Low m in. m in. SLE (1) tSLC tSLC (1) SLE = H igh to CBO (1) m ax. MOE (MOE = Tied high) MD Bus ValidDATAIN tMM LS tMM LH tMM LH tMM LS MDIN Set-up to MLEIN = Low MDIN Hold to MLEIN = Low min. min. MLE tSC tM C (2) tSC tMC tM LC (2) Bits 32-63 to CBO Bits 0-31 to CBO M LEIN = High to CBO (2) m ax. m ax. m ax. tMLC CBOE tCECZx tCECZx CBOE = Low to CBO Enabled max. CBO Final Checkbits Out to 1 2 3 4 5 NOTES: 1. Assumes that System Data is valid at least 3ns before SLE goes HIGH. 2. Assumes that Memory Data is valid at least 4ns before MLE goes HIGH. Figure 14. 64-Bit Single Chip "Generate Only" Timing 36 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE AC TIMING DIAGRAMS--DIAGNOSTIC TIMING Propagation Delay Parameter From Name To Min./ Max. 465 to 1 2 3 4 5 CBI Checkbits In tCSCS tCSC S C BI Set-up to SYNC LK = High MD Bus Memory DataIN tMSCS tMSCS MDIN Set-up to SYNC LK = H igh min. MLE tMLSCS tMLSCS MLE = H igh Set-up to SYN CLK = High max. SCLKEN tSESCS tSESCH tSESCS tSESCH SCLKEN Set-up to SYNC LK = High SCLKEN = H old After SYNCLK = H igh min. min. SYNCLK tSYNCLK tSCS tCLEAR tSYNCLK tSCS tCLEAR SCLKEN Pulse W itdh SCLKEN = High to SDOUT C LEAR Pulse W itch max. max. max. C LEAR tCLR tCLR Valid DataOUT C LEAR = Low to SDOUT max. SD Bus to 1 2 3 4 5 Figure 15. 32-Bit Diagnostic Timing 37 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE TEST WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS V CC 7.0V 500 VIN Pulse Generator RT D.U.T. 50pF 500 C L SWITCH POSITION Test Open Drain Disable Low Enable Low All Other Tests Open Closed Switch V OUT DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. SET-UP, HOLD, AND RELEASE TIMES DATA INPUT tSU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tREM tH 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V PULSE WIDTH LOW -HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE 1.5V 1.5V tSU tH PROPAGATION DELAY SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V ENABLE AND DISABLE TIMES ENABLE DISABLE 3V CONTROL INPUT tPZL OUTPUT NORMALLY LOW SW ITCH CLOSED tPZH OUTPUT NORMALLY HIGH SWITCH OPEN 3.5V 1.5V 0.3V tPHZ 0.3V 1.5V 0V 0V VOH tPLZ 1.5V 0V 3.5V VOL NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 38 IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXXX Device Type XX Package PQF G Plastic Quad Flatpack Pin Grid Array 49C465 49C465A 32-Bit Flow-thruTM E rror Detection and Correction Unit CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com for Tech Support: logichelp@idt.com (408) 654-6459 39 |
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