View 526A264D_968550.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HB526A264DB Series
1,048,576-word x 64-bit x 2-bank Synchronous Dynamic RAM Module
ADE-203-607 (Z) Preliminary Rev. 0.1 May. 20, 1997 Description
The HB526A264DB is a 1Mx 64 x 2 banks Synchronous Dynamic RAM Small Outline Dual In-line Memory Module (S.O.DIMM), mounted 8 pieces of 16-Mbit SDRAM (HM5216805TT/HM5216805LTT) sealed in TSOP package and 1 piece of serial EEPROM (24C02) for Presence Detect (PD). An outline of the HB526A264DB is 144-pin Zig Zag Dual tabs socket type compact and thin package. Therefore, the HB526A264DB makes high density mounting possible without surface mount technology. The HB526A264DB provides common data inputs and outputs. Decoupling capacitors are mounted beside TSOP on the module board.
Features
* 144-pin Zig Zag Dual tabs socket type Outline: 67.60 mm (Length) x 25.40 mm (Height) x 3.80 mm (Thickness) Lead pitch: 0.80 mm * 3.3V power supply * Clock frequency: 100 MHz / 83 MHz * LVTTL interface * 2 Banks can operates simultaneously and independently * Burst read/write operation and burst read/single write operation capability * Programmable burst length : 1/2/4/8/full page * Programmable burst sequence Sequential/interleave * Full page burst length capability Sequential burst Burst stop capability * Programmable CAS latency : 2/3 * Byte control by DQMB Preliminary:The specification of this device are subject to change without notice. Please contact your nearest Hitachi's Sales Dept. regarding specification.
HB526A264DB Series
* 4096 refresh cycles: 64 ms * 2 variations of refresh Auto refresh Self refresh * Low self refresh current: HB526A264DB-10L (L-version)
Ordering Information
Type No. HB526A264DB-10 HB526A264DB-10L HB526A264DB-12 Frequency 100 MHz 100 MHz 83 MHz Package Small outline DIMM (144-pin) Contact pad Gold
Pin Arrangement
Front Side
1pin 2pin
59pin 60pin
61pin 62pin
143pin 144pin
Back Side
2
HB526A264DB Series
Pin Arrangement (cont.)
Front side Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 Signal name Pin No. VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 VSS DQMB0 DQMB1 VDD A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VDD DQ12 DQ13 DQ14 DQ15 VSS NC NC CK0 VDD RAS 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 Back side Signal name Pin No. NC VSS NC NC VDD DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VDD A6 A8 VSS A9 A10 (AP) VDD DQMB2 DQMB3 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 Signal name Pin No. VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 VSS DQMB4 DQMB5 VDD A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VDD DQ44 DQ45 DQ46 DQ47 VSS NC NC CKE0 VDD CAS 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 Signal name CK1 VSS NC NC VDD DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53 DQ54 DQ55 VDD A7 A11 (BS) VSS NC NC VDD DQMB6 DQMB7 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63
3
HB526A264DB Series
Front side Pin No. 67 69 71 Signal name Pin No. WE S0 NC 139 141 143 Back side Signal name Pin No. VSS SDA VDD 68 70 72 Signal name Pin No. NC NC NC 140 142 144 Signal name VSS SCL VDD
Pin Description
Pin name A0 to A11 Function Address input Row address Column address DQ0 to DQ63 S0 RAS CAS WE DQMB0 to DQMB7 CK0/CK1 CKE0 SDA SCL VDD VSS NC Data-input/output Chip select Row address asserted bank enable Column address asserted Write enable Byte input/output mask Clock input Clock enable Data-input/output for serial PD Clock input for serial PD Power supply Ground No connection A0 to A10 A0 to A8 A11
Bank select address
4
HB526A264DB Series
Serial PD Matrix*1
Byte No. Function described 0 1 2 3 4 5 6 7 8 9 Number of bytes used by module manufacturer Total SPD memory size Memory type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 80 08 04 0B 09 01 40 00 01 A0 128 256 byte SDRAM 11 9 1 64 0 (+) LVTTL CL = 3
Number of row addresses bits 0 Number of column addresses bits Number of banks Module data width 0 0 0
Module data width (continued) 0 Module interface signal levels 0 SDRAM cycle time (highest CAS latency) 10 (10 ns) 12 (12 ns) 1
1 0
1 1
0 1
0 1
0 0
0 1
0 0
0 1
C0 75
10
SDRAM access from Clock (highest CAS latency) -10 (7.5 ns) -12 (9 ns)
1 0 1
0 0 0
0 0 0
1 0 0
0 0 0
0 0 0
0 0 0
0 0 0
90 00 80 Non parity Normal (15.625 s) Self refresh 2M x 8 -- 1 CLK
11 12
Module configuration type Refresh rate/type
13 14 15
SDRAM width Error checking SDRAM width
0 0
0 0 0
0 0 0
0 0 0
1 0 0
0 0 0
0 0 0
0 0 1
08 00 01
0 SDRAM device attributes: minimum clock delay for backto-back random column addresses SDRAM device attributes: Burst lengths supported SDRAM device attributes: number of banks on SDRAM device SDRAM device attributes: CAS latency SDRAM device attributes: S0 latency SDRAM device attributes: WE latency 1 0
16 17
0 0
0 0
0 0
1 0
1 0
1 1
1 0
8F 02
1, 2, 4, 8, full page 2
18 19 20
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
1 0 0
1 0 0
0 1 1
06 01 01
2, 3 0 0
5
HB526A264DB Series
Byte No. Function described 21 22 23 SDRAM module attributes SDRAM device attributes: General SDRAM cycle time (2nd highest CAS latency) -10 (15 ns) -12 (12 ns) 24 SDRAM access from Clock (2nd highest CAS latency) -10 (9 ns) -12 (12 ns) 25 SDRAM cycle time (3rd highest CAS latency) Undefined SDRAM access from Clock (3rd highest CAS latency) Undefined Minimum row precharge time -10 -12 28 Row active to row active min -10 -12 29 RAS to CAS delay min -10 -12 30 Minimum RAS pulse width -10 -12 31 Density of each bank on module Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 0 0 00 0E F0 Non buffer VCC 10% CL = 2
0 1
0 0
1 0
1 1
0 0
0 0
0 0
0 0
30 90
1 0
1 0
0 0
0 0
0 0
0 0
0 0
0 0
C0 00
26
0
0
0
0
0
0
0
0
00
27
0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 x
0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 x
0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 x
1 0 1 1 1 1 1 0 0 0 0 1 1 0 0 x
1 0 0 1 1 1 1 1 0 0 0 1 1 0 0 x
1 1 1 0 1 1 1 0 1 0 0 0 0 1 0 x
1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 x
0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 x
1E 24 14 18 1E 1E 3C 48 04 00 01 38 F9 07 00 xx
30 ns 36 ns 20 ns 24 ns 30 ns 30 ns 60 ns 72 ns 16M byte Future use
32 to 61 Superset information 62 63 SPD data revision code Checksum for bytes 0 to 62 -10/10L -12 64 Manuf act urer's JEDEC ID c ode
HITACHI
65 to 71 Manuf act urer's JEDEC ID c ode 72 Manufacturing location
* 2 (ASCII8bit code)
6
HB526A264DB Series
Byte No. Function described 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number 87 Manufacturer's part number Manufacturer's part number (L-version) 88 89 90 91 92 93 94 Manufacturer's part number Manufacturer's part number Manufacturer's part number Revision code Revision code Manufacturing date Manufacturing date Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x *4 -- 0 0 -- 1 0 -- 1 0 -- 0 0 -- 0 0 -- 1 1 -- 1 1 -- 0 0 -- 66 06 *3 66 MHz CL = 2, 3 1 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 x x 0 0 1 1 1 0 1 1 1 0 0 0 1 1 1 1 0 1 1 1 1 1 x x 0 0 1 1 1 0 1 1 1 0 0 1 1 1 1 0 0 0 0 0 1 0 x x 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 x x 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 0 0 0 0 x x 0 1 0 1 1 0 1 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 x x 0 0 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 x x 48 42 35 32 36 41 32 36 34 44 42 5F 31 30 32 20 4C 20 20 20 30 20 xx xx H B 5 2 6 A 2 6 4 D B -- 1 0 2 (Space) L (Space) (Space) (Space) Initial (Space) Year code (binary) Week code (binary)
95 to 98 Assembly serial number 99 to 125 Manufacturer specific data 126 127 Intel specification frequency Intel specification CAS# latency support
Notes: 1. All serial PD data are not protected. 0: Serial data, "driven Low", 1: Serial data, "driven High" 2. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows "J" on ASCII code.) 3. All bits of 99 through 125 are not defined ("1" or "0"). 4. Bytes 95 through 98 are assembly serial number.
7
HB526A264DB Series
Block Diagram
WE S0
WE DQMB0 8 DQ0 to DQ7 N0, N1 DQM I/O0 to I/O7 WE DQM 8 DQ8 to DQ15 N2, N3 I/O0 to I/O7 WE DQMB2 8 DQ16 to DQ23 N8, N9 DQM I/O0 to I/O7 WE DQM 8 N10, N11 I/O0 to I/O7
CS
WE DQMB4 8 DQ32 to DQ39 N4, N5 DQM I/O0 to I/O7 WE DQM 8 DQ40 to DQ47 N6, N7 I/O0 to I/O7 WE DQMB6 DQM 8 N12, N13 I/O0 to I/O7 WE DQM 8 N14, N15 I/O0 to I/O7
CS
D0
D4
CS
CS
DQMB1
D1
DQMB5
D5
CS
CS
D2
DQ48 to DQ55
D6
CS
CS
DQMB3 DQ24 to DQ31
D3
DQMB7 DQ56 to DQ63
D7
RAS CAS A0 to A11 CKE0 R0 CK0 R1
RAS (D0 to D7) CAS (D0 to D7) A0 to A11(D0 to D7) CKE (D0 to D7) CLK (D0,D4) CLK (D1,D5) R2 VSS SCL
Serial PD SCL A0 A1 A2 U0 SDA SDA
CK1 VDD
C0-C15
CLK (D2,D6) R3 CLK (D3,D7) VDD (D0 to D7, U0)
C100-C107
Notes : 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state.
VSS
VSS (D0 to D7, U0) * D0 to D7 : HM5216805TT U0 : 24C02 C0 to C17 : 0.33 F C100 to C107 : 0.1 F N0 to N15 : Network Resistors (10 ) R0 to R3 : Chip Resistors
8
HB526A264DB Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Note: 1. Respect to V SS . Symbol VT VDD Iout PT Topr Tstg Value -1.0 to +4.6 -1.0 to +4.6 50 8.0 0 to +70 -55 to +125 Unit V V mA W C C Note 1 1
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Symbol VDD VSS Input high voltage Input low voltage VIH VIL Min 3.0 0 2.0 -0.3 Typ 3.3 0 -- -- Max 3.6 0 4.6 0.8 Unit V V V V 1, 2 1, 3 Notes 1
Notes: 1. All voltage referred to VSS 2. VIH (max) = 5.5 V for pulse width 5 ns 3. VIL (min) = -1.0 V for pulse width 5 ns
9
HB526A264DB Series
DC Characteristics (Ta = 0 to 70C, VDD = 3.3 V 0.3 V, V SS = 0 V)
HB526A264DB -10/10L Parameter Operating current Standby current (Bank Disable) Symbol I CC1 I CC2 Min -- -- -- Max 800 24 16 -12 Min -- -- -- Max 680 24 16 Unit mA mA mA Test conditions Burst length = 1 t RC = min CKE0 = VIL, t CK = min Notes 1, 2, 4 5
CKE0 = VIL 6 CK0/CK1 = VIL or VIH Fixed CKE0 = VIH, NOP command t CK = min CKE0 = VIL, t CK = min, DQ = High-Z CKE0 = VIH, NOP command t CK = min, DQ = High-Z t CK = min, BL = 4 3
--
320
--
280
mA
Active standby current (Bank active)
I CC3
--
56
--
56
mA
1, 2
--
360
--
320
mA
1, 2, 3
Burst operating current (CAS Latency = 2) (CAS Latency = 3) Refresh current Self refresh current
I CC4 I CC4 I CC5 I CC6
-- -- -- -- -- -10 -10 2.4 --
800 1200 680 16 2 10 10 -- 0.4
-- -- -- -- -- -10 -10 2.4 --
680 1000 560 16 2 10 10 -- 0.4
mA mA mA mA mA A A V V
1, 2, 4
t RC = min VIH VDD - 0.2 VIL 0.2 V 0 Vin VDD 0 Vout VDD DQ = disable I OH = -2 mA I OL = 2 mA 7
Self refresh current (L-version) I CC6 Input leakage current Output leakage current Output high voltage Output low voltage I LI I LO VOH VOL
Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signal transition is once per two CK0/CK1 cycles. 4. Input signal transition is once per one CK0/CK1 cycle. 5. After power down mode, CK0/CK1 operating current. 6. After power down mode, no CK0/CK1 operating current. 7. After self refresh mode set, self refresh current.
10
HB526A264DB Series
Capacitance (Ta = 25C, VDD = 3.3 V 0.3 V)
Parameter Input capacitance (Address) Symbol CIN Max 60 60 60 25 20 Unit pF pF pF pF pF Notes 1, 3 1, 3 1, 3 1, 2, 3 1, 3
Input capacitance (RAS, CAS, WE, CK0/CK1, CKE0) CIN Input capacitance (S0) Input capacitance (DQMB0 to DQMB7) Input/Output capacitance (DQ0 to DQ63) CIN CIN CI/O
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. DQMB = VIH to disable Dout. 3. This parameter is sampled and not 100% tested.
AC Characteristics (Ta = 0 to 70C, VDD = 3.3 V 0.3 V, V SS = 0 V)
HB526A264DB -10/10L Parameter System clock cycle time (CAS Latency = 2) (CAS Latency = 3) CK0/CK1 high pulse width CK0/CK1 low pulse width Access time from CK0/CK1 (CAS Latency = 2) (CAS Latency = 3) Data-out hold time CK0/CK1 to Data-out low impedance CK0/CK1 to Data-out high impedance Data-in setup time Data in hold time Address setup time Address hold time CKE0 setup time CKE0 setup time for power down exit CKE0 hold time Symbol t CK t CK t CKH t CKL t AC t AC t OH t LZ t HZ t DS t DH t AS t AH t CES t CESP t CEH Min 15 10 3 3 -- -- 3 0 -- 2 1 2 1 2 2 1 Max -- -- -- -- 9 7.5 -- -- 7 -- -- -- -- -- -- -- -12 Min 18 12 4 4 -- -- 3 0 -- 3 1 3 1 3 3 1 Max -- -- -- -- 12 9 -- -- 9 -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns 1, 2 1, 2, 3 1, 4 1 1 1 1 1, 5 1 1 ns ns ns 1 1 1, 2 Unit ns Notes 1
11
HB526A264DB Series
AC Characteristics (Ta = 0 to 70C, VDD = 3.3 V 0.3 V, V SS = 0 V) (cont)
HB526A264DB -10/10L Parameter Command (S0, RAS, CAS, WE, DQMB) setup time Command (S0, RAS, CAS, WE, DQMB) hold time Ref/Active to Ref/Active command period Active to precharge command period Active to precharge on full page mode Active command to column command (same bank) Precharge to active command period Symbol t CS t CH t RC t RAS t RASC t RCD t RP Min 2 1 90 60 -- 30 30 15 20 1 -- Max -- -- -- -12 Min 3 1 108 Max -- -- -- Unit ns ns ns Notes 1 1 1 1 1 1 1 1 1
120000 72 120000 -- -- -- -- -- 5 64 36 36 18 24 1 --
120000 ns 120000 ns -- -- -- -- 5 64 ns ns ns ns ns ms
Write recovery or data in to precharge lead t DPL time Active (a) to Active (b) command period Transition time (rise to fall) Refresh period Notes: 1. 2. 3. 4. 5. t RRD tT t REF
AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.40 V. Access time is measured at 1.40 V. Load condition is C L = 50 pF with current source. t LZ (max) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES defines CKE0 setup time to CKE0 rising edge except power down exit command.
Test Conditions * Input and output timing reference levels: 1.4 V * Input waveform and output load: See following figures
2.8 V
input
V SS
80% 20%
I/O
50 +1.4 V CL
t
T
tT
12
HB526A264DB Series
Relationship Between Frequency and Minimum Latency
HB526A264DB Parameter Frequency (MHz) tCK (ns) Active command to column command (same bank) Active command to active command (same bank) Active command to precharge command (same bank) Precharge command to active command (same bank) Write recovery or data input to precharge command (same bank) Active command to active command (different bank) Self refresh exit time Last data in to active command (Auto precharge, same bank) Self refresh exit to command input Precharge command to high impedance (CAS latency = 3) (CAS latency = 2) Last data out to active command (auto precharge) (same bank) Last data out to precharge (early precharge) (CAS latency = 3) (CAS latency = 2) Column command to column command Write command to data in latency DQMB to data in DQMB to data out CKE0 to CK0/CK1 disable Symbol t RCD t RC t RAS t RP t DPL t RRD I SREX I APW I SEC I HZP I HZP I APR -10/10L 100 66 10 15 3 9 6 3 2 2 2 5 9 3 -- 1 2 6 4 2 1 2 2 3 6 3 2 1 33 30 1 3 2 1 1 1 2 2 3 3 2 1 -12 83 12 3 9 6 3 2 2 2 5 9 3 -- 1 55 18 2 6 4 2 1 2 2 3 6 3 2 1 28 36 1 3 2 1 1 1 2 2 3 3 2 1 Notes 1 = [tRAS + tRP] 1 1 1 1 1 2 = [tDPL + tRP] = [tRC]
I EP I EP I CCD I WCD I DID I DOD I CLE
-2 -- 1 0 0 2 1
-2 -1 1 0 0 2 1
-2 -1 1 0 0 2 1
-2 -- 1 0 0 2 1
-2 -1 1 0 0 2 1
-2 -1 1 0 0 2 1
13
HB526A264DB Series
Relationship Between Frequency and Minimum Latency (cont)
HB526A264DB Parameter Frequency (MHz) tCK (ns) Register set to active command S0 to command disable Power down exit to command input Burst stop to output valid data hold (CAS latency = 3) (CAS latency = 2) Burst stop to output high impedance (CAS latency = 3) (CAS latency = 2) Burst stop to write data ignore Symbol t RSA I CDD I PEC I BSR I BSR I BSH I BSH I BSW -10/10L 100 66 10 15 1 0 1 2 -- 3 -- 0 1 0 1 2 1 3 2 0 33 30 1 0 1 2 1 3 2 0 -12 83 12 1 0 1 2 -- 3 -- 0 55 18 1 0 1 2 1 3 2 0 28 36 1 0 1 2 1 3 2 0 Notes
Notes: 1. t RCD to tRRD are recommended value. 2. When self refresh exit is executed, CKE0 should be kept "H" longer than l SREX from exit cycle.
14
HB526A264DB Series
Pin Functions
CK0/CK1 (input pin): CK0/CK1 is the master clock input to this pin. The other input signals are referred at CK0/CK1 rising edge. S0 (input pin): When S0 is Low, the command input cycle becomes valid. When S0 is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RAS, CAS, and WE (input pins): Although these pin names are the same as those of conventional DRAM modules, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A10 (input pins): Row address (AX0 to AX10) is determined by A0 to A10 level at the bank active command cycle CK0/CK1 rising edge. Column address (AY0 to AY8) is determined by A0 to A8 level at the read or write command cycle CK0/CK1 rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by A11 (BS) is precharged. A11 (input pin): A11 is a bank select signal (BS). The memory array of the HB526A264DB is divided into bank 0 and bank 1, both which contain 2048 row x 512 column x 8 bits. If A11 is Low, bank 0 is selected, and if A11 is High, bank 1 is selected. CKE0 (input pin): This pin determines whether or not the next CK0/CK1 is valid. If CKE0 is High, the next CK0/CK1 rising edge is valid. If CKE0 is Low, the next CK0/CK1 rising edge is invalid. This pin is used for power-down and clock suspend modes. DQMB (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the DQMB is Low, the output buffer becomes Low-Z. Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data is written. DQ0 to DQ63 (DQ pins): Data is input to and output from these pins. These pins are the same as those of a conventional DRAM module. VDD (power supply pins): 3.3 V is applied. VSS (power supply pins): Ground is connected.
15
HB526A264DB Series
Command Operation
Command Truth Table The synchronous DRAM module recognizes the following commands specified by the S0, RAS, CAS, WE and address pins.
Function Ignore command No operation Burst stop in full page Column address and read command Read with auto-precharge Column address and write command Write with auto-precharge Row address strobe and bank act. Precharge select bank Precharge all bank Refresh Mode register set Symbol DESL NOP BST READ READ A WRIT WRIT A ACTV PRE PALL CKE0 n-1 n H H H H H H H H H H x x x x x x x x x x V x S0 H L L L L L L L L L L L RAS CAS WE x H H H H H H L L L L L x H H L L L L H H H L L x H L H H L L H L L H L A0 A11 A10 to A9 x x x V V V V V V x x V x x x L H L H V L H x V x x x V V V V V x x x V
REF/SELF H MRS H
Note: H: VIH. L: VIL. x: V IH or VIL. V: Valid address input
Ignore command [DESL]: When this command is set (S0 is High), the synchronous DRAM module ignore command input at the clock. However, the internal status is held. No operation [NOP]: This command is not an execution command. However, the internal operations continue. Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page (512)), and is illegal otherwise. Full page burst continues until this command is input. When data input/output is completed for a full-page of data (512), it automatically returns to the start address, and input/output is performed repeatedly. Column address strobe and read command [READ]: This command starts a read operation. In addition, the start address of burst read is determined by the column address (AY0 to AY8) and the bank select address (BS). After the read operation, the output buffer becomes High-Z. Read with auto-precharge [READ A]: This command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4, or 8. When the burst length is full-page (512), this command is illegal.
16
HB526A264DB Series
Column address strobe and write command [WRIT]: This command starts a write operation. When the burst write mode is selected, the column address (AY0 to AY8) and the bank select address (A11) become the burst write start address. When the single write mode is selected, data is only written to the location specified by the column address (AY0 to AY8) and the bank select address (A11). Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation after a burst write with a length of 1, 2, 4, or 8, or after a single write operation. When the burst length is full-page (512), this command is illegal. Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by A11 (BS) and determines the row address (AX0 to AX10). When A11 is Low, bank 0 is activated. When A11 is High, bank 1 is activated. Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by A11. If A11 is Low, bank 0 is selected. If A11 is High, bank 1 is selected. Precharge all banks [PALL]: This command starts a precharge operation for all banks. Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE0 truth table section. Mode register set [MRS]: Synchronous DRAM module has a mode register that defines how it operates. The mode register is specified by the address pins (A0 to A11) at the mode register set cycle. For details, refer to the mode register configuration. After power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register. DQMB Truth Table
CKE0 n-1 H H
Function Write enable/output enable Write inhibit/output disable Note: H: VIH. L: VIL. x: V IH or VIL. I DOD is needed.
Symbol ENB MASK
n x x
DQMB L H
The HB526A264DB series can mask input/output data by means of DQMB During reading, the output buffer is set to Low-Z by setting DQMB to Low, enabling data output. On the other hand, when DQMB is set to High, the output buffer becomes High-Z, disabling data output. During writing, data is written by setting DQMB to Low. When DQMB is set to High, the previous data is held (the new data is not written). Desired data can be masked during burst read or burst write by setting DQMB. For details, refer to the DQMB control section of the HB526A264DB operating instructions.
17
HB526A264DB Series
CKE0 Truth Table
CKE0 n-1 n H L L REF SELF H H H H Self-refresh Self refresh exit SELFX L L Power down Power down exit L L Note: H: VIH. L: VIL. x: V IH or VIL. L L H H L L L H H H H S0 H x x L L L H L H L H RAS x x x L L H x H x H x CAS x x x L L H x H x H x WE x x x H H H x H x H x
Current state Active Any Clock suspend Idle Idle Idle
Function Clock suspend mode entry Clock suspend Clock suspend mode exit Auto refresh command Self refresh entry Power down entry
Address x x x x x x x x x x x
Clock suspend mode entry: The synchronous DRAM module enters clock suspend mode from active mode by setting CKE0 to Low. The clock suspend mode changes depending on the current status (1 clock before) as shown below. ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining the bank active status. READ suspend and READ A suspend: The data being output is held (and continues to be output). WRITE suspend and WRIT A suspend: In this mode, external signals are not accepted. However, the internal state is held. Clock suspend: During clock suspend mode, keep the CKE0 to Low. Clock suspend mode exit: The synchronous DRAM module exits from clock suspend mode by setting CKE0 to High during the clock suspend state. IDLE: In this state, all banks are not selected, and completed precharge operation. Auto refresh command [REF]: When this command is input from the IDLE state, the synchronous DRAM module starts auto refresh operation. (The auto refresh is the same as the CBR refresh of conventional DRAM module.) During the auto refresh operation, refresh address and bank select address are generated inside the synchronous DRAM module. For every auto refresh cycle, the internal address counter is updated. Accordingly, 4096 times are required to refresh the entire memory. Before executing the auto refresh command, all the banks must be in the IDLE state. In addition, since the precharge for all banks is automatically performed after auto refresh, no precharge command is required after auto refresh.
18
HB526A264DB Series
Self refresh entry [SELF]: When this command is input during the IDLE state, the synchronous DRAM module starts self refresh operation. After the execution of this command, self refresh continues while CKE0 is Low. Since self refresh is performed internally and automatically, external refresh operations are unnecessary. Power down mode entry: When this command is executed during the IDLE state, the synchronous DRAM module enters power down mode. In power down mode, power consumption is suppressed by cutting off the initial input circuit. Self refresh exit: When this command is executed during self refresh mode, the synchronous DRAM module can exit from self refresh mode. After exiting from self refresh mode, the synchronous DRAM module enters the IDLE state. Power down exit: When this command is executed at the power down mode, the synchronous DRAM module can exit from power down mode. After exiting from power down mode, the synchronous DRAM module enters the IDLE state. Function Truth Table The following table shows the operations that are performed when each command is issued in each mode of the synchronous DRAM module.
Current state S0 Precharge H L L L L L L L L Idle H L L L L L L L L RAS CAS WE x H H H H L L L L x H H H H L L L L x H H L L H H L L x H H L L H H L L x H L H L H L H L x H L H L H L H L Address x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE Command DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS Operation Enter IDLE after t RP Enter IDLE after t RP NOP ILLEGAL ILLEGAL ILLEGAL NOP ILLEGAL ILLEGAL NOP NOP NOP ILLEGAL ILLEGAL Bank and row active NOP Refresh Mode register set
19
HB526A264DB Series
Current state S0 Row active H L L L L L L L L Read H L L L L L L L L Read with H auto-precharge L L L L L L L L RAS CAS WE x H H H H L L L L x H H H H L L L L x H H H H L L L L x H H L L H H L L x H H L L H H L L x H H L L H H L L x H L H L H L H L x H L H L H L H L x H L H L H L H L Address x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE Command DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS Operation NOP NOP NOP Begin read Begin write Other bank active ILLEGAL on same bank*3 Precharge ILLEGAL ILLEGAL Continue burst to end Continue burst to end Burst stop to full page Continue burst read to CAS latency and new read Term burst read/start write Other bank active ILLEGAL on same bank*3 Term burst read and Precharge ILLEGAL ILLEGAL Continue burst to end and precharge Continue burst to end and precharge ILLEGAL ILLEGAL ILLEGAL Other bank active ILLEGAL on same bank*3 ILLEGAL ILLEGAL ILLEGAL
20
HB526A264DB Series
Current state S0 Write H L L L L L L L L Write with H auto-precharge L L L L L L L L Refresh (auto refresh) H L L L L L L L L RAS CAS WE x H H H H L L L L x H H H H L L L L x H H H H L L L L x H H L L H H L L x H H L L H H L L x H H L L H H L L x H L H L H L H L x H L H L H L H L x H L H L H L H L Address x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE Command DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS Operation Continue burst to end Continue burst to end Burst stop on full page Term burst and new read Term burst and new write Other bank active ILLEGAL on same bank*3 Term burst write and precharge*2 ILLEGAL ILLEGAL Continue burst to end and precharge Continue burst to end and precharge ILLEGAL ILLEGAL ILLEGAL Other bank active ILLEGAL on same bank*3 ILLEGAL ILLEGAL ILLEGAL Enter IDLE after t RC Enter IDLE after t RC Enter IDLE after t RC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Notes: 1. H: VIH. L: VIL. x: V IH or VIL. The other combinations are inhibit. 2. An interval of t DPL is required between the final valid data input and the precharge command. 3. If tRRD is not satisfied, this operation is illegal.
21
HB526A264DB Series
From [PRECHARGE] To [DESL], [NOR] or [BST]: When these commands are executed, the synchronous DRAM module enters the IDLE state after tRP has elapsed from the completion of precharge.
From [IDLE] To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation. To [ACTV]: The bank specified by the address pins and the ROW address is activated. To [REF], [SELF]: The synchronous DRAM module enters refresh mode (auto refresh or self refresh). To [MRS]: The synchronous DRAM module enters the mode register set cycle.
From [ROW ACTIVE] To [DESL], [NOP] or [BST]: These commands result in no operation. To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.) To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.) To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands set the synchronous DRAM module to precharge mode. (However, an interval of t RAS is required.)
From [READ] To [DESL], [NOP]: These commands continue read operations until the burst operation is completed. To [BST]: This command stops a full-page burst. To [READ], [READ A]: Data output by the previous read command continues to be output. A f t e r CAS latency, the data output resulting from the next command will start. To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle. To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop a burst read, and the synchronous DRAM module enters precharge mode.
22
HB526A264DB Series
From [READ with AUTO PRECHARGE] To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the synchronous DRAM module then enters precharge mode. To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command.
From [WRITE] To [DESL], [NOP]: These commands continue write operations until the burst operation is completed. To [BST]: This command stops a full-page burst. To [READ], [READ A]: These commands stop a burst and start a read cycle. To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle. To [ACTV]: This command makes the other bank active. (However, an interval of t RRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop burst write and the synchronous DRAM module then enters precharge mode.
From [WRITE with AUTO-PRECHARGE] To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the synchronous DRAM module enters precharge mode. To [ACTV]: This command makes the other bank active. (However, an interval of tRC is required.) Attempting to make the currently active bank active results in an illegal command.
From [REFRESH] To [DESL], [NOP], [BST]: After an auto-refresh cycle (after t RC ), the synchronous DRAM module automatically enters the IDLE state.
23
HB526A264DB Series
Simplified State Diagram
SELF REFRESH SR ENTRY SR EXIT
MODE REGISTER SET
MRS IDLE
REFRESH
*1 AUTO REFRESH
CKE CKE_ IDLE POWER DOWN
ACTIVE CLOCK SUSPEND
ACTIVE
CKE_ CKE ROW ACTIVE
BST (on full page)
BST (on full page)
WRITE Write WRITE SUSPEND CKE_ WRITE CKE WRITE WITH AP CKE_ WRITEA SUSPEND WRITEA CKE PRECHARGE READ WITH AP WRITE WITH AP READ READ WITH AP WRITE
READ Read CKE_ READ CKE READ WITH AP CKE_ READA CKE PRECHARGE READA SUSPEND READ SUSPEND
WRITE WITH AP
PRECHARGE
POWER APPLIED
POWER ON
PRECHARGE PRECHARGE
Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state.
24
HB526A264DB Series
Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A11) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins. A11, A10, A9, A8: (OPCODE): The synchronous DRAM module has two types of write modes. One is the burst write mode, and the other is the single write mode. These bits specify write mode. Burst read and BURST WRITE: Burst write is performed for the specified burst length starting from the column address specified in the write cycle. Burst read and SINGLE WRITE: Data is only written to the column address specified during the write cycle, regardless of the burst length. A7: Keep this bit Low at the mode register set cycle. A6, A5, A4: (LMODE): These pins specify the CAS latency. A3: (BT): A burst type is specified. When full-page burst is performed, only "sequential" can be selected. A2, A1, A0: (BL): These pins specify the burst length.
A11
A10
A9
A8
A7 0
A6
A5
A4
A3 BT
A2
A1 BL
A0
OPCODE
LMODE
A6 A5 A4 CAS Latency 0 0 0 0 1 0 0 1 1 X 0 1 0 1 X R -- 2 3 R
A3 Burst Type 0 Sequential 1 Interleave A2 A1 A0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Burst Length BT=0 1 2 4 8 R R R F.P. BT=1 1 2 4 8 R R R R
A11 A10 0 X X X 0 X X X
A9 0 0 1 1
A8 0 1 0 1
Write mode Burst read and burst write R Burst read and SINGLE WRITE R
F.P. =Full Page (512) R is Reserved(inhibit) X: 0 or 1
25
HB526A264DB Series
Burst Sequence
Burst length = 2 Starting Ad. Addressing(decimal) A0 0 1 Sequence 0, 1, 1, 0, Interleave 0, 1, 1, 0, Burst length = 4 Starting Ad. Addressing(decimal) A1 0 0 1 1 Burst length = 8 Starting Ad. A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Addressing(decimal) Interleave 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 6, 2, 3, 0, 1, 6, 7, 4, 5, 3, 2, 1, 0, 7, 6, 5, 4, 4, 5, 6, 7, 0, 1, 2, 3, 5, 4, 7, 6, 1, 0, 3, 2, 6, 7, 4, 5, 2, 3, 0, 1, 7, 6, 5, 4, 3, 2, 1, 0, 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 0, 2, 3, 4, 5, 6, 7, 0, 1, 3, 4, 5, 6, 7, 0, 1, 2, 4, 5, 6, 7, 0, 1, 2, 3, 5, 6, 7, 0, 1, 2, 3, 4, 6, 7, 0, 1, 2, 3, 4, 5, 7, 0, 1, 2, 3, 4, 5, 6, A0 Sequence A0 0 1 0 1 Sequence 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, Interleave 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0,
26
HB526A264DB Series
Operation of HB526A264DB Series
Read/Write Operations Bank active: Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACTV) command. Either bank 0 or bank 1 is activated according to the status of the A11 pin, and the row address (AX0 to AX10) is activated by the A0 to A10 pins at the bank active command cycle. An interval of tRCD is required between the bank active command input and the following read/write command input. Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in the (CAS Latency-1) cycle after read command set. HB526A264DB series can perform a burst read operation. The burst length can be set to 1, 2, 4, 8 or full-page (512). The start address for a burst read is specified by the column address (AY0 to AY8) and the bank select address (A11) at the read command set cycle. In a read operation, data output starts after the number of cycles specified by the CAS Latency. The CAS Latency can be set to 2 or 3. When the burst length is 1, 2, 4, or 8, the Dout buffer automatically becomes High-Z at the next cycle after the successive burst-length data has been output. When the burst length is full-page (512), data is repeatedly output until the burst stop command is input. The CAS latency and burst length must be specified at the mode register. CAS Latency
CK0/CK1 t RCD Command
ACTV READ
Address
Row
Column
CL = 2 Dout CL = 3
out 0
out 1 out 0
out 2 out 1
out 3 out 2 out 3 CL: CAS Latency Burst Length = 4
27
HB526A264DB Series
Burst Length
CK0/CK1
t RCD
Command Address
ACTV READ
Row
Column
BL = 1 BL = 2
out 0 out 0 out 1
Dout
out 0 out 1 out 2 out 3
BL = 4
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7
BL = 8
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 8
out 255
out 0
out 1
BL = full page (512)
BL: Burst Length CAS Latency = 2
Write operation: Burst write or single write mode is selected by the OPCODE (A11, A10, A9, A8) of the mode register. Burst write A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the same cycle as a write command set. (The latency of data input is 0.) The burst length can be set to 1, 2, 4, 8, and full-page, like burst read operations. The write start address is specified by the column address (AY0 to AY8) and the bank select address (A11) at the write command set cycle.
CK0/CK1
t RCD
Command Address
ACTV WRIT
Row
Column
BL = 1 BL = 2
in 0 in 0 in 1 in 1 in 1 in 1 in 2 in 2 in 2 in 3 in 3 in 3 in 4 in 4 in 5 in 5 in 6 in 6 in 7 in 7 in 8
in 255
Din
in 0
BL = 4
in 0
BL = 8
in 0 in 0 in 1
BL = full page (512)
CAS Latency = 2, 3
28
HB526A264DB Series
Single write A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write operation, data is only written to the column address (AY0 to AY8) and the bank select address (A11) specified by the write command set cycle without regard to the burst length setting. (The latency of data input is 0).
CK0/CK1 t RCD Command
ACTV WRIT
Address Din
Row
Column
in 0 CAS Latency = 2, 3 Burst Length = 1, 2, 4, 8 full page
29
HB526A264DB Series
Auto Precharge Read with auto precharge: In this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval defined by IAPR is required before execution of the next command.
CAS latency 3 2 Precharge start cycle 2 cycle before the final data is output 1 cycle before the final data is output
CK0/CK1
CL=2 Command
READ
ACTV out0 out1 out2 out3 lAPR
Dout
CL=3 Command
READ
ACTV out0 out1 out2 out3 lAPR
Dout
Note: Internal auto-precharge starts at the timing indicated by " ". At CLK = 50 MHz (I APR changes depending on the operating frequency.)
30
HB526A264DB Series
Write with auto precharge: In this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval of IAPW is required between the final valid data input and input of the next command. Burst Write (Burst Length = 4)
CK0/CK1
Command
WRIT
ACTV
Din
in0
in1
in2
in3 lAPW
Single Write
CK0/CK1
Command
WRIT
ACTV
Din
in lAPW
31
HB526A264DB Series
Full-page Burst Stop Burst stop command during burst read: The burst stop (BST) command is used to stop data output during a full-page burst. The BST command sets the output buffer to High-Z and stops the full-page burst read. The timing from command input to the last data changes depending on the CAS latency setting. In addition, the BST command is valid only during full-page burst mode, and is invalid with burst lengths 1, 2, 4 and 8.
CAS latency 2 3 BST to valid data 1 2 BST to high impedance 2 3
CAS Latency = 2, Burst Length = full page
CK0/CK1 Command Dout
out out out out BST
out
out
l BSH = 2 cycle l BSR = 1 cycle
CAS Latency = 3, Burst Length = full page
CK0/CK1
Command
BST
Dout
out
out
out
out
out
out
out
l BSR = 2 cycle
l BSH = 3 cycle
32
HB526A264DB Series
Burst stop command at burst write: The burst stop command (BST command) is used to stop data input during a full-page burst write. No data is written in the same cycle as the BST command and in subsequent cycles. In addition, the BST command is only valid during full-page burst mode, and is invalid with burst lengths of 1, 2, 4 and 8. And an interval of tDPL is required between the BST command and the next precharge command. Burst Length = full page
CK0/CK1 Command Din in in t DPL I BSW = 0 cycle BST PRE/PALL
33
HB526A264DB Series
Command Intervals Read command to Read command interval: Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 cycle. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. READ to READ Command Interval (same ROW address in same bank)
CK0/CK1 Command
Address (A0-A10)
BS (A11)
READ
ACTV
READ
Row
Column A Column B
Dout
Bank0 Active Column =A Column =B Read Read
out A0 out B0 out B1 out B2 out B3 Column =A Column =B Dout Dout
CAS Latency = 3 Burst Length = 4 Bank0
Same bank, different ROW address: When the ROW address changes on same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank-active command. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. READ to READ Command Interval (different bank)
CK0/CK1 Command
Address (A0-A10)
BS (A11)
ACTV ACTV READ READ
Row 0
Row 1
Column A Column B
Dout
Bank0 Active Bank1 Bank0 Bank1 Active Read Read
out A0 out B0 out B1 out B2 out B3 Bank0 Bank1 Dout Dout
CAS Latency = 3 Burst Length = 4
34
HB526A264DB Series
Write command to Write command interval: Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 cycle. In the case of burst writes, the second write command has priority. WRITE to WRITE Command Interval (same ROW address in same bank)
CK0/CK1 Command
Address (A0-A10)
BS (A11) Din
Bank0 Active in A0 in B0 in B1 in B2 in B3 ACTV WRIT WRIT
Row
Column A Column B
Column =A Column =B Write Write
Burst Write Mode Burst Length = 4 Bank0
Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank-active command. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. In the case of burst write, the second write command has priority. WRITE to WRITE Command Interval (different bank)
CK0/CK1 Command
Address (A0-A10)
BS (A11)
ACTV ACTV WRIT WRIT
Row 0
Row 1
Column A Column B
Din
Bank0 Active
in A0
in B0
in B1
in B2
in B3
Bank1 Bank0 Bank1 Active Write Write
Burst Write Mode Burst Length = 4
35
HB526A264DB Series
Read command to Write command interval: Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 cycle. However, DQMB must be set High so that the output buffer becomes High-Z before data input. READ to WRITE Command Interval (1)
CK0/CK1 Command
CL=2
DQMB
READ WRIT
CL=3 Din
in B0 High-Z in B1 in B2 in B3
Dout
Burst Length = 4 Burst write
READ to WRITE Command Interval (2)
CK0/CK1 Command
READ WRIT
DQMB 2 clock
CL=2
High-Z High-Z
Dout
CL=3 Din
Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bankactive command. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. However, DQMB must be set High so that the output buffer becomes High-Z before data input.
36
HB526A264DB Series
Write command to Read command interval: Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 cycle. However, in the case of a burst write, data will continue to be written until one cycle before the read command is executed. WRITE to READ Command Interval (1)
CK0/CK1 Command WRIT READ
DQMB
Din Dout
in A0 out B0 Column = A Write CAS Latency Column = B Dout out B1 out B2 out B3 Burst Write Mode CAS Latency = 2 Burst Length = 4 Bank 0
Column = B Read
WRITE to READ Command Interval (2)
CK0/CK1 Command WRIT READ
DQMB
Din Dout
in A0
in A1 out B0 out B1 out B2 out B3 Burst Write Mode CAS Latency = 2 Burst Length = 4 Bank 0
Column = A Write
CAS Latency Column = B Read Column = B Dout
Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-active command. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. However, in the case of a burst write, data will continue to be written until one cycle before the read command is executed (as in the case of the same bank and the same address).
37
HB526A264DB Series
Read command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one cycle. However, since the output buffer then becomes High-Z after the cycles defined by I HZP, there is a possibility that burst read data output will be interrupted, if the precharge command is input during burst read. To read all data by burst read, the cycles defined by IEP must be assured as an interval from the final data output to precharge command execution. READ to PRECHARGE Command Interval (same bank): To output all data CAS Latency = 2, Burst Length = 4
CK0/CK1 Command READ
PRE/PALL
Dout CL=2
out A0
out A1
out A2
out A3
l EP = -1 cycle
CAS Latency = 3, Burst Length = 4
CK0/CK1 Command READ
PRE/PALL
Dout CL=3
out A0
out A1
out A2 l EP = -2 cycle
out A3
38
HB526A264DB Series
READ to PRECHARGE Command Interval (same bank): To stop output data CAS Latency = 2, Burst Length = 1, 2, 4, 8
CK0/CK1 Command READ
PRE/PALL
Dout
out A0 l HZP =2
High-Z
CAS Latency = 3, Burst Length = 1, 2, 4, 8
CK0/CK1 Command READ
PRE/PALL
Dout l HZP =3
out A0
High-Z
39
HB526A264DB Series
Write command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 cycle. WRITE to PRECHARGE Command Interval (same bank): However, if the burst write operation is unfinished, the input data must be masked by means of DQMB for assurance of the cycle defined by tDPL. WRITE to PRECHARGE Command Interval (same bank) Burst Length = 4 (To stop write operation)
CK0/CK1
Command
WRIT
PRE/PALL
DQMB
Din
t DPL
CK0/CK1
Command
WRIT
PRE/PALL
DQMB
Din
in A0
in A1
t DPL
Burst Length = 4 (To write all data)
CK0/CK1
Command
WRIT
PRE/PALL
DQMB
Din
in A0
in A1
in A2
in A3
t DPL
40
HB526A264DB Series
Bank active command interval: Same bank: The interval between the two bank-active commands must be no less than tRC. In the case of different bank-active commands: The interval between the two bank-active commands must be no less than tRRD. Bank active to bank active for same bank
CK0/CK1
Command
ACTV
ACTV
Address (A0-A10) BS (A11)
ROW
ROW
t RC Bank 0 Active Bank 0 Active
Bank active to bank active for different bank
CK0/CK1 ACTV ACTV
Command Address (A0-A10)
ROW:0
ROW:1
BS (A11)
t RRD Bank 0 Active Bank 1 Active
41
HB526A264DB Series
Mode register set to Bank-active command interval: The interval between setting the mode register and executing a bank-active command must be no less than tRSA .
CK0/CK1
Command
MRS
ACTV
Address (A0-A11)
CODE
BS & ROW
t RSA Mode Register Set Bank Active
42
HB526A264DB Series
DQMB Control The DQMB mask the lower and upper bytes of the DQ data, respectively. The timing of DQMB is different during reading and writing. Reading: When data is read, the output buffer can be controlled by DQMB. By setting DQMB to Low, the output buffer becomes Low-Z, enabling data output. By setting DQMB to High, the output buffer becomes High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency of DQMB during reading is 2.
CK0/CK1 DQMB Dout High-Z out 0 out 1 out 3
lDOD = 2 Latency
Writing: Input data can be masked by DQMB. By setting DQMB to Low, data can be written. In addition, when DQMB is set to High, the corresponding data is not written, and the previous data is held. The latency of DQMB during writing is 0.
CK0/CK1 DQMB
,
Din in 0 in 1 in 3 l DID = 0 Latency 43
HB526A264DB Series
Refresh Auto-refresh: All the banks must be precharged before executing an auto-refresh command. Since the autorefresh command updates the interval counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external address specification is not required. The refresh cycle is 4096 cycles/64 ms. (4096 cycles are required to refresh all the ROW addresses.) The output buffer becomes HighZ after auto-refresh start. In addition, since a precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by the precharge command is not required. Self-refresh: After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A selfrefresh is terminated by a self-refresh exit command. If you use distributed auto-refresh mode with 15.6 s interval in normal read/write cycle, auto-refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. If you use address refresh or burst auto-refresh mode in normal read/write cycle, 4096 cycles of distributed auto-refresh with 15.6 s interval should be executed within 64 ms immediately after exiting from and before entering into self refresh mode. Others Power-down mode: The synchronous DRAM module enters power-down mode when CKE0 goes Low in the IDLE state. In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE0 is held Low. In addition, by setting CKE0 to High, the synchronous DRAM module exits from the power down mode, and command input is enabled from the next cycle. In this mode, internal refresh is not performed. Clock suspend mode: By driving CKE0 to Low during a bank-active or read/write operation, the synchronous DRAM module enters clock suspend mode. During clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE0 is driven High, the synchronous DRAM module terminates clock suspend mode, and command input is enabled from the next cycle. For details, refer to the "CKE0 Truth Table". Power-up sequence: During power-up sequence, the DQMB and the CKE0 must be set to High. When 200 s has past after power on, all banks must be precharged using the precharge command. After tRP delay, set 8 or more auto refresh commands. And set the mode register set command to initialize the mode register.
44
HB526A264DB Series
Timing Waveforms
Read Cycle
t CK t CKH t CKL
" , ,
, , ! " , , " ! !
CK0/CK1 CKE0
t RC VIH t RCD t RAS t RP t CS t CH t CS t CH t CS t CH t CS t CH
, , ,, , , , , , ,
S0
t CS t CH t CS t CH t CS t CH t CS t CH
RAS
t CS t CH
t CS t CH
t CS t CH
t CS t CH
CAS
t CS t CH
t CS t CH
t CS t CH
t CS t CH
WE
t AS t AH t AS t AH
t AS t AH
t AS t AH
t AS t AH t AS t AH
A11
t AS t AH t AS t AH
t AS t AH
A10
t AS t AH
t AS t AH
Address
t CS
t CH
DQMB
Din
t AC
t AC
t AC
Dout
t AC
Bank 0 Active
Bank 0 Read
t LZ
t OH
t OH
t OH
t HZ
Bank 0 Precharge
Burst length = 4 Bank0 Access = VIH or VIL
45
HB526A264DB Series
Write Cycle

, , ! !
" , " !
t CK t CKH t CKL
CK0/CK1 CKE0
t RC
VIH
t RCD
t RAS
t RP
t CS t CH
t CS t CH
t CS t CH
t CS t CH
S0
, ,
RAS
t CS t CH t CS t CH t CS t CH t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
CAS
t CS t CH
t CS t CH
t CS t CH
t CS t CH
WE
t AS t AH t AS t AH
t AS t AH
t AS t AH
t AS t AH t AS t AH
A11
t AS t AH t AS t AH
t AS t AH
A10
t AS t AH
t AS t AH
Address
t CS
t CH
DQMB
t DS t DH tDS
t DH t DS t DH t DS
t DH
Din
t RWL
Dout
Bank 0 Active
Bank 0 Write
Bank 0 Precharge
Burst length = 4 Bank0 Access = VIH or VIL
46
HB526A264DB Series
Mode Register Set Cycle
,
A11(BS) Address DQMB Dout Din
valid code R: b C: b C: b' b b+3 b' b'+1 b'+2 b'+3 High-Z t RP t RSA t RCD
Output mask Precharge If needed Mode Bank 1 register Active Set Bank 1 Read
, , ,, , , , , , , ,, , ,
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
CK0/CK1 CKE0 S0
VIH
RAS
CAS
WE
tRCD = 3 CAS Latency = 3 Burst Length = 4 = VIH or VIL
47
HB526A264DB Series
Read Cycle/Write Cycle
, ,, , , , , , , , , ,
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CK0/CK1 CKE0 S0
VIH

RAS CAS WE A11(BS) DQMB Dout Din Address R:a C:a R:b C:b C:b' C:b" a a+1 a+2 a+3 b b+1 b+2 b+3 b'
Bank 1 Read
Read cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = 4 = VIH or VIL
b'+1 b"
b"+1 b"+2 b"+3
High-Z
Bank 0 Active
Bank 0 Read
Bank 1 Active
Bank 1 Bank 0 Read Precharge
Bank 1 Read
Bank 1 Precharge
CKE0 S0
VIH
RAS CAS
Write cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = 4 = VIH or VIL
WE
A11(BS)
Address DQMB Dout Din
R:a
C:a
R:b
C:b
C:b'
C:b"
High-Z
a
a+1 a+2 a+3
Bank 1 Active
b
b+1 b+2 b+3 b'
Bank 0 Precharge
b'+1 b"
b"+1 b"+2 b"+3
Bank 0 Active
Bank 0 Write
Bank 1 Write
Bank 1 Write
Bank 1 Write
Bank 1 Precharge
48
HB526A264DB Series
Read/Single Write Cycle
,
DQMB Din Dout a b c a a+1 a+3
Bank 0 Active Bank 0 Read Bank 1 Active Bank 0 Write Bank 0 Bank 0 Write Write Bank 0 Precharge
, ,, , , , , , , , , , , ,
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CK0/CK1 CKE0 S0 RAS CAS
VIH
WE
A11(BS) DQMB Din Dout
Address
R:a
C:a
R:b
C:a' C:a a
a
a+1 a+2 a+3
a
a+1 a+2 a+3
Bank 0 Precharge
Bank 0 Active
Bank 0 Read
Bank 1 Active
Bank 0 Bank 0 Write Read
Bank 1 Precharge
CKE0 S0
VIH
RAS CAS
WE
A11(BS)
Address
R:a
C:a
R:b
C:a
C:b C:c
Read/Single write RAS-CAS delay = 3 CAS Latency = 3 Burst Length = 4 = VIH or VIL
49
HB526A264DB Series
Read/Burst Write Cycle
0 CK0/CK1 CKE0 S0 RAS CAS WE A11(BS) Address DQMB Din Dout
Bank 0 Active
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R:a
C:a
R:b
C:a
a a+1 a+2 a+3 a a+1 a+2
Bank 0 Read Bank 1 Active Clock Suspend
a+3
Bank 0 Write Bank 0 Precharge Bank 1 Precharge
CKE0 S0 RAS CAS WE A11(BS) Address DQMB Din Dout
VIH
R:a
C:a
R:b
C:a
a a+1 a+2 a+3 a a+1
Bank 0 Active Bank 0 Read Bank 1 Active
a+3
Bank 0 Write Bank 0 Precharge
Read/Burst write RAS-CAS delay = 3 CAS Latency = 4 Burst Length = 4 = VIH or VIL
50
HB526A264DB Series
Full Page Read/Write Cycle
0

. * " & . 0- , & " ' *
.
0 1 2 3 4 5 6 7 8 9 260 261 262 263 264 265 266 267 268 269 CK0/CK1 CKE0 S0 RAS CAS
VIH
Read cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = full page = VIH or VIL
WE
A11(BS) Address DQMB Dout Din
R:a
C:a
R:b
a
a+1
a+2
a+3
a-2
a-1
a
a+1
a+2
a+3
a+4
a+5
High-Z
Bank 0 Active
Bank 0 Read
Bank 1 Active
Burst stop
Bank 1 Precharge
CKE0 S0
VIH
RAS CAS
Write cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = full page = VIH or VIL
WE
A11(BS) Address Dout Din DQMB
R:a
C:a
R:b
High-Z
a
a+1
a+2
a+3
a+4
a+5
a+6
a+1
a+2
a+3
a+4
a+5
Bank 0 Active
Bank 0 Write
Bank 1 Active
Burst stop
Bank 1 Precharge
51
HB526A264DB Series
Auto Refresh Cycle

Self Refresh Cycle
CK0/CK1 CKE0 S0 ISREX CKE Low CKE High RAS CAS WE A11 (BS) Address DQMB Din Dout tRP
Precharge command If needed Self refresh entry command Self refresh exit ignore command or No operation Next Self refresh entry clock command enable
A10x1
, ,, , , , , ,, , , , , , , ,, , ,
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CK0/CK1 CKE0
VIH
S0
RAS
CAS WE
A11(BS)
Address DQMB Din
A8=1
R:a
C:a
Dout
High-Z
a
a+1
t RP
t RC
tRC
Precharge If needed
Auto Refresh
Auto Refresh
Active Bank 0
Read Bank 0
Refresh cycle and Read cycle RAS-CAS delay=2 CAS latency=2 Burst length=4 = VIH or VIL
High-Z tRC
Next Auto clock refresh enable
Self refresh cycle RAS-CAS delay = 3 CAS Latency = 3 Burst Length = 4 =VIH or VIL
52
HB526A264DB Series
Clock Suspend Mode
, ,,,, , , ,, , , , , , ,,,
t CESP t CEH t CES
,
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CK0/CK1 CKE0 S0 RAS CAS Read cycle RAS-CAS delay=2 CAS latency=2 Burst length=4 = VIH or VIL WE A11(BS) Address DQMB Dout R:a C:a R:b C:b a a+1 a+2 a+3 b b+1 b+2 b+3 Din
High-Z
Bank0 Active clock Active suspend start Active clock Bank0 suspend end Read Bank1 Active Read suspend start
Read suspend end
Bank1 Read
Bank0 Precharge
Earliest Bank1 Precharge
CKE0 S0
RAS CAS
Write cycle RAS-CAS delay=2 CAS latency=2 Burst length=4 = VIH or VIL
WE
A11(BS)
Address DQMB Dout
R:a
C:a R:b
C:b
High-Z
Din
a
a+1 a+2
a+3 b
b+1 b+2 b+3
Bank0 Active
Active clock suspend start
Active clock Bank0 Bank1 supend end Write Active
Write suspend start
Write suspend end
Bank1 Bank0 Write Precharge
Earliest Bank1 Precharge
53
HB526A264DB Series
Power Down Mode
Precharge command If needed Power down entry Power down mode exit Active Bank 0
, , , , ,, , , ,,, ,, , , , , ,
CK0/CK1 CKE0 S0
CKE Low
RAS CAS WE
A11(BS)
Address DQMB
A10=1
R: a
Din
Dout
High-Z
tRP
Power down cycle RAS-CAS delay=3 CAS latency=2 Burst length=4 = VIH or VIL
Power Up Sequence
0
1
2
3
4
5
6
7
8
9
10
48
49
50
51
52
53
54
55
CK0/CK1 CKE0 S0 RAS CAS WE Address DQMB Din/out
VIH
Valld
code
Valld
VIH High-Z tRP All banks Auto Refresh Precharge tRC Auto Refresh tRC tRSA Mode register Bank active Set If needed
54
HB526A264DB Series
Physical Outline
Unit: mm / inch
67.60 2.661 24.50 0.965
,,,,,,,,,,,,,,,,,,,,,,,,, 2R0.118Min. ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,, (front) ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,
23.20 0.913 2.50 0.098 B 4.60 0.181 32.80 1.291 A
143 1
63.60 2.504 (Datum -A-)
3.80Max. 0.150Max. 2R3.00Min
,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, ,
3.20Min. 0.126Min.
20.00 0.787
3.30 0.130
2- o1.80 2- o0.071 2-R2.00 2-R0.079
,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,, (back) ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,
(Datum -A-)
144 2
2.00Min. 0.079Min.
Detail A
Detail B
(DATUM -A-) 0.60 0.05 0.024 0.002 2.5 0.098 R0.75 R0.030
0.25 Max. 0.010 Max.
0.80 0.031
4.00 0.10 0.157 0.004
2.55 Min. 0.100 Min.
4.00 0.10 0.157 0.004
3.70 0.146
2.10 0.083 23.20 0.913
4.60 0.181 32.80 1.291
1.50 0.10 0.059 0.004
4.00Min. 0.157Min.
1.00 0.10 0.039 0.004
25.40 1.000 6.00 0.236
55
HB526A264DB Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
56
HB526A264DB Series
Revision Record
Rev. Date 0.0 0.1 Contents of Modification Drawn by T. Sugano Approved by K. Tsuneda Jun. 18, 1996 Initial issue May. 20, 1997 (referred to HM5216805/HM5216405 rev.3.0) Correct errors Addition of HB526A264DB-10L Deletion of HB526A264DB-15 Change of Serial PD Matrix Absolute Maximum Ratings Topr: 0 to 65 C to 0 to 70C Change of note1 DC Characteristics Addition of ICC6 (L-version) max: 2/2 mA AC Characteristics tAC (CL = 2) max: 9.5/12 ns to 9/12 ns tAC (CL = 3) max: 8/9.5 ns to 7.5/9 ns tHZ min: 2/2 ns to --/-- ns Change of symbol: t RWL to tDPL Change of description for Self-refresh
57

▲Up To Search▲

Price & Availability of 526A264D

	To Download 526A264D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .