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HB56H164EJ Series
1,048,576-word x 64-bit High Density Dynamic RAM Module
ADE-203-697A(Z) Rev. 1.0 Dec. 27, 1996 Description
The HB56H164EJ belongs to 8 Byte DIMM (Dual In-line Memory Module) family, and has been developed as an optimized main memory solution for 4 and 8 Byte processor applications. The HB56H164EJ is a 1M x 64 dynamic RAM module, mounted 4 pieces of 16-Mbit DRAM (HM5118165) sealed in SOJ package and 2 pieces of 16-bit BiCMOS line driver (74ABT16244) sealed in TSSOP package. The HB56H164EJ offers Extended Data Out (EDO) Page Mode as a high speed access mode. An outline of the HB56H164EJ is 168-pin socket type package (dual lead out). Therefore, the HB56H164EJ makes high density mounting possible without surface mount technology. The HB56H164EJ provides common data inputs and outputs. Decoupling capacitors are mounted on the module board.
Features
* 168-pin socket type package (Dual lead out) Outline: 133.35 mm (Length) x 25.40 mm (Height) x 9.00 mm (Thickness) Lead pitch: 1.27 mm * Single 5 V (5%) supply * High speed Access time: tRAC = 60/70 ns (max) tCAC = 20/23 ns (max) * Low power dissipation Active mode: 3.906/3.486 W (max) Standby mode (TTL): 378 mW (max) (CMOS): 357 mW (max) * Buffered input except RAS and DQ * 4 byte interleave enabled, dual address input (A0/B0) * JEDEC standard outline buffered 8-byte DIMM * EDO page mode capability * 1,024 refresh cycles: 16 ms * 2 variations of refresh RAS-only refresh CAS-before-RAS refresh * TTL compatible
HB56H164EJ Series
Ordering Information
Type No. HB56H164EJ-6 HB56H164EJ-7 Access time 60 ns 70 ns Package 168-pin dual lead out socket type Contact pad Gold
Pin Arrangement
Front side Back side
1 pin 10 pin 11 pin 85 pin 94 pin 95 pin
40 pin 41 pin 124 pin 125 pin
84 pin 168 pin
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HB56H164EJ Series
Pin Arrangement
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pin name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 DQ16 NC VSS NC NC VCC WE0 CE0 CE2 RE0 OE0 VSS A0 A2 Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 Pin name VSS OE2 RE2 CE4 CE6 WE2 VCC NC NC DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC DQ24 NC NC NC NC DQ25 NC DQ27 VSS DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 Pin name VSS DQ36 DQ37 DQ38 DQ39 VCC DQ40 DQ41 DQ42 DQ43 NC VSS DQ45 DQ46 DQ47 DQ48 DQ49 VCC DQ50 DQ51 DQ52 NC VSS NC NC VCC NC CE1 CE3 NC NC VSS A1 A3 Pin No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Pin name VSS NC NC CE5 CE7 PDE VCC NC NC DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 NC NC NC NC DQ61 NC DQ63 VSS DQ64 DQ65 DQ66 DQ67 VCC DQ68 DQ69 DQ70
3
HB56H164EJ Series
Pin No. 35 36 37 38 39 40 41 42 Pin name A4 A6 A8 NC NC VCC NC NC Pin No. 77 78 79 80 81 82 83 84 Pin name NC VSS PD1 PD3 PD5 PD7 ID0 (VSS) VCC Pin No. 119 120 121 122 123 124 125 126 Pin name A5 A7 A9 NC NC VCC NC B0 Pin No. 161 162 163 164 165 166 167 168 Pin name NC VSS PD2 PD4 PD6 PD8 ID1 (VSS) VCC
Pin Description
Pin name A0 to A9, B0 Function Address input Row address Column address Refresh address DQ0 to DQ7, DQ9 to DQ16, DQ18 to DQ25, DQ27 to DQ34, DQ36 to DQ43, DQ45 to DQ52, DQ54 to DQ61, DQ63 to DQ70 RE0, RE2 CE0 to CE7 WE0, WE2 OE0, OE2 VCC VSS PD1 to PD8 ID0, ID1 PDE NC Data-in/data-out : A0 to A9, B0 : A0 to A9, B0 : A0 to A9, B0
Row address strobe (RAS) Column address strobe (CAS) Read/Write enable Output enable Power supply Ground Presence detect ID bit Presence detect enable No connection
4
HB56H164EJ Series
Presence Detect Pin Assignment
PDE = Low Pin name PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 Note: Pin No. 79 163 80 164 81 165 82 166 1: High level (Driver output) 0: Low level (Driver output) 60 ns 0 0 1 0 1 1 1 1 70 ns 0 0 1 0 1 0 1 1 PDE = High All High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z
5
HB56H164EJ Series
Block Diagram
RE0 WE0 OE0 RAS CE0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CE1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LCAS I/O I/O I/O I/O I/O I/O I/O I/O UCAS I/O I/O I/O I/O I/O I/O I/O I/O WE OE CE4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 CE5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 RE2 WE2 OE2 RAS LCAS I/O I/O I/O I/O I/O I/O I/O I/O UCAS I/O I/O I/O I/O I/O I/O I/O I/O WE OE
D0
D2
RAS CE2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CE3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 LCAS I/O I/O I/O I/O I/O I/O I/O I/O UCAS I/O I/O I/O I/O I/O I/O I/O I/O
WE
OE CE6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 CE7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
RAS LCAS I/O I/O I/O I/O I/O I/O I/O I/O UCAS I/O I/O I/O I/O I/O I/O I/O
WE
OE
D1
D3
PD1 to PD8
A0 B0 A1 to A9 VCC VSS 0.22F x 7pcs A0(D0 to D1) A0(D2 to D3) A1 to A9(D0 to D3) VCC(D0 to D3, 74ABT16244) VSS(D0 to D3, 74ABT16244) * D0 to D3 : HM5118165 : 74ABT16244
VSS VSS VCC VSS VCC VCC VSS VCC VSS VCC
PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8
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HB56H164EJ Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout Pt Topr Tstg Value -0.5 to +7.0 -0.5 to +7.0 50 5 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to 70C)
Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage Note: VIH VIL Min 0 4.75 2.4 -0.5 Typ 0 5.0 -- -- Max 0 5.25 5.5 0.8 Unit V V V V 1 1 1 Note
1. All voltage referenced to VSS.
7
HB56H164EJ Series
DC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V)
60 ns Parameter Operating current Standby current Symbol Min ICC1 ICC2 -- -- 70 ns Max Min 744 72 -- -- Max Unit Test conditions 664 72 mA mA tRC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z tRC = min RAS = VIH, CAS = VIL Dout = enable tRC = min tHPC = min 0 V Vin 5.5 V 0 V Vout 5.5 V Dout = disable High Iout = -2 mA Low Iout = 2 mA 1, 3 2 1 Notes 1, 2
--
68
--
68
mA
RAS-only refresh current Standby current CAS-before-RAS refresh current EDO page mode current Input leakage current Output leakage current Output high voltage Output low voltage
ICC3 ICC5 ICC6 ICC7 ILI ILO VOH VOL
-- -- -- -- -10 -10 2.4 0
744 84 744 804 10 10 VCC 0.4
-- -- -- -- -10 -10 2.4 0
664 84 664 724 10 10 VCC 0.4
mA mA mA mA A A V V
Notes: 1. ICC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH.
Capacitance (Ta = 25C, VCC = 5 V 5%)
Parameter Input capacitance (Address) Input capacitance (CAS, WE, OE) Input capacitance (RAS) I/O capacitance (DQ) Symbol CI1 CI2 CI3 CI/O Typ -- -- -- -- Max 20 20 29 20 Unit pF pF pF pF Notes 1 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
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HB56H164EJ Series
AC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V)*1, *2, *18, *19
Test Conditions * * * * * Input rise and fall times: 2 ns Input levels: 0 V, 3.0 V Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
60 ns Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Refresh period (1,024 cycles) Symbol tRC tRP tCP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tOED tDZO tDZC tT tREF Min 104 40 10 60 10 5 10 0 10 20 15 20 40 10 20 0 0 2 -- Max -- -- -- 70 ns Min 124 50 13 Max -- -- -- Unit ns ns ns Notes
10000 70 10000 13 -- -- -- -- 40 25 -- -- -- -- -- -- 50 16 5 10 0 13 20 15 23 45 10 23 0 0 2 --
10000 ns 10000 ns -- -- -- -- 47 30 -- -- -- -- -- -- 50 16 ns ns ns ns ns ns ns ns ns ns ns ns ns ms 5 6 6 7 3 4
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HB56H164EJ Series
Read Cycle
60 ns Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time from RAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Output data hold time from RAS Output buffer turn-off time to RAS Output buffer turn-off to WE WE to Din delay time RAS to Din delay time RAS next CAS delay time Symbol tRAC tCAC tAA tOEA tRCS tRCH tRCHR tRRH tRAL tCAL tCLZ tOH tOHO tOFF tOEZ tCDD tOHR tOFR tWEZ tWED tRDD tRNCD Min -- -- -- -- 0 0 60 5 35 18 2 3 3 -- -- 20 3 -- -- 20 15 60 Max 60 20 35 20 -- -- -- -- -- -- -- -- -- 20 20 -- -- 15 20 -- -- -- 70 ns Min -- -- -- -- 0 0 70 5 40 23 2 3 3 -- -- 23 3 -- -- 23 18 70 Max 70 23 40 23 -- -- -- -- -- -- -- -- -- 20 20 -- -- 15 20 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13, 22 13 5 22 22 22 12 12 Notes 8, 9 9, 10, 17 9, 11, 17 9, 21
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HB56H164EJ Series
Write Cycle
60 ns Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol tWCS tWCH tWP tRWL tCWL tDS tDH Min 0 10 10 15 10 0 15 Max -- -- -- -- -- -- -- 70 ns Min 0 13 10 18 13 0 18 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 15 15 Notes 14
Read-Modify-Write Cycle
60 ns Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol tRWC tRWD tCWD tAWD tOEH Min 136 79 34 49 15 Max -- -- -- -- -- 70 ns Min 161 92 40 57 18 Max -- -- -- -- -- Unit ns ns ns ns ns 14 14 14 Notes
Refresh Cycle
60 ns Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) RAS precharge to CAS hold time Symbol tCSR tCHR tRPC Min 10 10 0 Max -- -- -- 70 ns Min 10 10 0 Max -- -- -- Unit ns ns ns Notes
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HB56H164EJ Series
EDO Page Mode Cycle
60 ns Parameter EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Output data hold time from CAS low CAS hold time refferd OE CAS to OE setup time Read command hold time from CAS precharge Symbol tHPC tRASP tCPA tCPRH tDOH tCOL tCOP tRCHC Min 25 -- -- 40 3 10 5 35 Max -- 70 ns Min 30 Max -- Unit ns Notes 20 16 9, 17
100000 -- 40 -- -- -- -- -- -- 45 3 13 5 40
100000 ns 45 -- -- -- -- -- ns ns ns ns ns ns
9, 17
EDO Page Mode Read-Modify-Write Cycle
60 ns Parameter EDO page mode read-modify-write cycle time WE delay time from CAS precharge Symbol tHPRWC tCPW Min 68 54 Max -- -- 70 ns Min 79 62 Max -- -- Unit ns ns 14 Notes
Notes: 1. AC measurements assume tT = 2 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh cycle or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if tRCD tRAD (max) + tAA (max)- tCAC (max), then access time is controlled exclusively by tCAC. 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either tOED or tCDD must be satisfied. 6. Either tDZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH (min) and VIL (max). 8. Assumes that tRCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that tRCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that tRAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 12. Either tRCH or tRRH must be satisfied for a read cycles. 13. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.
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HB56H164EJ Series
14. tWCS , tRWD, tCWD, tAWD, and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics onry; if tWCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min) or tCWD tCWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. tRASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among tAA , tCAC and tCPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tOEH tCWL, the DQ pin will remain open circuit (high impedance); tOEH < tOEH, invalid data will be out at each DQ. 19. All the VCC and VSS pins shall be supplied with the same voltages. 20. tHPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2tT) becomes greater than the specified tHPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 21. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC / VSS line noise, which causes to degrade VIH min./ VIL max level. 22. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between tOHR and tOH, and between tOFR and tOFF. 23. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL.
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HB56H164EJ Series
Notes concerning 2CAS control
Please do not separate the 2CASs (CAS0 and CAS1 (or CAS2, CAS4, CAS6 and CAS3, CAS5, CAS7)) operation timing intentionally. However skew between 2CASs are allowed under the following conditions. 1. Each of the 2CASs should satisfy the timing specifications individually. 2. Different operation mode for upper/lower byte is not allowed: such as following.
RAS CAS0 (CAS2, CAS4, CAS6) CAS1 (CAS3, CAS5, CAS7) Early write Delayed write
WE
3. Closely separated upper/lower byte control is not allowed. However when the condition (tCP tUL) is satisfied, page mode can be performed.
RAS
CAS0 (CAS2, CAS4, CAS6) CAS1 (CAS3, CAS5, CAS7) t UL
4. Byte control operation by remaining CAS0 (CAS2, CAS4, CAS6) or CAS1 (CAS3, CAS5, CAS7) high is guaranteed.
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HB56H164EJ Series
Timing Waveforms*23
Read Cycle
t RC t RAS t RP
RAS t CSH t RCD tT t RSH t CAS t CRP
CAS
t RAD t ASR t ASC t RAL t CAL t CAH
t RAH
Address
Row
Column t RRH t RCHR t RCS t RCH
WE t WED t DZC t CDD t RDD Din High-Z
t DZO
t OEA
t OED
OE t OEZ t OHO t OFF t OH t OFR t OHR t WEZ Dout Dout
t CAC t AA t RAC t CLZ
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HB56H164EJ Series
Early Write Cycle
t RC t RAS t RP
RAS t CSH t RCD tT CAS t RSH t CAS t CRP
t ASR
t RAH
t ASC
t CAH
Address
Row
Column
t WCS
t WCH
WE
t DS
t DH
Din
Din
Dout
High-Z* * t WCS t WCS (min)
16
HB56H164EJ Series
Delayed Write Cycle*18
t RC t RAS
t RP
RAS t CSH t RCD tT CAS t ASR t RAH t ASC t CAH t RSH t CAS t CRP
Address
Row
Column t CWL t RCS t RWL t WP
WE
t DZC
t DS
t DH
Din
High-Z
Din t OEH t OED
t DZO

OE t OEZ t CLZ Dout High-Z Invalid Dout 17
HB56H164EJ Series
Read-Modify-Write Cycle*18
t RWC t RAS
t RP
RAS tT t RCD t CAS t CRP
CAS t RAD t ASR t RAH t ASC t CAH
Address
Row t RCS
Column t CWD t AWD t RWD tCWL t RWL t WP
WE t DZC t DS Din
High-Z Din
t DH
t DZO
t OED t OEA
t OEH
OE t CAC t AA t RAC t OEZ t OHO
High-Z
Dout t CLZ
Dout
18
HB56H164EJ Series
RAS-Only Refresh Cycle
t RC t RAS RAS tT t CRP t RPC t CRP t RP
CAS
t ASR Address t OFR t OFF Dout Row
t RAH
High-Z
19
HB56H164EJ Series
CAS-Before-RAS Refresh Cycle
t RC t RP t RAS t RP t RAS t RC t RP
RAS tT t RPC t CP t CSR t CHR t RPC t CP t CRP t CSR t CHR

Address t OFR t OFF Dout High-Z 20
CAS
HB56H164EJ Series
EDO Page Mode Read Cycle
t RP t RASP tT CAS t RCS
WE
t RNCD
RAS
t HPC t HPC tCAS t RCHC t CPRH t CP t t CRP
t CSH t CAS t RCHR
t CP
t HPC t CAS
t CP
RSH
tCAS t RRH t RCH
t RCH t RCS
tASR
Address
tRAH tASC Row
tCAH
t ASC t CAH Column 2 t CAL
t ASC t CAH Column 3 t CAL
tASC
t RAL t CAH
Column 4
t WED
Column 1 t CAL tDZC
t CAL tRDD tCDD
Din
High-Z tDZO tCOL tCOP tOED

OE
tOEA
tCPA
tCPA
tCAC tAA
tAA tCAC
tOEZ
tWEZ
tOHO
tCPA tAA tCAC
tAA
tOEZ
tOFR tOHR tOEZ
tCAC
tRAC
tOEA
tDOH
tOHO
tOEA
tOHO tOFF tOH
Dout
Dout 1
Dout 2
Dout 2
Dout 3
Dout 4
21
HB56H164EJ Series
EDO Page Mode Early Write Cycle
t RASP t RP
RAS tT t CSH t RCD t CAS t CP t HPC t CAS t CP t RSH t CAS t CRP
CAS
t ASR t RAH
t ASC
t CAH
t ASC
tCAH
t ASC t CAH
Address
Row
Column 1
Column 2
Column N
t WCS
t WCH
t WCS
t WCH
t WCS
t WCH
WE
t DS
t DH
t DS
t DH
t DS
t DH
Din
Din 1
Din 2
Din N
Dout
High-Z*
* t WCS
t WCS (min)
22
HB56H164EJ Series
EDO Page Mode Delayed Write Cycle*18
t RASP t RP RAS tT t CSH t RCD t CAS t CP t HPC t CAS t CP t RSH t CAS t CRP
CAS
t RAD t ASR t RAH Address Row t ASC t CAH Column 1 t CWL t RCS WE t WP t DZC t DS t DH Din t DZO t OED Din 1 t DZO t OED t WP t DZC t DS t DH Din 2 t DZO t OED t WP t DZC t DS t DH Din N t RCS t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL

t OEH t OEH t OEH OE t CLZ t CLZ t CLZ t OEZ t OEZ t OEZ Dout High-Z
Invalid Dout Invalid Dout Invalid Dout
23
HB56H164EJ Series
EDO Page Mode Read-Modify-Write Cycle*18
t RASP t RP RAS tT t CP t RCD t CAS t CAS t HPRWC t CP t RSH t CAS
t CRP
CAS
t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD WE t RCS t WP t DZC t DS t DH Din t DZO
t OED
t ASC t CAH Column 2 t CWL t RCS t CPW t AWD t CWD t RCS t CWL
t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL
Address
t WP t DZC t DS t DH Din 2 t OED t OEH t DZO t OED
t WP t DZC t DS t DH Din N
Din 1 t DZO t OEH
t OEH
*
OE t OHO t OHO t OHO t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ
High-Z
Dout
Dout 1
Dout 2
Dout N
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HB56H164EJ Series
EDO Page Mode Mix Cycle (1)
t RP RAS tT CAS t RCD t WCS WE t ASC tRAH Row t WCH t RCS tCPW tAWD tCAH t ASC t CAH Column 2 t CAL t DS
Din
t RASP t CRP tCAS tRSH t RCS tWP t RAL t CAH Column 4 t CAL t DS High-Z tOED t DH Din 3 tWED tRDD tCDD t RRH t RCH
t CP t CAS t CSH t CAS
t CP tCAS
t CP
tASR Address
tASC t CAH Column 3
tASC
Column 1
t DH Din 1

tCPA tAA tOEA tCPA tCPA tAA t OEZ tAA tOFR tWEZ tOEZ tCAC tOHO tOFF tOH tCAC t DOH tCAC t OHO tOEA Dout Dout 2
Dout 3
OE
Dout 4
25
HB56H164EJ Series
EDO Page Mode Mix Cycle (2)
t RP t RASP
t RNCD
RAS
tT CAS
t CSH t CAS t RCD t RCS t RCHR
t CP t CAS
t CP tCAS
t CP tCAS t RCS tCPW tWP t RAL tASC t CAH Column 4 t CAL t DS t DH Din 3 tOED tCOP tRSH
t CRP
t RCH tWCS t WCH
t RCS
t RRH t RCH
WE
tASR
Address
tRAH Row
t ASC
tCAH
t ASC t CAH Column 2
t ASC t CAH Column 3 t CAL
Column 1 t CAL
t DS
Din
t DH Din 2
tRDD tCDD
High-Z
tOED
OE
tWED
tCOL t OEA tOEZ t OHO tCPA tAA tCAC tOEZ t OHO
Dout 3
tAA tOEA tCAC tRAC
tCPA tAA tCAC tOEA
tOFR tWEZ tOEZ tOHO tOFF tOH Dout 4
Dout
Dout 1
26
HB56H164EJ Series
Physical Outline
Unit: mm/inch
Front side 133.35 5.250 3.00 0.118 127.35 5.014 9.00 max 0.354 max
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Front) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 1 84 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
C B 36.83 1.450 54.61 2.150 A 11.43 0.450
,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, ,
3.00 0.118
8.89 0.350
1.27 0.10 0.050 0.004
Back side 2 - 3.00 2 - 0.118
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Back) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
168 85
4.00 0.157
17.78 0.700
Detail A 2.54 min 0.100 min 1.27 0.050 0.25 max 0.010 max
Detail B 1.00 0.039
Detail C 3.175 0.125 6.35 0.250 2.00 0.10 0.079 0.004
1.00 0.05 0.039 0.002
3.125 0.125 0.123 0.005
3.125 0.125 0.123 0.005
6.35 0.250 3.175 0.125 2.00 0.10 0.079 0.004
25.40 1.000
4.00 min 0.157 min
27
HB56H164EJ Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
28
HB56H164EJ Series
Revision Record
Rev. Date 1.0 Dec. 27, 1996 Contents of Modification Initial issue Drawn by Approved by
29

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