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HB56H164EJN-6B/7B
1,048,576-word x 64-bit High Density Dynamic RAM Module 168-pin JEDEC Standard Outline Unbufferd 8 byte DIMM
ADE-203-552A(Z) Rev. 1.0 Feb. 21, 1996
Description
The HB56H164EJN belongs to 8 Byte DIMM (Dual In-line Memory Module) family, and has been developed as an optimized main memory solution for 4 and 8 Byte processor applications. The HB56H164EJN is a 1M x 64 dynamic RAM module, mounted 4 pieces of 16-Mbit DRAM (HM5118165BJ) sealed in SOJ package and 1 pieces of serial EEPROM (24C02) for Presence Detect (PD). The HB56H164EJN offers Extended Data Out (EDO) Page Mode as a high speed access mode. An outline of the HB56H164EJN is 168-pin socket type package (dual lead out). Therefore, the HB56H164EJN makes high density mounting possible without surface mount technology. The HB56H164EJN provides common data inputs and outputs. Decoupling capacitors are mounted beneath each SOJ on the module board.
Features
* * * * * 168-pin socket type package (Dual lead out) Lead pitch: 1.27 mm Single 5 V (5%) supply High speed Access time: tRAC = 60/70 ns (max) Access time: tCAC = 15/18 ns (max) Low power dissipation Active mode: 3.6/3.2 W (max) Standby mode (TTL): 42 mW (max) Standby mode (CMOS): 21 mW (max) EDO page mode capability 1,024 refresh cycles: 16 ms 3 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh TTL compatible
* * *
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HB56H164EJN-6B/7B
Ordering Information
Type No. HB56H164EJN-6B HB56H164EJN-7B Access time 60 ns 70 ns Package 168-pin dual lead out socket type Contact pad Gold
Pin Arrangement
Front side Back side
1 pin 10 pin 11 pin 85 pin 94 pin 95 pin
40 pin 41 pin 124 pin 125 pin
84 pin 168 pin
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12
Pin Name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS
Pin No. 13 14 15 16 17 18 19 20 21 22 23 24
Pin Name DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 NC NC VSS NC
Pin No. 25 26 27 28 29 30 31 32 33 34 35 36
Pin Name NC VCC WE0 CAS0 CAS1 RAS0 OE0 VSS A0 A2 A4 A6
Pin No. 37 38 39 40 41 42 43 44 45 46 47 48
Pin Name A8 NC NC VCC VCC NC VSS OE2 RAS2 CAS2 CAS3 WE2
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HB56H164EJN-6B/7B
Pin Arrangement (cont)
Pin No. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Pin Name VCC NC NC NC NC VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS Pin No. 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Pin Name NC NC NC SDA SCL VCC VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 NC NC VSS NC Pin No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Pin Name NC VCC NC CAS4 CAS5 NC NC VSS A1 A3 A5 A7 A9 NC NC VCC NC NC VSS NC NC CAS6 CAS7 NC VCC NC NC NC NC VSS Pin No. 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Pin Name DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS NC NC SA0 SA1 SA2 VCC
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HB56H164EJN-6B/7B
Pin Description
Pin Name A0 to A9 Function Address Input Row Address Column Address Refresh Address Data-in/Data-out Row Address Strobe Column Address Strobe Read/Write Enable Output Enable Serial Data for PD Serial Clock for PD Serial Address for PD Power Supply Ground Non Connection : : : : A0 to A9 A0 to A9 A0 to A9 A0 to A9
DQ0 to DQ63 RAS0, RAS2 CAS0 to CAS7 WE0, WE2 OE0, OE2 SDA SCL SA0 to SA2 VCC VSS NC
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HB56H164EJN-6B/7B
Serial PD Matrix
Byte Number 0 1 2 3 4 5 6 7 8 9 Function Described Number Serial PD Bytes Serial Memorry Fundamental Memory Type Number of Rows Number of Columns Number of Banks Data Width Data Width (continued) Voltage Interface RAS Access Time 60 ns RAS Access Time 70 ns 10 CAS Access Time 15 ns CAS Access Time 18 ns 11 12 Error Detection/Corraction Refresh Period Bit7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit6 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 Bit5 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Bit4 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 Bit3 1 1 0 1 1 0 0 0 0 1 0 1 0 0 0 Bit2 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 Bit1 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 Bit0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 NoneParity Normal (15.625s) Note 13 256 Bytes EDO 10 10 1 64 0 (+) 5.0 Volt
Note: Serial-PD Datas are not protected. 1: High Level (Serial Data) 0: Low Level (Serial Data)
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HB56H164EJN-6B/7B
Block Diagram
RAS0 CAS0 CAS1 WE0 OE0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LCAS UCAS RAS WE I/O I/O I/O I/O I/O I/O I/O I/O D0 I/O I/O I/O I/O I/O I/O I/O I/O OE DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 RAS2 CAS4 CAS5 WE2 OE2 LCAS UCAS RAS WE I/O I/O I/O I/O I/O I/O I/O I/O D2 I/O I/O I/O I/O I/O I/O I/O I/O OE
CAS2 CAS3 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 LCAS UCAS RAS WE I/O I/O I/O I/O I/O I/O I/O I/O D1 I/O I/O I/O I/O I/O I/O I/O I/O OE
CAS6 CAS7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 LCAS UCAS RAS WE I/O I/O I/O I/O I/O I/O I/O I/O D3 I/O I/O I/O I/O I/O I/O I/O I/O OE
Serial PD A0 to A9 VCC VSS 0.22 F x 8 pcs D0 to D3 D0 to D3, U0 D0 to D3, U0 SCL A0 SA0 * D0 to D3 U0 : HM5118165 : 24C02 U0 A1 SA1 A2 SA2 SDA
Note 1. The SDA pull-up resistor is required due to the open-drain/open-collecter output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inactive "High" state.
Absolute Maximum Ratings
Parameter Symbol Value Unit
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HB56H164EJN-6B/7B
Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature VT VCC Iout Pt Topr Tstg -1.0 to +7.0 -1.0 to +7.0 50 4 0 to +70 -55 to +125 V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to 70C)
Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage Note: 1. All voltage referenced to V SS . VIH VIL Min 0 4.75 2.4 -1.0 Typ 0 5.0 -- -- Max 0 5.25 5.5 0.8 Unit V V V V 1 1 1 Note
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HB56H164EJN-6B/7B
DC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V)
60 ns Parameter Operating current Standby current Symbol Min I CC1 I CC2 -- -- 70 ns Max Min 680 8 -- -- Max Unit Test condition 600 8 mA mA t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min t HPC = min 0 V Vin 5.5 V 0 V Vout 5.5 V Dout = disable High Iout = -2 mA Low Iout = 2 mA 1, 3 2 1 Note 1, 2
--
4
--
4
mA
RAS-only refresh current Standby current CAS-before-RAS refresh current EDO page mode current Input leakage current Output leakage current Output high voltage Output low voltage
ICC3 I CC5 ICC6 I CC7 I LI I LO VOH VOL
-- -- -- -- -10 -10 2.4 0
680 20 680 740 10 10 VCC 0.4
-- -- -- -- -10 -10 2.4 0
600 20 600 660 10 10 VCC 0.4
mA mA mA mA A A V V
Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH.
Capacitance (Ta = 25C, VCC = 5 V 5%)
Parameter Input capacitance (Address) Input capacitance (RAS, WE, OE) Input capacitance (CAS) I/O capacitance (DQ) Symbol CI1 CI2 CI3 CI/O Typ -- -- -- -- Max 40 34 27 20 Unit pF pF pF pF Notes 1 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout.
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HB56H164EJN-6B/7B
AC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V)*1, *2, *18, *19
Test Conditions * * * * * Input rise and fall times: 2 ns Input levels: 0 V, 3.0 V Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
60 ns Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Refresh period (1,024 cycles) Symbol t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t OED t DZO t DZC tT t REF Min 104 40 10 60 10 0 10 0 10 20 15 15 48 5 15 0 0 2 -- Max -- -- -- 10000 10000 -- -- -- -- 45 30 -- -- -- -- -- -- 50 16 70 ns Min 124 50 13 70 13 0 10 0 13 20 15 18 58 5 18 0 0 2 -- Max -- -- -- 10000 10000 -- -- -- -- 52 35 -- -- -- -- -- -- 50 16 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 5 6 6 7 3 4 Notes
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HB56H164EJN-6B/7B
Read Cycle
60 ns Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time from RAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Output data hold time from RAS Output buffer turn-off time to RAS Output buffer turn-off to WE WE to Din delay time RAS to Din delay time Symbol t RAC t CAC t AA t OEA t RCS t RCH t RCHR t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD t OHR t OFR t WEZ t WED t RDD Min -- -- -- -- 0 0 60 5 30 18 0 3 3 -- -- 15 3 -- -- 15 15 Max 60 15 30 15 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- 70 ns Min -- -- -- -- 0 0 70 5 35 23 0 3 3 -- -- 18 3 -- -- 18 18 Max 70 18 35 18 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 13 5 12 12 Notes 8, 9 9, 10, 17 9, 11, 17 9, 21
Write Cycle
60 ns Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol t WCS t WCH t WP t RWL t CWL t DS t DH Min 0 10 10 10 10 0 10 Max -- -- -- -- -- -- -- 70 ns Min 0 13 10 13 13 0 13 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 15 15 Notes 14
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HB56H164EJN-6B/7B
Read-Modify-Write Cycle
60 ns Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol t RWC t RWD t CWD t AWD t OEH Min 136 79 34 49 15 Max -- -- -- -- -- 70 ns Min 161 92 40 57 18 Max -- -- -- -- -- Unit ns ns ns ns ns 14 14 14 Notes
Refresh Cycle
60 ns Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) RAS precharge to CAS hold time Symbol t CSR t CHR t RPC Min 5 10 0 Max -- -- -- 70 ns Min 5 10 0 Max -- -- -- Unit ns ns ns Notes
EDO Page Mode Cycle
60 ns Parameter EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Output data hold time from CAS low CAS hold time refferd OE CAS to OE setup time Reas command hold time from CAS precharge Symbol t HPC t RASP t CPA t CPRH t DOH t COL t COP t RCHC Min 25 -- -- 35 3 10 5 35 Max -- 70 ns Min 30 Max -- Unit ns Notes 20 16 9, 17
100000 -- 35 -- -- -- -- -- -- 40 3 13 5 40
100000 ns 40 -- -- -- -- -- ns ns ns ns ns ns
9, 17
EDO Page Mode Read-Modify-Write Cycle
60 ns Parameter WE delay time from CAS precharge Symbol Min 68 54 Max -- -- 70 ns Min 79 62 Max -- -- Unit ns ns 14 Notes
EDO page mode read-modify-write cycle time t HPRWC t CPW
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HB56H164EJN-6B/7B
Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh cycle or CASbefore-RAS refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if tRCD tRAD (max) + tAA (max) - tCAC (max), then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD < tRCD (max) and tRAD < tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1TTL loads and 100 pF. 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) is define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t CPW and t AWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to CAS leading edge in early write cycle and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC or tCPA. 18. In delayed write or read-modify-write cycle, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tOEH tCWL, the DQ pin will remain open circuit (high impedance); if t OEH tCWL, invalid data will be out at each DQ. 19. All the V CC and VSS pins shall be supplied with the same voltages. 20. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2tT) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 21. When output buffers are enabeled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally causes large V CC / V SS line noise, which causes to degrade V IH min / V IL max level.
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HB56H164EJN-6B/7B
Notes concerning 2CAS control
(1) In one memory cycle, active both of 2CASs (CAS0 and CAS1 (or CAS2, 4, 6 and CAS3, 5, 7)) or only one of them or neither of them. (2) To activate both of 2CASs in an early write cycle or a page mode early write cycle, please keep tSKW (skew between CAS0 and CAS1 (or CAS2, 4, 6 and CAS3, 5, 7)) 5 ns or less.
RAS
CAS0 (CAS2) (CAS4) (CAS6) CAS1 (CAS3) (CAS5) (CAS7) tSKW < 5ns = WE
(3) If the different CASs are activated in the consecutive page cycles, tUL the period that both CASs are high, should be keep tCP spec (tCP min tUL).
Example RAS
CAS0 (CAS2) (CAS4) (CAS6) CAS1 (CAS3) (CAS5) (CAS7)
1st cycle
tUL
2st cycle
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HB56H164EJN-6B/7B
Timing Waveforms
Read Cycle
tRC tRAS RAS tCSH tRCD tT CAS tRAD tASR Address tRAH tASC tRAL tCAL tCAH tRSH tCAS tCRP tRP
Row
Column tRCHR tRCS tRCH tRRH
WE tWED tDZC High-Z tCDD tRDD
Din tDZO
tOEA
tOED
OE tOEZ tOHO tOFF tOH tOH tOH tWEZ Dout Dout
tCAC tAA tRAC tCLZ
Note :
H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) Invalid Dout
Early Write Cycle
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HB56H164EJN-6B/7B
tRC tRAS RAS tRP
tCSH tRCD tT CAS tCAS tRSH
tCRP
tASR
tRAH
tASC
tCAH
Address
Row
Column tWP tWCS tWCH
WE
tDS
tDH
Din
Din
Dout
High-Z * OE : H or L WCS
WCS(min)
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HB56H164EJN-6B/7B
Delayd Write Cycle
tRC tRAS RAS tCSH tRCD tT CAS tASR tRAH tASC tCAH tRSH tCAS tCRP tRP
Address
Row
Column tCWL tRCS tRWL tWP
WE tDZC High-Z Din tCLZ tDZO tOED tOEH High-Z
Invalid Dout
tDH tDS Din
Dout tOEZ
OE > * tOEH = tCWL
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HB56H164EJN-6B/7B
Read-Modify-Write Cycle
tRWC tRAS RAS tRCD tT CAS tRAD tASR tRAH tASC tCAH tRSH tCRP
tRP
Address
Row tRCS
Column tCWD tAWD tRWD tCWL tRWL tWP
WE tDZC High-Z Din tCAC tAA tRAC tCLZ Dout tOEA tDZO tOED tOEZ tOHO tOEH Dout High-Z tDH tDS Din
OE > * tOEH = tCWL
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HB56H164EJN-6B/7B
RAS-Only Refresh Cycle
tRC tRAS RAS tRP
tT tCRP tRPC tCRP
CAS
tASR
tRAH
Address tOFR tOFF Dout
Row
High-Z
* WE, OE : H or L
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HB56H164EJN-6B/7B
CAS-Before-RAS Refresh Cycle
tRC tRP RAS tT tRPC tCP CAS tCSR tCHR tRPC tCP tCSR tCHR tCRP tRAS tRP tRAS tRC tRP
Address tOFR tOFF Dout High-Z
* WE, OE : H or L
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HB56H164EJN-6B/7B
Hidden Refresh Cycle
tRC tRAS RAS tRSH tRCD tT CAS tRAD tASR Address Row tRAH tRAL tASC tCAH
tRP
tRC tRAS tRP
tRC tRAS
tRP
tCHR
tCRP
Column tRCH tRCS tRRH
WE tDZC High-Z tDZO tOEA OE tCAC tAA tRAC tCLZ Dout Dout tOFR tOHR tOFF tOH tOEZ tWEZ tOHO tOED tWED tCDD tRDD
Din
EDO Page Mode Read Cycle
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HB56H164EJN-6B/7B
tRP RAS tT tCSH CAS tCAS tRCHR tRCS WE
tWP
tRASP tHPC tCP tCAS tCP tCAS
tRCHC
tHPC
tHPC
tCPRH tCP tRSH tCAS
tCRP
tRCH
tRCS
tRRH tRCH
tRAL
tASC
tRAH tASR Address
Row tASC
tCAH
tASC
tASC tCAH tCAH
Column 4
tWED
tCAH
Column 1
Column 2
Column 3
tRDD tDZC tCAL tCAL tCAL tCAL tCDD
Din tDZO
High-Z
tCOL
tCOP
tOED tOFR tOHR
OE
tOEA tCAC tAA tCPA tCPA tOEZ tOEA tCAC tOHO Dout 2 tCPA tOEZ tOHO Dout 3 tOEZ
tAA tWEZ
tAA
tCAC tDOH
tAA
tCAC tOEA
tRAC Dout
tOFF tOHO
tOH Dout 4
Dout 1
Dout 2
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HB56H164EJN-6B/7B
EDO Page Mode Eary Write Cycle
tRASP tRP RAS tCSH tRCD tT CAS tCAS tCP tHPC tCAS tCP
tRSH tCAS
tCRP
tASR Address
tRAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
Row
Column 1 tWP tWCS tWCH
Column 2 tWP tWCS tWCH
Column N tWP tWCS tWCH
WE
tDS
tDH
tDS
tDH
tDS
tDH
Din
Din 1
Din 2
Din N
Dout
High-Z * OE : H or L > ** tWCS = tWCS(min.)
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HB56H164EJN-6B/7B
EDO Page Mode Delayed Write Cycle
tRASP RAS tCSH tRCD tT CAS tRAD tRAH tASR Address Row tASC tCAH Column 1 tCWL tRCS WE
tWP tWP tWP
tRP
tHPC tCAS tCP tCAS tCP
tRSH tCRP tCAS
tASC tCAH Column 2 tCWL tRCS
tASC tCAH Column N tCWL tRCS tRWL
tDZC
tDS tDH
tDZC tDS
Din 2
tDZC tDS tDH
Din N
tDH
Din tDZO tCLZ
Din 1
tDZO tOEH tCLZ tOEH
tDZO tCLZ tOEH High-Z
Dout Invalid Dout tOED tOEZ OE Invalid Dout tOED tOEZ Invalid Dout tOED tOEZ
* tOEH > tCWL =
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HB56H164EJN-6B/7B
EDO Page Mode Read-Modify-Write Cycle
tRASP RAS tHPRWC tT tRCD CAS tRAD tASC tCAH tCWL
Column 1
tRP
tRSH tCP tCAS
tCRP
tCAS
tCP
tCAS
tASC tCAH tCWL
Column 2
tASC
tRWL tCAH tCWL
tASR Address
tRAH
Row
Column N
tRWD tRCS WE tDZC tWP tDS
tDH
tCPW
tRCS
tCPW tRCS tAWD
tCWD
tAWD
tCWD
tAWD
tCWD
tDZC
tDS
tWP
tDH Din 2
tDZC
tWP
tDS tDH
Din
tCLZ
Din 1
tCLZ
tCLZ
Din N
tCAC tAA tRAC
tOEA
tCAC tAA tCPA tOEH
tOEA Dout 2
tCAC tAA tCPA tOEH
tOEA Dout N
tOEH
High-Z
Dout tDZO
Dout 1
tOHO
tDZO
tOEZ
tOHO
tDZO
tOEZ
tOHO
tOEZ
OE
tOED
tOED
tOED * tOEH > tCWL =
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HB56H164EJN-6B/7B
EDO Page Mode Mix Cycle (1)
tRP RAS tT tCSH CAS tRCD tWCS WE tRAH tASR Address
Row tASC Column 1
tRASP tCRP tCP tCAS tCP tCAS tCP tRSH tCAS
tCAS
tWP tWCH
tRCS
tRCS
tRRH tRCH
tWP tCPW
tAWD
tCAH tASC tCAH
Column 2 tASC
tASC tCAH
tRAL tCAH
Column 4
Column 3
tCAL tDS Din tDH High-Z tDS tDH
Din 3
tCAL
tRDD tCDD
Din 1
tWED
tOFR
tOED OE tCPA tAA tOEA tCAC Dout
tCPA tAA
tWEZ
tOEZ
tOHO
tCAC tDOH
Dout 2
tCPA tAA tCAC
tOEA
tOFF
tOH Dout 4
tOEZ tOHO
Dout 3
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HB56H164EJN-6B/7B
EDO Page Mode Mix Cycle (2)
tRP RAS tT tCSH CAS tRCD tRCS WE tWP tRAH tCAH tASR Address
Row tASC Column 1
tRASP tCRP tCP tCAS tCP tCAS tCP tRSH tCAS
tCAS tRCHR tRCH
tWCS tWCH
tRCS
tWP
tRCS
tRRH tRCH
tCPW tASC tCAH
Column 3
tRAL tASC tCAH
Column 4
tASC tCAH
Column 2
tCAL tDS Din High-Z
Din 2
tCAL tDH tDS tDH
Din 3
tCAL
tRDD tCDD
tWED tCOP tOED OE
tAA tOEA tOFR
tOED tCOL tOEA tCPA tAA tCAC tOEA
Dout 3
tWEZ
tRAC Dout
tCAC
tOEZ
tOHO
tCPA
tOEZ
tOHO
tOEZ
tOFF tOH Dout 4
tAA tCAC
tOHO
Dout 1
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HB56H164EJN-6B/7B
Physical Outline
133.35 5.250 3.00 0.118 127.35 5.014
Unit: mm/inch
5.28 max. 0.208 max.
3.00 0.118
1
84
C 8.89 0.350 11.43 0.450 36.83 1.450
B 54.61 2.150
A 1.270.10 0.0500.004
2- 3.00 2- 0.118
4.00 0.157
17.78 0.700
Detail A
Detail B 1.27 0.050 1.00 0.039
Detail C 1.00 0.039
2.54 min. 0.100 min.
0.25 max. 0.010 max.
1.000.05 0.0390002
3.1250.125 0.1230.005
3.1250.125 0.1230.005
6.35 0.250 2.000.10 0.0790.004
6.35 0.250 2.000.10 0.0790.004
25.40 1.000
4.00 min 0.157 min
168
85
27
HB56H164EJN-6B/7B
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
28
HB56H164EJN-6B/7B
Revision Record
Rev. 1.0 Date Feb. 21, '96 Contents of Modification
Initial issue
Drawn by S. Tsukui
Approved by K. Tsuneda
29

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