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HN58V65A Series HN58V66A Series
8192-word x 8-bit Electrically Erasable and Programmable CMOS ROM
ADE-203-539 (Z) Preliminary Rev. 0.1 Nov. 12, 1996 Description
The Hitachi HN58V65A series and HN58V66A series are a electrically erasable and programmable EEPROM's organized as 8192-word x 8-bit. Employing advanced MNOS memory technology and CMOS process and circuitry technology. They also have a 32-byte page programming function to make their write operations faster.
Features
* * * * * * * * * * * Single 2.7 to 5.5 V supply On-chip latches: address, data, CE, OE, WE Automatic byte write: 10 ms (max) Automatic page write (32 bytes): 10 ms (max) Fast access time: 100 ns (max) at 2.7 V VCC < 4.5 V 70 ns (max) at 4.5 V VCC 5.5 V Low power dissipation: active: 20 mW/MHz (typ) standby: 110 W (max) Ready/Busy Data polling and Toggle bit Data protection circuit on power on/off Conforms to JEDEC byte-wide standard Reliable CMOS with MNOS cell technology
Preliminary: This document contains information on a new product. Specifications and information contained herein are subject to change notice.
HN58V65A Series, HN58V66A Series
Features (cont)
* * * * * 105 erase/write cycles (in page mode) 10 years data retention Software data protection Write protection by RES pin (only the HN58V66A series) Industrial versions (Temperature range: -20 to 85C and -40 to 85C) are also available.
Ordering Information
Access time Type No. HN58V65AP-10 HN58V66AP-10 HN58V65AFP-10 HN58V66AFP-10 HN58V65AT-10 HN58V66AT-10 2.7 V VCC < 4.5 V 100 ns 100 ns 100 ns 100 ns 100 ns 100 ns 4.5 V VCC 5.5 V 70 ns 70 ns 70 ns 70 ns 70 ns 70 ns 28-pin plastic TSOP(TFP-28DB) 400 mil 28-pin plastic SOP (FP-28D) Package 600 mil 28-pin plastic DIP (DP-28)
Pin Arrangement
HN58V65AP Series HN58V65AFP Series
RDY/Busy A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE NC A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 RDY/Busy A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
HN58V66AP Series HN58V66AFP Series
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE RES A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
(Top view)
(Top view)
2
HN58V65A Series, HN58V66A Series
Pin Arrangement (cont)
HN58V65AT Series
A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 15 16 17 18 19 20 21 22 23 24 25 26 27 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A3 A4 A5 A6 A7 A12 RDY/Busy VCC WE NC A8 A9 A11 OE
(Top view) HN58V66AT Series
A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 15 16 17 18 19 20 21 22 23 24 25 26 27 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A3 A4 A5 A6 A7 A12 RDY/Busy VCC WE RES A8 A9 A11 OE
(Top view)
3
HN58V65A Series, HN58V66A Series
Pin Description
Pin name A0 to A12 I/O0 to I/O7 OE CE WE VCC VSS RDY/Busy RES* NC
1
Function Address input Data input/output Output enable Chip enable Write enable Power supply Ground Ready busy Reset No connection
Notes: 1. This function is supported by only the HN58V66A series.
Block Diagram
I/O0 High voltage generator
to
VCC VSS RES *1 OE CE WE RES *1 A0
to
I/O7
RDY/Busy
I/O buffer and input latch Control logic and timing
Y decoder
Y gating
A4 Address buffer and latch A5
to
X decoder
Memory array
A12
Data latch
Note: 1. This function is supported by only the HN58V66A series.
4
HN58V65A Series, HN58V66A Series
Mode Selection
Pin mode Read Standby Write Deselect Write Inhibit CE VIL VIH VIL VIL x x Data Polling Program reset VIL x OE VIL x*
2
WE VIH x VIL VIH VIH x VIH x
RES* 3 VH * x VH VH x x VH VIL
1
RDY/Busy High-Z High-Z High-Z to V OL High-Z -- -- VOL High-Z
I/O Dout High-Z Din High-Z -- -- Data out (I/O7) High-Z
VIH VIH x VIL VIL x
Notes: 1. Refer to the recommended DC operating conditions. 2. x : Don't care 3. This function supported by only the HN58V66A series.
Absolute Maximum Ratings
Parameter Supply voltage * Input voltage *
1 3 1
Symbol VCC Vin Topr Tstg
Value -0.6 to +7.0 -0.5* to +7.0* 0 to +70 -55 to +125
2 4
Unit V V C C
Operating temperature range * Storage temperature range Notes: 1. 2. 3. 4.
With respect to V SS . Vin min : -3.0 V for pulse width 50 ns. Including electrical characteristics and data retention. Should not exceed VCC + 1 V.
5
HN58V65A Series, HN58V66A Series
Recommended DC Operating Conditions
Parameter Supply voltage Input voltage Symbol VCC VIL VIH VH * Operating temperature Notes: 1. 2. 3. 4.
4
Min 2.7 -0.3* 1.9*
2 1
Typ 3.0 -- -- -- --
Max 5.5 0.6 VCC + 0.3* VCC + 1.0 70
3
Unit V V V V C
VCC - 0.5 0
Topr
VIL min: -1.0 V for pulse width 50 ns. VIH = 2.4 V for VCC = 3.6 to 5.5 V. VIH max: V CC + 1.0 V for pulse width 50 ns. This function is supported by only the HN58V66A series.
DC Characteristics (Ta = 0 to + 70C, VCC = 2.7 to 5.5 V)
Parameter Input leakage current Output leakage current VCC current (standby) Symbol I LI I LO I CC1 I CC2 VCC current (active) I CC3 Min -- -- -- -- -- -- -- -- Output low voltage Output high voltage Note: VOL VOH -- Typ -- -- -- -- -- -- -- -- -- Max 2* 2 20 1 6 10 12 25 0.4 --
1
Unit A A A mA mA mA mA mA V V
Test conditions VCC = 5.5 V, Vin = 5.5 V VCC = 5.5 V, Vout = 5.5/0.4 V CE = VCC CE = VIH Iout = 0 mA, Duty = 100%, Cycle = 1 s at VCC = 3.6 V Iout = 0 mA, Duty = 100%, Cycle = 1 s at VCC = 5.5 V Iout = 0 mA, Duty = 100%, Cycle = 100 ns at VCC = 3.6 V Iout = 0 mA, Duty = 100%, Cycle = 70 ns at VCC = 5.5 V I OL = 2.1 mA I OH = -400 A
VCC x 0.8 --
1. I LI on RES : 100 A max (only the HN58V66A series)
Capacitance (Ta = 25C, f = 1 MHz)
Parameter Input capacitance Output capacitance Note: Symbol Cin*
1 1
Min -- --
Typ -- --
Max 6 12
Unit pF pF
Test conditions Vin = 0 V Vout = 0 V
Cout*
1. This parameter is sampled and not 100% tested.
6
HN58V65A Series, HN58V66A Series
AC Characteristics (Ta = 0 to + 70C, VCC = 2.7 to 5.5 V)
Test Conditions * Input pulse levels : 0.4 V to 2.4 V (VCC = 2.7 to 3.6 V), 0.4 V to 3.0 V (VCC = 3.6 to 5.5 V) 0.4 V to VCC (RES pin*2) * Input rise and fall time : 5 ns * Input timing reference levels : 0.8, 1.8 V * Output load : 1TTL Gate +100 pF * Output reference levels : 1.5 V, 1.5 V Read Cycle 1 (VCC = 2.7 to 4.5 V)
HN58V65A/HN58V66A -10 Parameter Address to output delay CE to output delay OE to output delay Address to output hold OE (CE) high to output float* RES low to output float* RES to output delay*
2 1, 2 1
Symbol t ACC t CE t OE t OH t DF t DFR t RR
Min -- -- 10 0 0 0 0
Max 100 100 50 -- 40 350 450
Unit ns ns ns ns ns ns ns
Test conditions CE = OE = VIL, WE = VIH OE = VIL, WE = VIH CE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = OE= VIL, WE = VIH
Notes: 1. t DF and t DFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. This function is supported by only the HN58V66A series.
7
HN58V65A Series, HN58V66A Series
Read Cycle 2 (VCC = 4.5 to 5.5 V)
HN58V65A/HN58V66A -10 Parameter Address to output delay CE to output delay OE to output delay Address to output hold OE (CE) high to output float* RES low to output float* RES to output delay*
2 1, 2 1
Symbol t ACC t CE t OE t OH t DF t DFR t RR
Min -- -- 10 0 0 0 0
Max 70 70 40 -- 30 350 450
Unit ns ns ns ns ns ns ns
Test conditions CE = OE = VIL, WE = VIH OE = VIL, WE = VIH CE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = VIL, WE = VIH CE = OE = VIL, WE = VIH CE = OE= VIL, WE = VIH
Notes: 1. t DF and t DFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer driven. 2. This function is supported by only the HN58V66A series.
Read Timing Waveform
Address t ACC CE tCE OE tOE WE High tDF tOH
Data Out t RR
Data Out Valid
RES *1 Note: 1. This function is supported by only the HN58V66A series.
t DFR
8
HN58V65A Series, HN58V66A Series
Write Cycle 1 (VCC = 2.7 to 4.5 V)
Parameter Address setup time Address hold time CE to write setup time (WE controlled) CE hold time (WE controlled) WE to write setup time (CE controlled) WE hold time (CE controlled) OE to write setup time OE hold time Data setup time Data hold time WE pulse width (WE controlled) CE pulse width (CE controlled) Data latch time Byte load cycle Byte load window Write cycle time Time to device busy Write start time Reset protect time* Reset high time*
4, 5 4
Symbol t AS t AH t CS t CH t WS t WH t OES t OEH t DS t DH t WP t CW t DL t BLC t BL t WC t DB t DW t RP t RES
Min*1 0 50 0 0 0 0 0 0 50 0 200 200 100 0.3 100 -- 120 0*
3
Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max -- -- -- -- -- -- -- -- -- -- -- -- -- 30 -- 10* -- -- -- --
2
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s s ms ns ns s s
Test conditions
100 1
Notes: 1. Use this device in longer cycle than this value. 2. t WC must be longer than this value unless polling techniques or RDY/Busy are used. This device automatically completes the internal write operation within this value. 3. Next read or write operation can be initiated after t DW if polling techniques or RDY/Busy are used. 4. This function is supported by only the HN58V66A series. 5. This parameter is sampled and not 100% tested.
9
HN58V65A Series, HN58V66A Series
Write Cycle 2 (VCC = 4.5 to 5.5 V)
Parameter Address setup time Address hold time CE to write setup time (WE controlled) CE hold time (WE controlled) WE to write setup time (CE controlled) WE hold time (CE controlled) OE to write setup time OE hold time Data setup time Data hold time WE pulse width (WE controlled) CE pulse width (CE controlled) Data latch time Byte load cycle Byte load window Write cycle time Time to device busy Write start time Reset protect time* Reset high time*
4, 5 4
Symbol t AS t AH t CS t CH t WS t WH t OES t OEH t DS t DH t WP t CW t DL t BLC t BL t WC t DB t DW t RP t RES
Min*1 0 50 0 0 0 0 0 0 50 0 100 100 50 0.2 100 -- 120 0*
3
Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max -- -- -- -- -- -- -- -- -- -- -- -- -- 30 -- 10* -- -- -- --
2
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s s ms ns ns s s
Test conditions
100 1
Notes: 1. Use this device in longer cycle than this value. 2. t WC must be longer than this value unless polling techniques or RDY/Busy are used. This device automatically completes the internal write operation within this value. 3. Next read or write operation can be initiated after t DW if polling techniques or RDY/Busy are used. 4. This function is supported by only the HN58V66A series. 5. This parameter is sampled and not 100% tested.
10
HN58V65A Series, HN58V66A Series
Byte Write Timing Waveform(1) (WE Controlled)
t WC Address t CS CE t AS tWP WE t OES OE t DS Din t DW RDY/Busy High-Z tRP t DB High-Z t DH t OEH t BL t AH t CH
tRES RES * 1 V CC Note: 1. This function is supported by only the HN58V66A series.
11
HN58V65A Series, HN58V66A Series
Byte Write Timing Waveform(2) (CE Controlled)
Address t WS CE t AS WE t OES OE t DS Din t DW High-Z t RP t DB High-Z t DH t OEH t AH t CW t WH t BL t WC
RDY/Busy
t RES RES *1
V CC Note: 1. This function is supported by only the HN58V66A series.
12
HN58V65A Series, HN58V66A Series
Page Write Timing Waveform(1) (WE Controlled)
*1
Address A0 to A12
t AS WE t CS CE
t AH t WP t DL t CH t BLC
t BL
t WC
t OEH t OES OE t DH t DS
Din t DW RDY/Busy High-Z t DB High-Z
t RP
RES *2 t RES VCC
Notes: 1. A5 through A12 are page address and these address are latched at the first falling edge of WE. 2. This function is supported by only the HN58V66A series.
13
HN58V65A Series, HN58V66A Series
Page Write Timing Waveform(2) (CE Controlled)
*1
Address A0 to A12 CE
t AS
t AH t CW t DL t BLC
t BL
t WS WE
t WH
t WC
t OEH t OES OE t DH t DS
Din t DW RDY/Busy High-Z t DB High-Z
t RP
RES *2 t RES VCC Notes: 1. A5 through A12 are page address and these address are latched at the first falling edge of CE. 2. This function is supported by only the HN58V66A series.
14
HN58V65A Series, HN58V66A Series
Data Polling Timing Waveform
Address
An
An
An
CE
WE
t CE*1 t OEH
t OES
OE t OE*1 I/O7 Din X Dout X t WC Note: 1. See AC read characteristics. Dout X t DW
15
HN58V65A Series, HN58V66A Series
Toggle Bit This device provide another function to determine the internal programming cycle. If the EEPROM is set to read mode during the internal programming cycle, I/O6 will charge from "1" to "0" (toggling) for each read. When the internal programming cycle is finished, toggling of I/O6 will stop and the device can be accessible for next read or program. Toggle Bit Waveform
Next mode
*4
Address t CE *3 CE
WE t OE OE t OEH
*1 *2 *2
*3
t OES
I/O6
Din
Dout
Dout t WC
Dout
Dout t DW
Notes: 1. 2. 3. 4.
I/O6 biginning state is "1". I/O6 ending state will vary. See AC read characteristics. Any address location can be used, but the address must be fixed.
16
HN58V65A Series, HN58V66A Series
Software Data Protection Timing Waveform(1) (in protection mode)
VCC
CE
WE tBLC Address Data 1555 AA 0AAA 55 1555 A0 Write address Write data tWC
Software Data Protection Timing Waveform(2) (in non-protection mode)
VCC
tWC
Normal active mode
CE
WE
Address Data
1555 0AAA 1555 1555 0AAA 1555 AA 55 80 AA 55 20
17
HN58V65A Series, HN58V66A Series
Functional Description
Automatic Page Write Page-mode write feature allows 1 to 32 bytes of data to be written into the EEPROM in a single write cycle. Following the initial byte cycle, an additional 1 to 31 bytes can be written in the same manner. Each additional byte load cycle must be started within 30 s from the preceding falling edge of WE or CE. When CE or WE is kept high for 100 s after data input, the EEPROM enters write mode automatically and the input data are written into the EEPROM. Data Polling Data polling allows the status of the EEPROM to be determined. If EEPROM is set to read mode during a write cycle, an inversion of the last byte of data to be loaded outputs from I/O7 to indicate that the EEPROM is performing a write operation. RDY/Busy Signal RDY/B usy signal also allows status of the EEPROM to be determined. The RDY/Busy signal has high impedance except in write cycle and is lowered to V OL after the first write signal. At the end of a write cycle, the RDY/Busy signal changes state to high impedance. RES Signal (only the HN58V66A series) When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping RES low when VCC is switched. RES should be high during read and programming because it doesn't provide a latch function.
VCC
Read inhibit
Read inhibit
RES
Program inhibit
Program inhibit
18
HN58V65A Series, HN58V66A Series
WE, CE Pin Operation During a write cycle, addresses are latched by the falling edge of WE or C E, and data is latched by the rising edge of WE or CE. Write/Erase Endurance and Data Retention Time The endurance is 105 cycles in case of the page programming and 104 cycles in case of the byte programming (1% cumulative failure rate). The data retention time is more than 10 years when a device is page-programmed less than 104 cycles. Data Protection 1. Data Protection against Noise on Control Pins (CE, OE, WE) during Operation During readout or standby, noise on the control pins may act as a trigger and turn the EEPROM to programming mode by mistake. To prevent this phenomenon, this device has a noise cancellation function that cuts noise if its width is 15 ns or less in programming mode. Be careful not to allow noise of a width of more than 15 ns on the control pins.
WE CE
VIH 0V
VIH OE 0V
15 ns max
19
HN58V65A Series, HN58V66A Series
2. Data protection at VCC on/off When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act as a trigger and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the EEPROM must be kept in an unprogrammable state while the CPU is in an unstable state.
VCC CPU RESET * Unprogrammable
* Unprogrammable
*The EEPROM shoud be kept in unprogrammable state during V on/off by using CPU RESET signal. CC
(1) Protection by CE, OE, WE To realize the unprogrammable state, the input level of control pins must be held as shown in the table below.
CE OE WE x: Don't care. VCC: Pull-up to VCC level. VSS : Pull-down to V SS level. VCC x x x VSS x x x VCC
20
HN58V65A Series, HN58V66A Series
(2) Protection by RES (only the HN58V66A series) The unprogrammable state can be realized by that the CPU's reset signal inputs directly to the EEPROM's RES pin. RES should be kept VSS level during VCC on/off. The EEPROM breaks off programming operation when RES becomes low, programming operation doesn't finish correctly in case that RES falls low during programming operation. RES should be kept high for 10 ms after the last data input.
VCC
RES Program inhibit WE or CE Program inhibit
1 s min 100 s min
10 ms min
21
HN58V65A Series, HN58V66A Series
3. Software data protection To prevent unintentional programming caused by noise generated by external circuits, this device has the software data protection function. In software data protection mode, 3 bytes of data must be input before write data as follows. And these bytes can switch the non-protection mode to the protection mode.
Address Data
1555 AA 0AAA 55 1555 A0 Write address Write data } Normal data input
Software data protection mode can be cancelled by inputting the following 6 bytes. After that, this device turns to the non-protection mode and can write data normally. But when the data is input in the cancelling cycle, the data cannot be written.
Address 1555 0AAA 1555 1555 0AAA 1555 Data AA 55 80 AA 55 20
The software data protection is not enabled at the shipment. Note: There are some differences between Hitachi's and other company's for enable/disable sequence of software data protection. If there are any questions , please contact with Hitachi sales offices.
22
HN58V65A Series, HN58V66A Series
Package Dimensions
HN58V65AP Series HN58V66AP Series (DP-28)
35.6 36.5 Max
Unit : mm
28
15 13.4 14.6 Max
1
1.2 1.9 Max
14 2.54 Min 5.70 Max 15.24
0.51 Min
2.54 0.25
0.48 0.10
0.25 - 0.05 0 - 15
+ 0.11
HN58V65AFP Series HN58V66AFP Series (FP-28D)
18.3 18.75 Max 28 15 8.4
Unit : mm
2.5 Max
1 0.895
14
0.17 - 0.07
+ 0.08
11.8 0.3
0 - 10 1.27 0.10 0.40 - 0.05
+ 0.10
0.1 Min
1.0
23
HN58V65A Series, HN58V66A Series
Package Dimensions (cont)
HN58V65AT Series HN58V66AT Series (TFP-28DB)
8.0 8.1 Max 28 15
Unit : mm
1
+0.07 -0.02
14 0.55
0.20
1.0
11.8
M
5 Max
+0.03 -0.02
0.05 Min 0.20Max
0.5 0.1
1.2 Max
0.10
0.17
13.4 0.3
24
HN58V65A Series, HN58V66A Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
25
HN58V65A Series, HN58V66A Series
Revision Record
Rev. 0.0 0.1 Date Mar. 18, 1996 Nov. 12, 1996 Contents of Modification Initial issue Change of FP-28DA to DP-28 Addition of 5 V specification Drawn by Approved by
M. Terasawa T. Muto
26

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