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| (R) ST10X167/F168 Reducing Analog-Digital Conversion Error APPLICATION NOTE The ST10X167/F168 contains an Analog / Digital Converter with 10-bit resolution, 9.7 s conversion time, a sample & hold circuit on-chip, ESD protected analog inputs and a "Total Unadjusted Error" of 2LSB. An automatic self-calibration adjusts the ADC module to changing temperatures or process variations, giving high performance across the whole automotive temperature range. This application note identifies the causes of ADC error and gives solutions to optimize ADC performance. 72-TCH-175-00 19 Oct 1998 APPLICATION NOTE ST10X167/F168 Table of Contents 1 1.1 1.2 1.3 2 2.1 2.2 2.3 3 Sources of ADC error - - - - - - - - - - - - - - - - - - - - - 3 Analog input signal error - - - - - - - - - - - - - - - - - - - - 3 Input overload errors - - - - - - - - - - - - - - - - - - - - - - 6 Reference voltage errors - - - - - - - - - - - - - - - - - - - - 6 How to minimize error - - - - Optimize the input signal - - - - Reduce input overload error - - Reference voltage error reduction 7 7 7 8 Appendix - Definitions - - - - - - - - - - - - - - - - - - - - 9 2/10 72-TCH-175-00 APPLICATION NOTE ST10X167/F168 1 Sources of ADC error Sources of ADC accuracy error are classified into 3 categories: * Analog input signal error * Input overload error * Reference voltage error Each of these categories is described in the following sections. 1.1 Analog input signal error Analog input signal error can be created by poor matching of the source internal resistance with the ADC input parameters, either caused by, * voltage drop in the voltage source resistance due to input leakage current, * or by poor charging of the ADC internal capacitance (Cin). Analog input error can also be caused by noise from the analog input signal. This section described each of these causes. RASRC R1 SAMPLE P5.x V VIN CIO IOZ1 Leakage CIN AGND * * * * AGND IOZ1 (Input leakage current Port5): max +/- 500 nA (test Condition: 0.45V Figure 1 Source internal resistance errors 72-TCH-175-00 3/10 APPLICATION NOTE ST10X167/F168 Sources of ADC error Refer to Figure 1 for a schematic of source internal resistance errors. Voltage drop in the source resistance: The error generated by the voltage source internal resistance is: R SOUR CE x I 0Z1 ---- --------------- x 1024 ---error ( LSB ) = ------------ ----V A R E F - V A GND For example: A source resistance of 15Kohm and a specified leakage current (IOZ1) of +/- 500nA will cause a voltage error of +/- 7.5mV or +/- 1.5LSB. Refer the latest product data sheet for the value of IOZ1. Note Input leakage current is caused by parasitic current at input pin protection; this protection is necessary to protect the device against ESD (Electrical Static Discharge) and against overload. Poor charging of the ADC internal capacitance: During the sample time, the input capacitance (Cio and Cin) must be charged/discharged by the external source. The internal resistance of the source must allow the capacitance to reach its final value before the end of sample time: see Figure 2. 4/10 72-TCH-175-00 APPLICATION NOTE ST10X167/F168 Voltage at sample and hold input Vin Voltage error at time ti ts Vref/2 time error 0 Vref/2 Vref Vin Figure 2 Possible error due to input capacitance charging If this does not happen, i.e. if the source resistance is mis-matched to the sample time, a voltage loss will occur at the sample and hold stage. This voltage loss causes an accuracy loss when increasing or decreasing the input voltage from Vref/2 (hold capacitor is pre-charged to Vref/2 before sampling to reduce charge/discharge time). The error is calculated by the formula: 1 * M ax error ( LSB ) = -- x 1024 x exp ( -t s R x C ) 2 Where: TS = sample time in s, R = RSOURCE + R1 in , C = Cin + Cio in F. For example: Since the error is proportional to the difference between Vin and Vref/2, the effect produces a non-linearity in the conversion of large-amplitude signals. In practice, if Ts>7RC, the maximum error is reduced to <1/2 LSB (<0.05%). 72-TCH-175-00 5/10 APPLICATION NOTE ST10X167/F168 Sources of ADC error Errors due to noise from the input signal: The sample and hold circuitry is not designed to filter the input analog signal. Noise at the input signal will cause input voltage variation and, therefore, accuracy loss. 1.2 Input overload errors These errors are caused by input overload. During overload, internal protection-diodes sink current to reduce the overload voltage. Because of the close proximity of the internal protection-diodes and the ADC circuitry, the ADC performance is affected. The ST10C167 accepts up to 10mA of input overload current while guaranteeing a Total Unadjusted Error (TUE) of +/- 2LSB (refer to the product Data sheet for values). Overload above the specified limit causes ADC accuracy loss and may damage the circuit. 1.3 Reference voltage errors The accuracy of the conversion is obviously linked to the accuracy of the reference voltage. While noise and/or voltage variations are a well known source of error, internal resistance is another source of error from the reference voltage. During the conversion, the ADC internal capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage must allow the capacitance to reach its correct voltage within the conversion time (see Figure 2). A mis-match between the conversion time and reference voltage internal resistance will cause accuracy errors. P5.X VIN RREF VAREF R IN ADC VREF C REF VAGND Figure 3 Simplified circuit for analog reference voltage 6/10 72-TCH-175-00 APPLICATION NOTE ST10X167/F168 2 2.1 How to minimize error Optimize the input signal There are three possible optimizations: Minimize the total source impedance seen by the ST10: This means choosing sensors with low output impedance (not always easy for some types of sensor), and minimizing the serial resistance of any protection devices between the analog source and the input pin (while still providing a voltage protection level compatible with the circuit specification). Match the sample time to the analog source impedance: Use the formula that relates sample time to source internal resistance (given in the ST10 data sheet) to match the source resistance to one of the available sample times. For example: For a source impedance of 10kOhms, and given R A SR C = ts 330 - 0.25 then the minimum sample time is: t s = 330 x ( R A SR C + 0.25 ) t s = 3380ns ( min ) Note This formula includes a safety factor of 10, therefore from the equation for error on page 4, dynamic errors are 0.02LSB. Furthermore, RASRC is the total source impedance seen by the device and, therefore, includes any protection components. Reduce noise at the input pin: Add an external RC filter (with attention to the source internal resistance). Compute the average value of different samples in the software routine. 2.2 Reduce input overload error Because errors are induced from overload current going into/out of the integrated protection diodes, optimizations minimize this current in 3 ways: Minimize the over-voltage at the analog source: The possible optimizations depend on the user application, typically, they involve the addition of Zener diodes or transils. For component selection, refer to ST-On-Line Discrete Devices/Protection Circuit data books. Minimize the over-voltage at the ST10 analog input pins: Either, add protection diode(s) or transil(s), or add a serial resistor. CAUTION: the addition of a serial resistor increases the source internal resistance and, therefore, may impact maximum conversion speed. 72-TCH-175-00 7/10 APPLICATION NOTE ST10X167/F168 How to minimize error Synchronize ADC conversion with analog transitions: Where possible, avoid carrying out conversions when analog inputs are scheduled to go into overload conditions (at least, during the transition phase). 2.3 Reference voltage error reduction The possible optimizations are: Reference voltage noise: Reduce noise by careful design; PCB routing and de-coupling of the reference voltage: * Place the analog source as close as possible to the VAREF pin. * Avoid routing any high frequency/high amplitude signals near to the analog source. * Make sure that the Voltage Reference source presents a low impedance from dc to well above the max. sampling frequency (1/tc): see Figure 4. ZAREF 10/tc Figure 4 Analog reference source - impedance characteristics Match the reference voltage internal resistance to conversion time: Use the formula that relates conversion time to source internal resistance (given in the ST10 data sheet) to match the reference voltage to one of the 3 available conversion times. For example: given tc c R A R E F = -------- - 0.25 165 8/10 72-TCH-175-00 APPLICATION NOTE ST10X167/F168 then the max. source impedance for tcc of 1200ns is: 1200 ----- R A R E F = -- ---- - 0.25 165 = 7kOhms ( max ) Note This should hold up to f=10/tc, so if tc 20s,ZAREF < 7k, up to 500kHz. R VAREF C Z AREF=R//(1/jwC) VAGND Figure 5 Typical analog reference circuit Note Figure 5 shows a commonly used circuit for the analog reference voltage. 3 Appendix - Definitions LSB: Least Significant Bit. Resolution: defines the smallest input voltage change required to increment the output of the ADC between one code and the next adjacent code. Resolution is a design parameter rather than a performance specification; it says nothing about accuracy. Resolution is either expressed in percent of the full-scale, or in binary bits. Accuracy: defines the worst case difference between the actual input voltage and the full-scale weighted equivalent of the binary output code. For ST10 devices, the Total Unadjusted Error describes the maximum sum of all errors intrinsic to the ADC. Intrinsic errors: are errors intrinsic to the ADC itself, such as: quantizing error, scale error, offset error, hysteresis error, linearity error. For simplicity and ease of use, the ST10 ADC specification gives the sum of all intrinsic errors (Total Unadjusted Errors). 72-TCH-175-00 9/10 APPLICATION NOTE ST10X167/F168 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (R) The ST logo is a registered trademark of STMicroelectronics (c) 1998 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://ww w.st.com 10/10 72-TCH-175-00 |
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