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HN62W5016N Series
524288-word x 32-bit/1048576-word x 16-bit CMOS MASK Programmable ROM
Preliminary
Description
The HN62W5016N is a 16-Mbit CMOS mask-programmable ROM organized either as 524,288-word by 32-bit or as 1,048,576-word by 16-bit. Realizing low power consumption, this memory is allowed for battery operation. And a high speed access of 120/150 ns is the most suitable to the system using a high speed micro-computer by 32-bit.
Features
* * Low voltage operation: 3.3 V 0.3 V High Speed Normal access time: 120 ns/150 ns (max) Page access time: 40 ns/50 ns (max) Low power consumption Active: 360 mW (max) Standby: 0.72 mW (max) Power down mode: 36 W (max) Double word-wide or word-wide data organization with DW/W 4 double-word page access on double word-wide mode 8 word page access on word-wide mode Three-state data output for or-tying LVTTL compatible
*
* * * * *
Ordering Information
Type No. HN62W5016NF-12 HN62W5016NF-15 Access Time 120 ns 150 ns Package 70 pin plastic SSOP (FP-70DS)
Note: The specifications of this device are subject to change without notice. Please contact your hearest Hitachi's Sales Dept. regarding specifications.
HN62W5016N Series
Pin Arrangement
HN62W5016NF A0 A1 A2 A3 A4 A5 VDD D0 D16 D1 D17 VSS VDD D2 D18 D3 D19 D4 D20 D5 D21 VSS VDD D6 D22 D7 D23 VSS A6 A7 A8 A9 A10 A11 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 (Top view) 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 PWD NC NC DW/W OE CE VSS D31/A-1 D15 D30 D14 VSS VDD D29 D13 D28 D12 D27 D11 D26 D10 VSS VDD D25 D9 D24 D8 VDD NC A18 A17 A16 A15 A14 A13
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HN62W5016N Series
Pin Description
Pin name A2 to A18 A-1, A0 to A1 D0 to D31 DW/W CE OE PWD NC VDD VSS Function Address inputs Page address inputs Data output 32/16 bit (Double word/word) mode switch inputs Chip enable Output enable Power down input No connection Power supply Ground
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HN62W5016N Series
Block Diagram
A18 to A8 A7 to A2 A1 to A0 Address buffer X Decoder Memory array
Y Decoder
Y Gating
Page Decoder
(A-1)*1 DW/W OE CE PWD Control Logic
Double Word /Word
3-state output buffer
D0 to D31/(D15) Note: 1. A-1 is least signifcant address. When DW/W is 'low', D30 to D16 goes to high impedance state and D31 should be A-1. DW/W = VIH : 32-bit (D31 to D0) DW/W = VIL : 16-bit (D15 to D0)
Mode Selection
Pin Data output Mode Power down Standby Output disable Read (32-bit) Read (16-bit) Read (16-bit) PWD L H H H H H CE x
*1
Address input D16-D31 High-Z High-Z High-Z D16 to D31 High-Z High-Z LSB -- -- -- A0 A-1 A-1 MSB -- -- -- A18 A18 A18
OE x x H L L L
DW/W x x x H L L
D31/A-1 x x x Dout L H
D0-D15 High-Z High-Z High-Z D0 to D15 D0 to D15 D16 to D31
*2
H L L L L
Notes: 1. x: Don't care. 2. High-Z: High impedance.
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HN62W5016N Series
Absolute Maximum Ratings
Parameter Supply voltage All input and outpu tvoltage Operating temperatue range Storage temperature range Temperature under bias Note: 1. With respect to V SS Symbol VDD Vin, Vout Topr Tstg Tbias Value -0.3 to +5.5 -0.3 to VDD + 0.3 0 to +70 -55 to +125 -20 to +85 Unit V V C C C Note 1 1
Recommended DC Operating Conditions (VSS = 0 V, Ta = 0 to 70C)
Parameter Supply voltage Input voltage Symbol VDD VIH VIL Min 3.0 2.2 -0.3 Typ 3.3 -- -- Max 3.6 VDD + 0.3 0.8 Unit V V V
DC Characteristics (VDD = 3.3 0.3 V, VSS = 0 V, Ta = 0 to 70C)
Parameter Operating power supply current Standby power supply current Symbol I DD I SB1 I SB2 Power down supply current Input leakage current Output leakage current Output voltage I PWD |IIL| |IOL | VOH VOL Min -- -- -- -- -- -- 2.4 -- Max 100 200 3 10 10 10 -- 0.4 Unit mA A mA A A A V V Test Conditions VDD = 3.6 V, IDOUT = 0 mA, tRC = min VDD = 3.6 V, CE V DD - 0.2 V VDD = 3.6 V, CE 2.2 V VDD = 3.6 V, PWD 0.2 V VIN = 0 to VDD CE = 2.2 V, VOUT = 0 to VDD I OH = -2 mA I OL = 2 mA
Capacitance (VDD = 3.3 0.3 V, VSS = 0 V, Ta = 25C, VIN = 0 V, f = 1 MHz)
Parameter Input capacitance
*1 *1
Symbol Cin Cout
Min -- --
Max 10 15
Unit pF pF
Output capacitance Note:
1. This parameter is sampled and not 100% tested. D31/A-1 pin is output.
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HN62W5016N Series
AC Characteristics (VDD = 3.3 0.3 V, VSS = 0 V, Ta = 0 to 70C)
* * * * Output load: 1TTL + CL = 100 pF (including jig capacitance) Input pulse level: 0.4 to 2.4 V Input and output timing reference level: 1.4 V Input rise and fall time: 5 ns
HN62W5016N-12 Parameter Read cycle time Page read cycle time Address access Page access time CE access time OE access time DW/W access time Output hold time from address change Output hold time from CE Output hold time from OE Output hold time from DW/W Output hold time from PWD CE to output in high-Z OE to output in high-Z DW/W to output in high-Z CE to output in low-Z OE to output in low-Z DW/W to output in low-Z Recovery time from PWD Note: Symbol t RC t PC t AA t PA t ACE t OE t DWW t DHA t DHC t DHO t DHD t DHP t CHZ t OHZ t DHZ t CLZ t OLZ t DLZ tR Min 120 40 -- -- -- -- -- 0 0 0 0 0 -- -- -- 5 5 5 10 Max -- -- 120 40 120 40 120 -- -- -- -- -- 40 40 40 -- -- -- -- HN62W5016N-15 Min 150 50 -- -- -- -- -- 0 0 0 0 0 -- -- -- 5 5 5 10 Max -- -- 150 50 150 50 150 -- -- -- -- -- 50 50 50 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s 1 1 1 Note
1. t CHZ, tOHZ and t DHZ are defined as the time at which the output achieves the open circuit conditions and are not referred to output voltage levels.
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HN62W5016N Series
Timing Waveforms
Double Word Mode (DW/W = `VIH') or Word Mode (DW/W = `VIL')
t RC Address t AA t ACE CE t CLZ t OE OE t OLZ Dout High-Z Valid data t DHO t OHZ High-Z t DHC t CHZ t DHA
Notes: 1. tDHA, t DHC, tDHO: Determined by faster. 2. t AA, tACE , tOE: Determined by slower. 3. t CLZ , t OLZ : Determined by slower.
Double Word Mode, Word Mode Switch
A-1
High-Z
High-Z
t AA
DW/W
t DHA
t DHZ
D15 to D0 Valid data
t DWW
Valid data
t DHD
D31 to D16
t DLZ High-Z
Valid data
Notes: 1. CE and OE are enable, A18 to A0 are valid. 2. D31/A-1 pin is in the output state when DW/W is high, CE and OE are enable. Therefore, the input signals of opposite phase to the output must not be applied to them.
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HN62W5016N Series
Page Mode
A2 to A18
t RC
A0, A1,(A-1) *1
t PC
t PC
t PC
t PA t AA t DHA
t PA t DHA
t PA t DHA t DHA
Dout
Valid data
Valid data
Valid data
Valid data
Notes: 1. Page address is determind as below Double word mode (DW/W = 'VIH'): A0, A1 Word mode (DW/W = 'VIL'): A-1, A0, A1 2. CE and OE are enable.
Power Down Mode
CE
Address t AA Dout Valid data t DHP PWD High-Z tR Valid data
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HN62W5016N Series
Power Up Sequence
VDD
3.0V 0V CE
t P 100s
t ACE
Address
t AA
Dout Valid data
tR 10s
PWD
Notes: 1. This device is used ATD(Address Transition Detector). Therefore, transfer either CE or address(A18 to A2) after power up to 3.0 V. 2. tP, tR: Determined by slower.
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HN62W5016N Series
Package Dimensions
HN62W5016NF Series (FP-70DS)
Unit: mm
28.57 28.87 Max 70 36 12.70 3.15 Max 1 0.935 Max 35
0.17 0.05
15.90 0.2 1.60
0 - 7 0.32 -0.07
+0.08
0.80 0.10 0.15 M
0.1 +0.10 -0.05
0.80 0.15
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