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M68Z128
5V, 1 Mbit (128Kb x8) Low Power SRAM with Output Enable
PRELIMINARY DATA
ULTRA LOW DATA RETENTION CURRENT - 10nA (typical) - 2.0A (max) OPERATION VOLTAGE: 5V 10% 128Kb x 8 VERY FAST SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 55ns LOW VCC DATA RETENTION: 2V TRI-STATE COMMON I/O LOW ACTIVE and STANDBY POWER AUTOMATIC POWER-DOWN WHEN DESELECTED INTENDED FOR USE WITH ST ZEROPOWER AND TIMEKEEPER CONTROLLERS
TSOP32 (N) (8 x 20mm)
Figure 1. Logic Diagram DESCRIPTION The M68Z128 is a 1 Mbit (1,048,576 bit) CMOS SRAM, organized as 131,072 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 5V 10% supply, and all inputs and outputs are TTL compatible. Table 1. Signal Names A0-A16 DQ0-DQ7 E1 E2 G W VCC VSS Address Inputs Data Inputs / Outputs Chip Enable 1 Chip Enable 2 Output Enable Write Enable Supply Voltage Ground
VSS
AI00647
VCC
17 A0-A16
8 DQ0-DQ7
W E1 E2 G M68Z128
May 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M68Z128
Table 2. Absolute Maximum Ratings (1)
Symbol TA TSTG VIO
(2)
Parameter Ambient Operating Temperature Storage Temperature Input or Output Voltages Supply Voltage Output Current Power Dissipation
Value 0 to 70 -65 to 150 -0.3 to VCC + 0.3 -0.3 to 7.0 20 1
Unit C C V V mA W
VCC IO
(3)
PD
Notes: 1. Except for the rating "Operating Temperature Range" stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Up to a maximum operating VCC of 5.5V only. 3. One output at a time, not to exceed 1 second duration.
Figure 2. TSOP Pin Connections
A11 A9 A8 A13 W E2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
1
32
8 9
M68Z128
25 24
16
17
AI00657
G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
DESCRIPTION (cont'd) This device has an automatic power-down feature, reducing the power consumption by over 99% when deselected. The M68Z128 is available in TSOP32 (8 x 20mm) package.
READ MODE The M68Z128 is in the Read mode whenever Write Enable (W) is High with Output Enable (G) Low, and both Chip Enables (E1 and E2) are asserted. This provides access to data from eight of the 1,048,576 locations in the static memory array, specified by the 17 address inputs. Valid data will be available at the eight output pins within tAVQV after the last stable address, providing G is Low, E1 is Low and E2 is High. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tE1LQV, tE2HQV, or tGLQV) rather than the address. Data out may be indeterminate at tE1LQX, tE2HQX and tGLQX, but data lines will always be valid at tAVQV. WRITE MODE The M68Z128 is in the Write mode whenever the W and E1 pins are Low, with E2 High. Either the Chip Enable inputs (E1 and E2) or the Write Enable input (W) must be de-asserted during Address transitions for subsequent write cycles. Write begins with the concurrence of both Chip Enables being active with W low. Therefore, address setup time is referenced to Write Enable and both Chip Enables as tAVWL, tAVE1L and tAVE2H respectively, and is determined by the latter occurring edge. The Write cycle can be terminated by the earlier rising edge of E1, W, or the falling edge of E2. If the Output is enabled (E1 = Low, E2 = High and G = Low), then W will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for tDVE1H before the rising edge of E1 or for tDVE2L before the
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M68Z128
Table 3. Operating Modes
Mode Read Read Write Deselect Deselect
Note: X = VIH or VIL
E1 VIL VIL VIL VIH X
E2 VIH VIH VIH X VIL
W VIH VIH VIL X X
G VIH VIL X X X
DQ0-DQ7 Hi-Z Data Output Data Input Hi-Z Hi-Z
Power Active Active Active Standby Standby
Table 4. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 5ns 0 to 3V 1.5V
Figure 4. AC Testing Load Circuit
5.0V
Note that Output Hi-Z is defined as the point where data is no longer driven.
DEVICE UNDER TEST 990
1800
OUT
falling edge of E2, whichever occurs first, and remain valid for tWHDX, tE1HDX or tE2LDX. OPERATIONAL MODE The M68Z128 has a Chip Enable power down feature which invokes an automatic standby mode whenever either Chip Enable is de-asserted (E1 = High or E2 = Low). An Output Enable (G) signal provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W, E1, and E2 as summarized in the Operating Modes table.
CL = 50pF or 5pF
CL includes JIG capacitance
AI00658B
Table 5. Capacitance (1) (TA = 25 C, f = 1 MHz )
Symbol CIN COUT
(2)
Parameter Input Capacitance on all pins (except DQ) Output Capacitance
Test Condition VIN = 0V VOUT = 0V
Min
Max 9 9
Unit pF pF
Notes: 1. Sampled only, not 100% tested 2. Outputs deselected
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M68Z128
Figure 3. Block Diagram
VCC VSS (9) A CHIP ENABLE. DQ (8) DQ INPUT DATA CTRL I/O CIRCUITS COLUMN DECODER ROW DECODER MEMORY ARRAY
A
CHIP ENABLE. CHIP ENABLE (8) A A
W E1 E2 G
AI00665
Table 6. DC Characteristics (TA = 0 to 70 C; VCC = 5V 10%)
Symbol ILI ILO ICC1 (1) ICC2
(2)
Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Test Condition 0V VIN VCC 0V VOUT VCC VCC = 5.5V, (-55) VCC = 5.5V, E1 = VIH or E2 = VIL, f = 0 VCC = 5.5V, E1 VCC - 0.3V or E2 0.3V, f = 0
Min
Typ
Max 1 1
Unit A A mA mA A V V V V
30 0.1 0.4 -0.3 2.2
70 2 20 0.8 VCC + 0.3 0.4
ICC3 (3) VIL VIH VOL VOH
IOL = 2.1mA IOH = -1mA 2.4
Notes: 1. Average AC current, Outputs open, cycling at tAVAV minimum 2. All other Inputs at VIL 0.8V or VIH 2.2V 3. All other Inputs at VIL 0.3V or VIH VCC - 0.3V
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M68Z128
Table 7. Read and Standby Modes AC Characteristics (TA = 0 to 70C; VCC = 5V 10%)
M68Z128 Symbol Parameter Min tAVAV tAVQV
(1)
-55 Max
Unit
Read Cycle Time Address Valid to Output Valid Chip Enable 1 Low to Output Valid Chip Enable 2 High to Output Valid Output Enable Low to Output Valid Chip Enable 1 Low to Output Transition Chip Enable 2 High to Output Transition Output Enable Low to Output Transition Chip Enable 1 High to Output Hi-Z Chip Enable 2 Low to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition Chip Enable 1 Low or Chip Enable 2 High to Power Up Chip Enable 1 High or Chip Enable 2 Low to Power Down
55 55 55 55 20 5 5 0 20 20 20 5 0 55
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tE1LQV (1) tE2HQV tGLQV tE1LQX
(1) (1) (3)
tE2HQX (3) tGLQX tE1HQZ tE2LQZ
(3) (2,3) (2,3)
tGHQZ (2,3) tAXQX (1) tPU tPD
Notes: 1. CL = 100pF (see Figure 4) 2. CL = 5pF (see Figure 4) 3. At any given temperature and voltage condition, tEIHQZ + tEZHQZ is less than tEILQX and tEZLQX, tGHQZ is less than tGLQX for any given device.
Figure 5. Address Controlled, Read Mode AC Waveforms
tAVAV A0-A16 tAVQV VALID tAXQX
DQ0-DQ7
DATA VALID
AI01078
Note: E1 = Low, E2 = High, G = Low, W = High
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M68Z128
Figure 6. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
tAVAV A0-A16 tAVQV tE1LQV E1 tE1LQX tE2HQV E2 tE2HQX tGLQV G tGLQX DQ0-DQ7 VALID
AI00805
VALID tAXQX tE1HQZ
tE2LQZ
tGHQZ
Note: Write Enable (W) = High
Figure 7. Standby Mode AC Waveforms
E1
E2 ICC1 ICC2 tPU 50% tPD
AI00806B
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M68Z128
Table 8. Write Mode AC Characteristics (TA = 0 to 70C; VCC = 5V 10%)
M68Z128 Symbol Parameter Min tAVAV tAVWL tAVWH tAVE1H tAVE2L tWLWH tWHAX tWHDX tWHQX
(2)
-55 Max
Unit
Write Cycle Time Address Valid to Write Enable Low Address Valid to Write Enable High Address Valid to Chip Enable 1 High Address Valid to Chip Enable 2 Low Write Enable Pulse Width Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Output Transition Write Enable Low to Output Hi-Z Address Valid to Chip Enable 1 Low Address Valid to Chip Enable 2 High Chip Enable 1 Low to Chip Enable 1 High Chip Enable 2 High to Chip Enable 2 Low Chip Enable 1 High to Address Transition Chip Enable 2 Low to Address Transition Input Valid to Write Enable High Input Valid to Chip Enable 1 High Input Valid to Chip Enable 2 Low
55 0 45 45 45 45 0 0 5 20 0 0 45 45 0 0 25 25 25
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tWLQZ (1,2) tAVE1L tAVE2H tE1LE1H tE2HE2L tE1HAX tE2LAX tDVWH tDVE1H tDVE2L
Note: 1. CL = 5pF (see Figure 4) 2. At any given temperature and voltage condition, tWHQX is less than tWLQZ for any given device.
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M68Z128
Figure 8. Write Enable Controlled, Write AC Waveforms
tAVAV A0-A16 VALID tAVWH tAVE1L E1 tAVE2H E2 tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI00807
tWHAX
tWHQX
Note: Output Enable (G) = Low
Figure 9. Chip Enable Controlled, Write AC Waveforms (1,2)
tAVAV A0-A16 VALID tAVE1H tAVE1L E1 tE1LE1H tE1HAX
tAVE2L tAVE2H E2 tAVWL W tE1HDX tE2LDX DQ0-DQ7 DATA INPUT tDVE1H tDVE2L tE2HE2L tE2LAX
AI00808
Notes: 1. Output Enable (G) = High 2. If E1 goes High or E2 goes Low simultaneously with W high, the output remains in a high-impedance state.
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M68Z128
Table 9. Low VCC Data Retention Characteristics (TA = 0 to 70C)
Symbol ICCDR VDR tCDR tER (1) Parameter Supply Current (Data Retention) Supply Voltage (Data Retention) Chip Disable to Power Down Operation Recovery Time Test Condition VCC = 3V, E1 VCC - 0.3V or E2 0.3V, f = 0 E1 VCC - 0.3V or E2 0.3V, f = 0 E1 VCC - 0.3V or E2 0.3V, f = 0 2 0 tAVAV Min Typ 0.01 Max 2 Unit A V ns ns
Note: 1. See Figure 10 for measurement points. Guaranteed but not tested. tAVAV is Read cycle time.
Figure 10. Low VCC Data Retention AC Waveforms
DATA RETENTION MODE 5V VCC 3V VDR > 2.0V tCDR E1 VDR - 0.3V E1 2.2V tER
E2 0.3V E2 0.8V
AI00659
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M68Z128
ORDERING INFORMATION SCHEME Example: M68Z128 -55 N 1
Speed -55 55 ns N
Package TSOP32 (8 x 20mm)
Temperature Range 1 0 to 70 C
For a list of available options (Speed, Package, etc... ) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
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M68Z128
TSOP32 - 32 lead Plastic Thin Small Outline (8 x 20mm)
Symb Typ A A1 A2 B C D D1 E e L N CP 0.50 0.05 0.95 0.17 0.10 19.80 18.30 7.80 0.40 0 32 0.10 mm Min Max 1.20 0.15 1.05 0.23 0.20 20.20 18.50 8.20 0.60 5 0.020 0.002 0.037 0.006 0.004 0.780 0.720 0.307 0.016 0 32 0.004 Typ inches Min Max 0.047 0.007 0.041 0.010 0.008 0.795 0.728 0.323 0.024 5
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
A1
L
Drawing is not to scale
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M68Z128
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1998 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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