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| (R) 74LVX174 HEX D-TYPE FLIP FLOP WITH CLEAR WITH 5V TOLERANT INPUTS s s s s s s s s s s HIGH SPEED: fMAX = 180 MHz (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC = 3V LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.3 V (TYP.) at VCC = 3.3V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 3.6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 174 IMPROVED LATCH-UP IMMUNITY M (Micro Package) T (TSSOP Package) ORDER CODES : 74LVX174M 74LVX174T Information signals applied to D inputs are transfered to the Q outputs on the positive going edge of the clock pulse. When the CLEAR input is held low, the Q outputs are held low independently of the other inputs . Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. It has better speed performance at 3.3V than 5V LS-TTL family combined with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. DESCRIPTION The LVX174 is a low voltage CMOS HEX D-TYPE FLIP FLOP WITH CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. PIN CONNECTION AND IEC LOGIC SYMBOLS April 1999 1/10 74LVX174 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2, 5, 7, 10, 12, 15 3, 4, 6, 11, 13, 14 9 8 16 SYMBOL CLEAR Q0 to Q5 D0 to D5 CLOCK GND VCC NAME AND FUNCT ION Asyncronous Master Reset (Active LOW) Flip-Flop Outputs Data Inputs Clock Input (LOW-to-HIGH, Edge- Triggered) Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS CL EAR L H H H X:Don't Care OUT PUT S CLO CK X Q L L H Qn F UNCTIO N CLEAR D X L H X NO CHANGE LOGIC DIAGRAM Thislogic diagram has notbe used to esimate propagation delays 2/10 74LVX174 ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7.0 -0.5 to 7.0 -0.5 to VCC + 0.5 - 20 20 25 50 -65 to +150 300 Unit V V V mA mA mA mA o o ICC or IGND DC VCC or Ground Current C C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top dt/dv Supply Voltage (note 1) Input Voltage Output Voltage Operating Temperature: Input Rise and Fall Time (VCC = 3V) (note 2) Parameter Valu e 2 to 3.6 0 to 5.5 0 to VCC -40 to +85 0 to 100 Unit V V V o C ns/V 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2V 3/10 74LVX174 DC SPECIFICATIONS Symb ol Parameter V CC (V) VIH High Level Input Voltage 2.0 3.0 3.6 VIL Low Level Input Voltage 2.0 3.0 3.6 VOH High Level Output Voltage 2.0 3.0 3.0 VOL Low Level Output Voltage 2.0 3.0 3.0 II ICC Input Leakage Current Quiescent Supply Current 3.6 3.6 VI = V IH or V IL VI(*) = VIH or VIL (* ) Test Co nditions Min. 1.5 2.0 2.4 T yp. Valu e T A = 25 oC Max. -40 to 85 o C Min. 1.5 2.0 2.4 0.5 0.8 0.8 0.5 0.8 0.8 1.9 2.9 2.48 0.0 0.0 0.1 0.1 0.36 0.1 4 0.1 0.1 0.44 1 40 Max. Un it V V I O =-50 A IO=-50 A IO=-4 mA IO=50 A IO=50 A IO=4 mA 1.9 2.9 2.58 2.0 3.0 V V A A VI = 5V or GND VI = VCC or GND (*) All outputs loaded. DYNAMIC SWITCHING CHARACTERISTICS Symb ol Parameter V CC (V) VOLP VOLV VIHD VILD Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) 3.3 -0.8 3.3 3.3 C L = 50 pF 0.8 Test Co nditions o Valu e T A = 25 C Min. T yp. 0.3 -0.3 2 Max. 0.8 -40 to 85 C Min. Max. o Un it V 1) Worst case package 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND 3) max number of data inputs (n) switching. (n-1) switching 0V to3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD). f=1MHz 4/10 74LVX174 AC ELECTRICAL CHARACTERISTICS (Input t r = tf =3 ns) Symb ol Parameter V CC (V) tPLH tPHL Propagation Delay Time CK to Q 2.7 2.7 3.3(*) 3.3(*) 2.7 2.7 3.3(*) 3.3(*) 2.7 3.3 2.7 (*) T est Con ditio n CL (p F) 15 50 15 50 15 50 15 50 Valu e T A = 25 oC -40 to Min. T yp. Max. Min. 7.6 14.5 1.0 10.1 18.0 1.0 5.9 8.4 7.9 10.4 6.2 8.7 6.5 5.0 6.5 5.0 7.5 5.0 0.0 0.0 4.5 3.0 130 60 180 95 0.5 0.5 1.0 1.0 9.3 12.8 15.0 18.5 9.7 13.2 1.0 1.0 1.0 1.0 1.0 1.0 Un it 85 o C Max. 17.5 21.0 11.0 14.5 18.5 22.0 11.5 15.0 7.5 5.0 7.5 5.0 8.5 6.0 0.0 0.0 4.5 3.0 ns tPLH tPHL Propagation Delay Time CLR to Q ns twL tw ts th tREM fMAX CLR pulse Width, HIGH CK pulse Width Setup Time Q to CK HIGH or LOW Hold Time Q to CK HIGH or LOW Recovery Time CLR to Q Maximum Clock Frequency ns ns ns ns ns 3.3(*) 2.7 3.3(*) 2.7 3.3(*) 2.7 3.3(*) 2.7 2.7 3.3(*) 3.3 2.7 3.3 (*) 15 50 15 50 50 50 65 45 115 65 55 40 95 55 1.5 1.5 MHz tOSLH tOSHL Output to Output Skew Time (note 1, 2) ns (*) 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the same direction, either HIGH or LOW 2) Parameter guaranteed by design (*) Voltage range is 3.3V 0.3V CAPACITIVE CHARACTERISTICS Symb ol Parameter V CC (V) C IN CPD Input Capacitance Power Dissipation Capacitance (note 1) 3.3 3.3 fIN = 10 MHz Test Co nditions Min. T yp. 5 23 Valu e T A = 25 oC Max. -40 to 85 o C Min. Max. pF pF Un it 1) CPD isdefined as the value of the IC'sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD * VCC * fIN + ICC/n(per circuit) 5/10 74LVX174 TEST CIRCUIT CL = 50 pF or equivalent (includes jigand probe capacitance) RT = ZOUT of pulse generator (typically 50) WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/10 74LVX174 WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle) WAVEFORM 3: RECOVERY TIME (f=1MHz; 50% duty cycle) 7/10 74LVX174 SO-16 MECHANICAL DATA DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm TYP. MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.004 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010 P013H 8/10 74LVX174 TSSOP16 MECHANICAL DATA mm MIN. A A1 A2 b c D E E1 e K L 0o 0.50 0.05 0.85 0.19 0.09 4.9 6.25 4.3 5 6.4 4.4 0.65 BSC 4o 0.60 8o 0.70 0o 0.020 0.10 0.9 TYP. MAX. 1.1 0.15 0.95 0.30 0.20 5.1 6.5 4.48 0.002 0.335 0.0075 0.0035 0.193 0.246 0.169 0.197 0.252 0.173 0.0256 BSC 4o 0.024 8o 0.028 0.004 0.354 MIN. inch TYP. MAX. 0.433 0.006 0.374 0.0118 0.0079 0.201 0.256 0.176 DIM. A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 9/10 74LVX174 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com . 10/10 |
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