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HIGH SPEED 3.3V (4K X 9) SYNCHRONOUS DUAL-PORT RAM
Features
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IDT70V914S
x
x
x
High-speed clock-to-data output times - Commercial: 20/25ns (max.) - Industrial: 20/25ns (max.) Low-power operation - IDT70V914S Active: 250 mW (typ.) Standby: 10 mW (typ.) Architecture based on Dual-Port RAM cells - Allows full simultaneous access from both ports Synchronous operation - 5ns setup to clock, 1ns hold on all control, data, and address inputs
x x x x
x
- Data input, address, and control registers - Fast 20ns clock to data out - Self-timed write allows fast cycle times - 20ns cycle times, 50MHz operation LVTTL-compatible, single 3.3V (+ 0.3V) power supply Clock Enable feature Guaranteed data output hold times Available in an 80-pin TQFP Industrial temperature range (-40C to +85C) is available
Functional Block Diagram
REGISTER REGISTER
I/O0-8L
WRITE LOGIC
MEMOR MEMORY Y ARRAY ARRAY
WRITE LOGIC
I/O0-8R
SENSE SENSE AMPS DECODER DECODER AMPS
OEL CLKL CLKENL
Selftimed Write Logic
REG en
REG en
OER CLKR CLKENR
Selftimed Write Logic
R/WL CEL
REG
REG
R/WR CER
5616 drw 01
A0L - A11L
A0R - A11R
JANUARY 2001
1
(c)2000 Integrated Device Technology, Inc. DSC-5616/2
IDT70V914S High-Speed 3.3V (4K x 9) Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70V914 is a high-speed 4K x 9 bit synchronous Dual-Port RAM. The memory array is based on Dual-Port memory cells to allow simultaneous access from both ports. Registers on control, data, and address inputs provide low set-up and hold times. The timing latitude provided by this approach allow systems to be designed with very short cycle times. With an input data register, this device has been optimized for applications having unidirectional data flow or bi-directional data flow in bursts. The IDT70V914 utilizes a 9-bit wide data path to allow for parity at the user's option. This feature is especially useful in data communication applications where it is necessary to use a parity bit for transmission/ reception error checking. Fabricated using IDT's CMOS high-performance technology, these Dual-Ports typically operate on only 250mW of power at maximum highspeed clock-to-data output times as fast as 20ns. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. The IDT70V914 is packaged in an 80-pin TQFP.
Pin Configurations(1,2,3)
Reference
N/C A6L A7L A8L A9L A10L A11L N/C OEL N/C VCC R/WL N/C N/C CEL GND I/O8L I/O7L I/O6L N/C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
N/C N/C A5L A4L A3L A2L A1L A0L CLKENL CLKL CLKR CLKENR A0R A1R A2R A3R A4R A5R A6R N/C
IDT70V914PF PN80-1(4) 80-Pin TQFP Top View(5) N/C A7R A8R A9R A10R A11R N/C OER N/C GND GND R/WR N/C N/C CER GND I/O8R I/O7R I/O6R N/C
,
3490 drw 02
NOTES: 1. All VCC pins must be connected to power supply. 2. All ground pins must be connected to ground supply. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
N/C N/C I/O5L VCC I/O4L I/O3L I/O2L I/O1L I/O0L GND GND I/O0R I/O1R I/O2R I/O3R VCC I/O4R I/O5R N/C N/C
6.42 2
IDT70V914S High-Speed 3.3V (4K x 9) Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol VTERM(2) VTERM(2) TBIAS TSTG IOUT Rating Terminal Voltage with Respect to GND Terminal Voltage Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial -0.5 to +4.6 -0.5 to VCC -55 to +125 -65 to +150 50 Unit V V
o
Maximum Operating Temperature and Supply Voltage(1,2)
Grade Commercial Industrial Ambient Temperature 0 C to +70 C -40 C to +85 C
O O O O
GND 0V 0V
VCC 3.3V 0.3 3.3V 0.3
5616 tbl 02
C C
NOTES: 1. This is the parameter TA. This is the "instant on" case temperature.
o
mA
5616 tbl 01
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
Recommended DC Operating Conditions
Sym bol VCC GND VIH VIL Param eter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 3.0 0 2.2 -0.3
(1)
Typ. 3.3 0
____
Max. 3.6 0 VCC+0.3 0.8
(2)
Unit V V V V
5616 tbl 03
____
Capacitance
(TA = +25C, f = 1.0MHz)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance
TQFP Only
Conditions VIN = 3dV VOUT = 3dV
Max. 8 9
Unit pF pF
5616 tbl 04
NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed VCC + 0.3V.
NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 3.3V 0.3)
70V914S Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current
(1)
Test Conditions VCC = 3.6V, VIN = 0V to VCC CE = VIH, VOUT = 0V to VCC IOL = +4mA IOH = -4mA
Min.
___
Max. 10 10 0.4
___
Unit A A V V
5616 tbl 05
Output Leakage Current Output Low Voltage Output High Voltage
___ ___
2.4
NOTE: 1. At VCC < 2.0V, input leakages are undefined
3 6.42
IDT70V914S High-Speed 3.3V (4K x 9) Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4) (VCC = 3.3V 0.3V)
70V914S20 Com'l & Ind Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - All CMOS Level Inputs) Full Standby Current (One Port - All CMOS Level Inputs) Test Condition CEL and CER = VIL, Outputs Disabled f = fMAX(1) CEL and CER = VIH f = fMAX(1) CE"A" = VIL and CE"B" = VIH(3) Active Port Outputs Disabled, f=fMAX(1) Both Ports CER and CEL > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(2) CE"A" < 0.2V and CE"B" > VCC - 0.2V(3) VIN > VCC - 0.2V or VIN < 0.2V, Active Port Outputs Disabled f = fMAX(1) Version COM'L IND COM'L IND COM'L IND COM'L IND COM'L IND Typ.(2) 80 80 30 30 55 55 3 3 55 55 Max. 140 200 55 85 85 100 15 15 85 100 70V914S25 Com'l & Ind Typ.(2) 75 75 25 25 45 45 3 3 45 45 Max. 130 190 50 80 80 95 15 15 80 95 mA mA mA mA Unit mA
ISB1
ISB2
ISB3
ISB4
NOTES: 1. At fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. Vcc = 3.3V, TA = 25C for Typ, and are not production tested. ICC DC = 150mA (Typ).
5616 tbl 06
6.42 4
IDT70V914S High-Speed 3.3V (4K x 9) Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns Max. 1.5V 1.5V Figures 1,2 and 3
5616 tbl 07
3.3V
3.3V
540 DATAOUT 435 30pF DATAOUT 435
540
5pF*
5616 drw 03
5616 drw 04
Figure 1. AC Output Test load.
Figure 2. Output Test Load (For tCKLZ, tCKHZ, tOLZ, and tOHZ) *Including scope and jig.
8 7 6 tCD (Typical, ns) 5 4 3 2 1 0 -1
- 9pF is the I/O capacitance of this device, and 30pF is the AC Test Load Capacitance
20 40 60 80 100 120 140 160 180 200 Capacitance (pF)
5616 drw 05
,
Figure 3. Typical Output Derating (Lumped Capacitive Load).
5 6.42
IDT70V914S High-Speed 3.3V (4K x 9) Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)
(Commercial: VCC = 3.3V 0.3V)
70914S20 Com'l & Ind Symbol tCYC tCH tCL tCD tS tH tDC tCKLZ tCKHZ tOE tOLZ tOHZ tSCK tHCK Clock Cycle Time Clock High Time Clock Low Time Clock High to Output Valid Registered Signal Set-up Time Registered Signal Hold Time Data Output Hold After Clock High Clock High to Output Low-Z(1,2) Clock High to Output High-Z
(1,2)
70914S25 Com'l & Ind Min. 25 10 10
____
Parameter
Min. 20 8 8
____
Max.
____ ____ ____
Max.
____ ____ ____
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
20
____ ____ ____ ____
25
____ ____ ____ ____
5 1 3 2
____ ____
6 1 3 2
____ ____
9 10
____
12 12
____
Output Enable to Output Valid Output Enable to Output Low-Z(1,2) Output Disable to Output High-Z(1,2) Clock Enable, Disable Set-up Time Clock Enable, Disable Hold Time
0
____
0
____
9
____ ____
11
____ ____
5 2
6 2
Port-to-Port Delay tCWDD tCSS Write Port Clock Hig h to Read Data Delay Clock-to-Clock Setup Time
____ ____
35 15
____ ____
45 20
ns ns
5616 tbl 08
NOTES: 1. Transition is measured 0mV from Low or High impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested.
6.42 6
IDT70V914S High-Speed 3.3V (4K x 9) Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle, Either Side
tCYC CLK tCH tCL tSCK CLKEN tS CE tH tHCK tSCK
R/W
ADDRESS
An tCD
An + 1 tDC Qn tCKLZ (1)
An + 2
An + 3 tCKHZ (1)
DATAOUT
Qn + 1 tOHZ
(1)
Qn + 1 tOLZ tOE
5616 drw 06 (1)
OE
Timing Waveform of Write with Port-to-Port Read(2,3,4)
CLK "A"
R/W "A"
ADDR "A"
MATCH
NO MATCH
DATA IN "A"
VALID
tCCS CLK "B"
(5)
tCD R/W "B"
ADDR "B"
MATCH
NO MATCH
tCWDD DATA OUT "B"
VALID
tCD
VALID
tDC
5616 drw 07
NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. CEL = CER = VIL, CLKENL = CLKENR = VIL. 3. OE = VIL for the reading port, port 'B'. 4. All timing is the same for left and right ports. Ports "A" may be either the left or right port. Port "B" is opposite from port "A". 5. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD. tCWDD does not apply in this case.
7 6.42
IDT70V914S High-Speed 3.3V (4K x 9) Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read-to-Write Cycle No. 1(1,2) (tCYC = min.)
tCYC CLK CLKEN tS CE
(1)
tCYC tCL tCH tCL
tCH
tH
R/W
ADDRESS
An
An + 1
An + 1
(1)
An + 2
DATAIN tCD DATAOUT tCKLZ (3) Qn tCKHZ (3)
Dn + 1
(1)
Dn + 2
5616 drw 08
Timing Waveform of Read-to-Write Cycle No. 2(4) (tCYC > min.)
tCYC CLK CLKEN tS CE tH tCH
(4)
tCL
R/W
ADDRESS
An
An + 1
DATAIN tCD DATAOUT tCKLZ OE
(3)
Dn + 1
Qn tOHZ
5616 drw 09
NOTES: 1. For tCYC = min.; data out coincident with the rising edge of the subsequent write clock can occur. To ensure writing to the correct address location, the write must be repeated on the second write clock rising edge. If CE = VIL, invalid data will be written into array. The An+1 must be rewritten on the following cycle. 2. OE LOW throughout. 3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 4. For tCYC > min.; OE may be used to avoid data out coincident with the rising edge of the subsequent write clock. Use of OE will eliminate the need for the write to be repeated.
6.42 8
IDT70V914S High-Speed 3.3V (4K x 9) Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Functional Description
The IDT70V914 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide very short set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. The internal write pulse width is dependent on the LOW to HIGH transitions of the clock signal allowing the shortest possible realized cycle times. Clock enable inputs are provided to stall the operation of the address and data input registers without introducing clock skew for very fast interleaved memory applications. A HIGH on the CE input for one clock cycle will power down the internal circuitry to reduce static power consumption.
Truth Table I: Read/Write Control(1)
Inputs Synchronous CLK CE H L L X
(3)
Outputs Asynchronous OE X X L H I/O0-8 High-Z DATAIN DATAOUT High-Z Deselected, Power-Down Selected and Write Enabled Read Selected and Data Output Enable Read Outputs Disabled
5616 tbl 09
R/W X L H X
Mode
Truth Table II: Clock Enable Function Table(1)
Inputs Mode Load "1" Load "0" Hold (do nothing) CLK(3) X CLKEN(2) L L H H Register Inputs ADDR H L X X DATAIN H L X X Register Outputs(4) ADDR H L NC NC DATAOUT H L NC NC
5616 tbl 10
NOTES: 1. 'H' = HIGH voltage level steady state, 'h' = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'L' = LOW voltage level steady state 'l' = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'X' = Don't care, 'NC' = No change 2. CLKEN = VIL must be clocked in during Power-Up. 3. Control signals are initialted and terminated on the rising edge of the CLK, depending on their input level. When R/W and CE are LOW, a write cycle is initiated on the LOW-to-HIGH transition of the CLK. Termination of a write cycle is done on the next LOW-to-HIGH transistion of the CLK. 4. The register outputs are internal signals from the register inputs being clocked in or disabled by CLKEN.
9 6.42
IDT70V914S High-Speed 3.3V (4K x 9) Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range
Blank I
Commercial (0C to +70C) Industrial (-40C to +85C)
PF
80-pin TQFP (PN80-1)
20 25
Commercial & Industrial Commercial & Industrial
Speed in nanoseconds
S
Standard Power
70V914 36K (4K x 9-Bit) 3.3V Synchronous Dual-Port RAM
5616 drw 10
Datasheet Document History
1/20/00: 1/10/01: Initial Public Offering Page 1 Fixed AL and AR numbers in drawing Page 4 Increased storage temperature parameter Clarified TA parameter Page 5 DC Electrical parameters-changed wording from "open" to "disabled" Changed 200mV to 0mV in notes
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
6.42 10
for Tech Support: 831-754-4613 DualPortHelp@idt.com
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