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INTEGRATED CIRCUITS
74F841/842/843/845/846 Bus interface latches
Product specification
Replaces datasheet 74F841/842/843/844/845/846 of 1999 Jan 08
1999 Jun 23
IC15 Data Handbook
Philips Semiconductors
Philips Semiconductors
Product specification
Bus interface latches
74F841/74F842/74F843/ 74F845/74F846
74F841/74F842 10-bit bus interface latches, non-inverting/inverting (3-State) 74F843 9-bit bus interface latch, non-inverting (3-State) 74F845/74F846 8-bit bus interface latches, non-inverting/inverting (3-State)
FEATURES
* High speed parallel latches * Extra data width for wide address/data paths or buses carrying
parity
DESCRIPTION
The 74F841-74F846 bus interface latch series are designed to provide extra data width for wider address/data paths of buses carrying parity. The 74F841-74F846 series are funcitonally an pin compatible to the AMD AM29841-AM29846 series. The 74F841 consists of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is High. This allows asynchronous operation, as the output transition follows the data in transition. On the LE High-to-Low transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable (OE) is Low. When OE is High the output is in the High-impedance state. The 74F842 is the inverted output version of the 74F841. The 74F843 consists of nine D-type latches with 3-State outputs. In addition to the LE and OE pins, the 74F843 has a Master Reset (MR) pin and Preset (PRE) pin. These pins are ideal for parity bus interfacing in high performance systems. When MR is Low, the outputs are Low if OE is Low. When MR is High, data can be entered into the latch. When PRE is Low, the outputs are High, if OE is Low, PRE overrides MR. The 74F845 consists of eight D-type latches with 3-State outputs. In addition to the LE, OE, MR and PRE pins, the 74F845 has two addtitional OE pins making a total of three Output Enables (OE0, OE1, OE2) pins. The multiple Ouptut Enables (OE0, OE1, OE2) allow multi-user control of the interface, e.g., CS, DMA, and RD/WR. The 74F846 is the inverted output version of the 74F845.
* High impedance NPN base input structure minimizes bus loading * IIL is 20A vs 1000A for AM29841 series * Buffered control inputs to reduce AC effects * Ideal where high speed, light loading, or increased fan-in are
required as with MOS microprocessors
* Positive and negative over-shoots are clamped to ground * 3-State outputs glitch free during power-up and power-down * 48mA sink current * Slim dual in-line 300 mil package * Broadside pinout * Pin-for-pin and function compatible with AMD AM29841-846
series
TYPE 74F841, 74F842 74F843, 74F845 74F846
TYPICAL PROPAGATION DELAY 5.5ns 5.5ns 6.2ns
TYPICAL SUPPLY CURRENT (TOTAL) 60mA 75mA 60mA
ORDERING INFORMATION
PACKAGES 24-pin plastic Slim DIP (300 mil) 24-pin plastic SOL COMMERCIAL RANGE VCC = 5V10%; Tamb = 0C to +70C N74F841N, N74F842N, N74F843N, N74F845N, N74F846N N74F841D, N74F842D, N74F843D, N74F845D, N74F846D PACKAGE DRAWING NUMBER SOT222-1 SOT137-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS Dn LE OE, OEn MR PRE Qn Qn Data inputs Latch Enable input Output Enable input (active Low) Master Reset input (active Low) Preset input (active Low) Data outputs Data outputs DESCRIPTION 74F(U.L.) HIGH/LOW 1.0/0.033 1.0/0.033 1.0/0.033 1.0/0.033 1.0/0.033 1200/80 1200/80 LOAD VALUE HIGH/LOW 20A/20A 20A/20A 20A/20A 20A/20A 20A/20A 24mA/48mA 24mA/48mA
NOTE: One (1.0) FAST Unit Load is defined as: 20A in the High state and 0.6mA in the Low state.
1999 Jun 23
2
853-1208 21851
Philips Semiconductors
Product specification
Bus interface latches
74F841/74F842/74F843/ 74F845/74F846
PIN CONFIGURATION for 74F841
OE 1 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 24 VCC 23 Q0 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 Q9 13 LE
PIN CONFIGURATION for 74F842
OE 1 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 24 VCC 23 Q0 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 Q9 13 LE
D8 10 D9 11 GND 12
D8 10 D9 11 GND 12
SF01279
SF01282
LOGIC SYMBOL for 74F841
2 3 4 5 6 7 8 9 10 11
LOGIC SYMBOL for 74F842
2 3 4 5 6 7 8 9 10 11
D0 13 1 LE OE Q0
D1
D2
D3
D4
D5
D6
D7
D8
D9 13 1 LE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
23 VCC = Pin 24 GND = Pin 12
22
21
20
19
18
17
16
15
14
23 VCC = Pin 24 GND = Pin 12
22
21
20
19
18
17
16
15
14
SF01280
SF01283
LOGIC SYMBOL (IEEE/IEC) for 74F841
1 13 EN C1
LOGIC SYMBOL (IEEE/IEC) for 74F842
1 13 EN C1
2 3 4 5 6 7 8 9 10 11
1D
23 22 21 20 19 18 17 16 15 14
2 3 4 5 6 7 8 9 10 11
1D
23 22 21 20 19 18 17 16 15 14
SF01281
SF01284
1999 Jun 23
3
Philips Semiconductors
Product specification
Bus interface latches
74F841/74F842/74F843/ 74F845/74F846
PIN CONFIGURATION for 74F843
OE 1 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 24 VCC 23 Q0 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 PRE 13 LE
D8 10 MR 11 GND 12
SF01285
LOGIC SYMBOL for 74F843
2 3 4 5 6 7 8 9 10
13 14 11 1
LE PRE MR OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
23 VCC = Pin 24 GND = Pin 12
22
21
20
19
18
17
16
15
SF01286
LOGIC SYMBOL (IEEE/IEC) for 74F843
1 11 14 S2 13 C1 23 22 21 20 19 18 17 16 15 EN R
2 3 4 5 6 7 8 9 10
1D
SF01287
1999 Jun 23
4
Philips Semiconductors
Product specification
Bus interface latches
74F841/74F842/74F843/ 74F845/74F846
PIN CONFIGURATION for 74F845
OE0 OE1 D0 D1 D2 D3 D4 D5 D6 1 2 3 4 5 6 7 8 9 24 VCC 23 OE2 22 Q0 21 Q1 20 Q2 19 Q3 18 Q4 17 Q5 16 Q6 15 Q7 14 PRE 13 LE
PIN CONFIGURATION for 74F846
OE0 OE1 D0 D1 D2 D3 D4 D5 D6 1 2 3 4 5 6 7 8 9 24 VCC 23 OE2 22 Q0 21 Q1 20 Q2 19 Q3 18 Q4 17 Q5 16 Q6 15 Q7 14 PRE 13 LE
D7 10 MR 11 GND 12
D7 10 MR 11 GND 12
SF01291
SF01294
LOGIC SYMBOL for 74F845
3 4 5 6 7 8 9 10
LOGIC SYMBOL for 74F846
3 4 5 6 7 8 9 10
13 14 11 1 2 23
LE PRE MR OE0 OE1 OE2
D0
D1
D2
D3
D4
D5
D6
D7
13 14 11 1 2 23
LE PRE MR OE0 OE1 OE2
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
VCC = Pin 24 GND = Pin 12
22
21
20
19
18
17
16
15
VCC = Pin 24 GND = Pin 12
22
21
20
19
18
17
16
15
SF01292
SF01295
LOGIC SYMBOL (IEEE/IEC) for 74F845
1 2 23 14 11 13 S2 R C1 22 21 20 19 18 17 16 15
LOGIC SYMBOL (IEEE/IEC) for 74F846
1 2 23 14 11 13 S2 R C1 22 21 20 19 18 17 16 15
&
EN
&
EN
3 4 5 6 7 8 9 10
1D
3 4 5 6 7 8 9 10
1D
SF01293A
SF01296A
1999 Jun 23
5
Philips Semiconductors
Product specification
Bus interface latches
74F841/74F842/74F843/ 74F845/74F846
LOGIC DIAGRAM for 74F841
D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 D8 10 D9 11
D L Q
D L Q
D L Q
D L Q
D L Q
D L Q
D L Q
D L Q
D L Q
D L Q
C
LE
13
OE
1 23 Q0 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 Q9
VCC = Pin 24 GND = Pin 12
SF01297
LOGIC DIAGRAM for 74F842
D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 D8 10 D9 11
D L Q
D L Q
D L Q
D L Q
D L Q
D L Q
D L Q
D L Q
D L Q
D L Q
C
LE
13
OE
1 23 Q0 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 Q9
VCC = Pin 24 GND = Pin 12
SF01298
FUNCTION TABLE for 74F841 and 74F842
OUTPUTS INPUTS 74F841 OE L L L L H L H= L= h= l= = X= NC= Z= LE H H X L Dn L H l h X X Qn L H L H Z NC 74F842 Qn H Transparent L H Latched L Z NC High Impedance Hold OPERATING MODE
High voltage level Low voltage level High state one setup time before the High-to-Low LE transition Low state one setup time before the High-to-Low LE transition High-to-Low transition Don't care No change High impedance "off" state
1999 Jun 23
6
Philips Semiconductors
Product specification
Bus interface latches
74F841/74F842/74F843/ 74F845/74F846
LOGIC DIAGRAM for 74F843
D0 2 PRE 14 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 D8 10
DP L 11 13 Q
DP L Q
DP L Q
DP L Q
DP L Q
DP L Q
DP L Q
DP L Q
DP L Q
C
C
C
C
C
C
C
C
C
MR LE
OE VCC = Pin 24 GND = Pin 12
1 23 Q0 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8
SF01299
FUNCTION TABLE for 74F843
OUTPUTS INPUTS 74F843 OE L L L L L L H L H= L= h= l= = X= NC= Z= PRE L H H H H H X H MR X L H H H H X H LE X X H H X L Dn X X L H l h X X Qn H L L Transparent H L Latched H Z NC High Impedance Hold Preset Clear OPERATING MODE
High voltage level Low voltage level High state one setup time before the High-to-Low LE transition Low state one setup time before the High-to-Low LE transition High-to-Low transition Don't care No change High impedance "off" state
1999 Jun 23
7
Philips Semiconductors
Product specification
Bus interface latches
74F841/74F842/74F843/ 74F845/74F846
LOGIC DIAGRAM for 74F845
D0 3 PRE 14 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 10
DP L 11 13 1 2 23 22 Q0 Q
DP L Q
DP L Q
DP L Q
DP L Q
DP L Q
DP L Q
DP L Q
C
C
C
C
C
C
C
C
MR LE OE0 OE1 OE2 VCC = Pin 24 GND = Pin 12
21 Q1
20 Q2
19 Q3
18 Q4
17 Q5
16 Q6
15 Q7 SF01301
LOGIC DIAGRAM for 74F846
D0 3 PRE 14 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 10
DP L 11 13 1 2 23 22 Q0 Q
DP L Q
DP L Q
DP L Q
DP L Q
DP L Q
DP L Q
DP L Q
C
C
C
C
C
C
C
C
MR LE OE0 OE1 OE2 VCC = Pin 24 GND = Pin 12
21 Q1
20 Q2
19 Q3
18 Q4
17 Q5
16 Q6
15 Q7
SF01302
FUNCTION TABLE for 74F845 and 74F846
OUTPUTS INPUTS 74F845 OE L L L L L L H L H= L= h= l= = X= NC= Z= PRE L H H H H H X H MR X L H H H H X H LE X X H H X L Dn X X L H l h X X Qn H L L H L H Z NC 74F846 Qn H L H Transparent L H Latched L Z NC High Impedance Hold Preset Clear OPERATING MODE
High voltage level Low voltage level High state one setup time before the High-to-Low LE transition Low state one setup time before the High-to-Low LE transition High-to-Low transition Don't care No change High impedance "off" state 8
1999 Jun 23
Philips Semiconductors
Product specification
Bus interface latches
74F841/74F842/74F843/ 74F845/74F846
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range. SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to VCC 84 0 to +70 -65 to +150 UNIT V V mA V mA C C
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARAMETER MIN 4.5 2.0 0.8 -18 -24 48 +70 NOM 5.0 MAX 5.5 V V V mA mA mA C UNIT
1999 Jun 23
9
Philips Semiconductors
Product specification
Bus interface latches
74F841/74F842/74F843/ 74F845/74F846
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted. SYMBOL PARAMETER TEST CONDITIONS1 MIN IO = -15mA 15mA OH VO OH High-level High level output voltage VCC = MIN, , VIL = MAX, VIH = MIN IO = -24mA 24mA OH VCC = MIN, , VIL = MAX, VIH = MIN IOL = 32mA IOL = 48mA 10%VCC 5%VCC 10%VCC 5%VCC 10%VCC 5%VCC 2.2 2.2 2.0 2.0 0.38 0.38 -0.73 0.55 0.55 -1.2 100 20 -20 50 -50 -100 50 VCC = MAX 60 70 40 VCC = MAX 65 60 65 VCC = MAX 75 85 50 VCC = MAX 70 70 -225 65 80 92 60 90 90 90 100 115 70 95 95 3.3 LIMITS TYP2 UNIT MAX V V V V V V V A A A A A mA mA mA mA mA mA mA mA mA mA mA mA mA
VO OL VIK II IIH IIL IOZH IOZL IOS
Low-level Low level output voltage Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Off-state output current, High-level voltage applied Off-state output current, Low-level voltage applied Short-circuit output current3 ICCH 74F841 ICCL ICCZ ICCH 74F842 ICCL ICCZ ICCH 74F843 74F845 ICCL ICCZ ICCH 74F846 ICCL ICCZ
VCC = MIN, II = IIK VCC = 0.0V, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V VCC = MAX
ICC
Supply current y (total)
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter test, IOS tests should be performed last.
1999 Jun 23
10
Philips Semiconductors
Product specification
Bus interface latches
74F841/74F842/74F843/ 74F845/74F846
AC ELECTRICAL CHARACTERISTICS for 74F841/74F842
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay Dn to Qn 74F841 Propagation delay LE to Qn Propagation delay Dn to Qn 74F842 Propagation delay LE to Qn Output enable time High or Low-level OEn to Qn or Qn Output disable time High or Low-level OEn to Qn or Qn Waveform 1, 2 Waveform 5 Waveform 6 Waveform 5 Waveform 6 5.0 4.5 2.5 4.0 1.0 1.0 7.0 6.5 4.5 6.0 4.5 5.0 10.0 9.0 8.0 9.5 8.0 8.0 3.0 3.0 2.0 3.0 1.0 1.0 10.5 9.5 8.5 10.5 8.5 8.5 ns ns ns Waveform 1, 2 Waveform 1, 2 4.5 4.0 3.5 3.0 6.5 6.0 5.5 5.0 9.5 9.0 8.5 8.0 4.0 3.5 4.5 4.0 10.0 9.5 9.0 8.5 ns ns Waveform 1, 2 2.0 2.5 TYP 4.0 4.5 MAX 7.5 7.5 Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 2.0 2.5 MAX 8.0 8.0 ns UNIT
AC SETUP REQUIREMENTS for 74F841/74F842
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN ts(H) ts(L) th(H) th(L) tw(H) th(H) th(L) tw(H) Setup time, High or Low Dn to LE Hold time, High or Low Dn to LE LE pulse width, High Hold time, High or Low Dn to LE LE pulse width, High 74F842 Waveform 4 74F841 Waveform 4 Waveform 4 Waveform 4 Waveform 4 0.0 0.0 2.5 3.0 3.5 3.0 3.5 3.0 TYP Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 1.0 1.0 3.0 4.0 4.0 3.5 4.5 3.0 MAX ns ns ns ns ns UNIT
1999 Jun 23
11
Philips Semiconductors
Product specification
Bus interface latches
74F841/74F842/74F843/ 74F845/74F846
AC ELECTRICAL CHARACTERISTICS for 74F843/74F845
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay Dn to Qn Propagation delay LE to Qn Propagation delay PRE to Qn Propagation delay MR to Qn Output enable time High or Low-level OEn to Qn Output disable time High or Low-level OEn to Qn Waveform 1, 2 Waveform 1, 2 Waveform 3 Waveform 3 Waveform 5 Waveform 6 Waveform 5 Waveform 6 2.0 2.5 4.5 4.0 3.5 2.0 2.5 4.0 1.0 1.0 TYP 4.5 4.5 6.5 6.0 5.5 4.5 4.5 6.0 4.5 5.0 MAX 7.5 8.0 9.5 8.5 8.5 7.5 7.5 9.5 8.0 8.0 Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 2.0 2.5 4.5 4.0 3.0 2.0 2.0 3.0 1.0 1.0 MAX 8.5 8.5 10.0 8.5 9.0 8.0 8.0 10.5 8.5 8.5 ns ns ns ns ns ns UNIT
AC SETUP REQUIREMENTS for 74F843/74F845
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(H) tREC tREC Setup time, High or Low Dn to LE Hold time, High or Low Dn to LE LE pulse width, High PRE pulse width, Low MR pulse width, Low PRE recovery time MR recovery time Waveform 4 Waveform 4 Waveform 4 Waveform 3 Waveform 3 Waveform 3 Waveform 3 1.0 1.0 3.0 4.0 3.0 4.0 4.0 0.0 3.5 TYP Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 0.0 0.0 3.0 4.0 3.0 5.0 5.0 0.0 4.5 MAX ns ns ns ns ns ns ns UNIT
1999 Jun 23
12
Philips Semiconductors
Product specification
Bus interface latches
74F841/74F842/74F843/ 74F845/74F846
AC ELECTRICAL CHARACTERISTICS for 74F846
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay Dn to Qn Propagation delay LE to Qn Propagation delay PRE to Qn Propagation delay MR to Qn Output enable time High or Low-level OEn to Qn Output disable time High or Low-level OEn to Qn Waveform 1, 2 Waveform 1, 2 Waveform 3 Waveform 3 Waveform 5 Waveform 6 Waveform 5 Waveform 6 3.5 3.0 5.0 4.5 3.5 5.0 2.5 4.0 1.0 1.0 TYP 5.5 5.0 7.0 6.5 5.5 7.0 5.0 6.0 4.5 5.0 MAX 8.5 8.0 10.0 9.0 8.5 10.0 7.5 9.5 8.0 8.0 Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 3.0 3.0 5.0 4.5 3.0 4.5 2.0 3.0 1.0 1.0 MAX 9.5 8.5 10.5 9.5 9.5 10.5 8.0 10.5 8.5 8.5 ns ns ns ns ns ns UNIT
AC SETUP REQUIREMENTS for 74F846
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(H) tREC tREC Setup time, High or Low Dn to LE Hold time, High or Low Dn to LE LE pulse width, High PRE pulse width, Low MR pulse width, Low PRE recovery time MR recovery time Waveform 4 Waveform 4 Waveform 4 Waveform 3 Waveform 3 Waveform 3 Waveform 3 0.0 0.0 3.0 4.0 3.0 4.0 4.0 0.0 3.5 TYP Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 0.0 0.0 3.0 4.0 3.0 5.0 5.0 0.0 4.5 MAX ns ns ns ns ns ns ns UNIT
1999 Jun 23
13
Philips Semiconductors
Product specification
Bus interface latches
74F841/74F842/74F843/ 74F845/74F846
AC WAVEFORMS
For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
Dn, LE VM tPLH Qn VM VM tPHL VM Qn Dn, LE VM tPHL VM VM tPLH VM
SF01303
SF01304
Waveform 1.
Propagation Delay, Non-Inverting Path
Waveform 2.
Propagation Delay, Inverting Path
PRE, MR
VM
tw(L)
VM tREC
Dn
VM ts(H)
VM th(H)
VM ts(L)
VM th(L)
LE
VM
LE
VM
VM tw(H)
VM
tPLH Qn, Qn tPHL Qn, Qn VM VM
SF01306
Waveform 4.
Data Setup and Hold Times
SF01305
Waveform 3. Master Reset and Preset Pulse Width, Master Reset and Preset to Output Delay, and Master Reset and Preset to Latch Enable Recovery Time
OEn
VM tPZH
VM tPHZ VM 0V VOH -0.3V
OEn
VM tPZL
VM tPLZ VM VOL +0.3V
3.5V
Qn, Qn
Qn, Qn
SF00509
SF00510
Waveform 5. 3-State Output Enable Time to High Level and Output Disable Time from High Level
Waveform 6. 3-State Output Enable Time to Low Level and Output Disable time from Low Level
1999 Jun 23
14
Philips Semiconductors
Product specification
Bus interface latches
74F841/74F842/74F843/ 74F845/74F846
TEST CIRCUIT AND WAVEFORMS
VCC 7.0V VIN PULSE GENERATOR RT D.U.T. VOUT RL NEGATIVE PULSE 90% VM 10% tTHL (tf ) CL RL tTLH (tr ) 90% POSITIVE PULSE 10% tTHL (tf ) AMP (V) 90% VM tw 10% 0V tw VM 10% tTLH (tr ) 0V AMP (V)
90%
Test Circuit for 3-State Outputs SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open
VM
Input Pulse Definition
DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00777
1999 Jun 23
15
Philips Semiconductors
Product specification
Bus interface latches
74F841/74F842/74F843/ 74F845/74F846
DIP24: plastic dual in-line package; 24 leads (300 mil)
SOT222-1
1999 Jun 23
16
Philips Semiconductors
Product specification
Bus interface latches
74F841/74F842/74F843/ 74F845/74F846
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
1999 Jun 23
17
Philips Semiconductors
Product specification
Bus interface latches
74F841/74F842/74F843/ 74F845/74F846
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 06-99 Document order number: 9397 750 06143
Philips Semiconductors
1999 Jun 23 18

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