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74VCX16373 Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs
October 1997 Revised November 2001
74VCX16373 Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs
General Description
The VCX16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear to be transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. The 74VCX16373 is designed for low voltage (1.4V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The 74VCX16373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
Features
I 1.4V to 3.6V VCC supply operation I 3.6V tolerant inputs and outputs I tPD (In to On) 3.0 ns max for 3.0V to 3.6V VCC I Power-off high impedance inputs and outputs I Support live insertion and withdrawal (Note 1) I Static Drive (IOH/IOL)
24 mA @ 3.0V VCC
I Uses patented noise/EMI reduction circuitry I Latch-up performance exceeds 300 mA I ESD performance: Human body model > 2000V Machine model > 200V I Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary)
Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number 74VCX16373GX (Note 2) 74VCX16373MTD (Note 3) Package Number BGA54A (Preliminary) MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: BGA package available in Tape and Reel only. Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
(c) 2001 Fairchild Semiconductor Corporation
DS500065
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74VCX16373
Connection Diagrams
Pin Assignment for TSSOP
Pin Descriptions
Pin Names OEn LEn I0-I15 O0-O15 NC Description Output Enable Input (Active LOW) Latch Enable Input Inputs Outputs No Connect
FBGA Pin Assignments
1 A B C D E F G H J O0 O2 O4 O6 O8 O10 O12 O14 O15 2 NC O1 O3 O5 O7 O9 O11 O13 NC 3 OE1 NC VCC GND GND GND VCC NC OE2 4 LE1 NC VCC GND GND GND VCC NC LE2 5 NC I1 I3 I5 I7 I9 I11 I13 NC 6 I0 I2 I4 I6 I8 I10 I12 I14 I15
Truth Tables
Inputs LE1 X H Pin Assignment for FBGA H L OE1 H L L L Inputs LE2 X H H L OE2 H L L L I8-I15 X L H X I0-I7 X L H X Outputs O0-O7 Z L H O0 Outputs O8-O15 Z L H O0
(Top Thru View)
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance O0 = Previous O0 before HIGH-to-LOW of Latch Enable
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74VCX16373
Functional Description
The 74VCX16373 contains sixteen edge D-type latches with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the In enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its I input changes. When LEn is LOW, the latches store information that was present on the I inputs a setup time preceding the HIGH-to-LOW transition on LEn. The 3-STATE outputs are controlled by the Output Enable (OEn) input. When OEn is LOW the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74VCX16373
Absolute Maximum Ratings(Note 4)
Supply Voltage (VCC ) DC Input Voltage (VI) Output Voltage (VO) Outputs 3-STATED Outputs Active (Note 5) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V VO > VCC DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (ICC or GND) Storage Temperature Range (TSTG)
-0.5V to +4.6V -0.5V to +4.6V -0.5V to +4.6V -0.5V to VCC +0.5V -50 mA -50 mA +50 mA 50 mA 100 mA -65C to +150C
Recommended Operating Conditions (Note 6)
Power Supply Operating Input Voltage Output Voltage (VO) Output in Active States Output in "OFF" State Output Current in IOH/IOL VCC = 3.0V to 3.6V VCC = 2.3V to 2.7V VCC = 1.65V to 2.3V VCC = 1.4V to 1.6V Free Air Operating Temperature (TA) Minimum Input Edge Rate (t/V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V
Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Floating or unused inputs must be held HIGH or LOW.
1.4V to 3.6V
-0.3V to +3.6V
0V to VCC 0.0V to 3.6V
24 mA 18 mA 6 mA 2 mA -40C to +85C
DC Electrical Characteristics
Symbol VIH Parameter HIGH Level Input Voltage Conditions VCC (V) 2.7 - 3.6 2.3 - 2.7 1.65 - 2.3 1.4 - 1.6 VIL LOW Level Input Voltage 2.7-3.6 2.3-2.7 1.65-2.3 1.4 - 1.6 VOH HIGH Level Output Voltage IOH = -100 A IOH = -12 mA IOH = -18 mA IOH = -24 mA IOH = -100 A IOH = -6 mA IOH = -12 mA IOH = -18 mA IOH = -100 A IOH = -6 mA IOH = -100 A IOH = -2 mA 2.7-3.6 2.7 3.0 3.0 2.3-2.7 2.3 2.3 2.3 1.65-2.3 1.65 1.4 - 1.6 1.4 VCC - 0.2 2.2 2.4 2.2 VCC - 0.2 2.0 1.8 1.7 VCC - 0.2 1.25 VCC - 0.2 1.05 V Min 2.0 1.6 0.65 x VCC 0.65 x VCC 0.8 0.7 0.35 x VCC 0.35 x VCC V V Max Units
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74VCX16373
DC Electrical Characteristics
Symbol VOL Parameter LOW Level Output Voltage
(Continued)
VCC (V) 2.7-3.6 2.7 3.0 3.0 2.3-2.7 2.3 2.3 1.65-2.3 1.65 1.4 - 1.6 1.4 1.4-3.6 1.4-3.6 0 1.4-3.6 1.4-3.6 2.7-3.6
Conditions IOL = 100 A IOL = 12 mA IOL = 18 mA IOL = 24 mA IOL = 100 A IOL = 12 mA IOL = 18 mA IOL = 100 A IOL = 6 mA IOL = 100 A IOL = 2 mA
Min
Max 0.2 0.4 0.4 0.55 0.2 0.4 0.6 0.2 0.3 0.2 0.35 5.0 10 10 20 20 750
Units
V
II IOZ IOFFI ICC ICC
Input Leakage Current 3-STATE Output Leakage Power-OFF Leakage Current Quiescent Supply Current Increase in ICC per Input
0 VI 3.6V 0 VO 3.6V VI = V IH or VIL 0 (VI, VO) 3.6V VI = V CC or GND VCC (VI, VO) 3.6V (Note 7) VIH = VCC -0.6V
A A A A A
Note 7: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
Symbol tPHL, tPLH Parameter Propagation Delay LE to On
(Note 8)
Conditions VCC (V) 3.3 0.3 2.5 0.2 1.8 0.15 TA = -40C to +85C, Min 0.8 1.0 1.5 1.0 0.8 1.0 1.5 1.0 0.8 1.0 1.5 1.0 0.8 1.0 1.5 1.0 1.5 1.5 2.5 3.0 1.0 1.0 1.0 1.2 ns Figures 6, 7 ns Figures 1, 6 ns Figures 6, 7 ns Figures 1, 6 Max 3.0 3.9 7.8 15.6 3.0 3.4 6.8 13.6 3.5 4.6 9.2 18.4 3.5 3.8 6.8 13.6 ns Figures 7, 9, 10 ns Figures 1, 3, 4 ns Figures 7, 9, 10 ns Figures 1, 3, 4 ns Figures 7, 8 ns Figures 1, 2 ns Figures 7, 8 ns Figures 1, 2 Units Figure Number
CL = 30 pF, RL = 500
CL = 15 pF, RL = 2k tPHL, tPLH Propagation Delay In to On CL = 30 pF, RL = 500
1.5 0.1 3.3 0.3 2.5 0.2 1.8 0.15
CL = 15 pF, RL = 2k tPZL, tPZH Output Enable Time CL = 30 pF, RL = 500
1.5 0.1 3.3 0.3 2.5 0.2 1.8 0.15
CL = 15 pF, RL = 2k tPLZ, tPHZ Output Disable Time CL = 30 pF, RL = 500
1.5 0.1 3.3 0.3 2.5 0.2 1.8 0.15
CL = 15 pF, RL = 2k TS Setup Time CL = 30 pF, RL = 500
1.5 0.1 3.3 0.3 2.5 0.2 1.8 0.15
CL = 15 pF, RL = 2k TH Hold Time CL = 30 pF, RL = 500
1.5 0.1 3.3 1.0 2.5 0.2 1.8 0.15
CL = 15 pF, RL = 2k
1.5 0.1
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74VCX16373
AC Electrical Characteristics
Symbol TW Pulse Width Parameter
(Continued)
VCC (V) 3.3 0.3 2.5 0.2 1.8 0.15 TA = -40C to +85C, Min 1.5 1.5 4.0 4.0 0.5 0.5 0.75 1.5 ns ns Figures 4, 7 ns Figures 1, 4 Max
Conditions CL = 30 pF, RL = 500
Units
Figure Number
CL = 15 pF, RL = 2k tOSHL tOSLH Output to Output Skew (Note 9) CL = 15 pF, RL = 2k
Note 8: For CL = 50PF, add approximately 300 ps to the AC maximum specification.
1.5 0.1 3.3 0.3 2.5 0.2 1.8 0.15 1.5 0.1
CL = 30 pF, RL = 500
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol VOLP Parameter Quiet Output Dynamic Peak VOL Conditions CL = 30 pF, VIH = VCC, VIL = 0V VCC (V) 1.8 2.5 3.3 VOLV Quiet Output Dynamic Valley VOL CL = 30 pF, VIH = VCC, VIL = 0V 1.8 2.5 3.3 VOHV Quiet Output Dynamic Valley VOH CL = 30 pF, VIH = VCC, VIL = 0V 1.8 2.5 3.3 TA = +25C Typical 0.25 0.6 0.8 -0.25 -0.6 -0.8 1.5 1.9 2.2 V V V Units
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter Conditions VCC = 1.8V, 2.5V or 3.3V, VI = 0V or VCC VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V VI = 0V or VCC, f = 10 MHz, VCC = 1.8V, 2.5V or 3.3V TA = +25C Typical 6 7 20 Units pF pF pF
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74VCX16373
AC Loading and Waveforms (VCC 3.3V 0.3V to 1.8V 0.15V)
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
SWITCH Open 6V at VCC = 3.3 0.3V; VCC x 2 at VCC = 2.5 0.2V; 1.8V 0.15V GND FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output HIGH Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output LOW Enable and Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and trec Waveforms Symbol Vmi Vmo VX VY
FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic VCC
3.3V 0.3V 1.5V 1.5V VOL + 0.3V VOH - 0.3V
2.5V 0.2V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V
1.8V 0.15V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V
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74VCX16373
AC Loading and Waveforms (VCC 1.5 0.1V)
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
SWITCH Open VCC x 2 at VCC = 1.5 0.1V GND FIGURE 7. AC Test Circuit
FIGURE 8. Waveform for Inverting and Non-Inverting Functions
FIGURE 9. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 10. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
Symbol Vmi Vmo VX VY
VCC 1.5V 0.1V VCC/2 VCC/2 VOL + 0.1V VOH - 0.1V
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74VCX16373
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A (Preliminary)
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74VCX16373 Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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