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PSD9XX Family Product Brief
PSD913F2 PSD934F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers
January, 2000 Preliminary
47280 Kato Road, Fremont, California 94538 Tel: 510-656-5400 Fax: 510-657-8495 800-TEAM-WSI (800-832-6974) Web Site: http://www.waferscale.com E-mail: info@waferscale.com
PSD9XX Family Product Brief
PSD913F2 PSD934F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers
Table of Contents
New ! EasyFLASH PSD9XX ..............................................................................................................................................................1 Introduction ........................................................................................................................................................................................2 In-System Programming (ISP) via JTAG .................................................................................................................................3 In-Application re-Programming (IAP) .......................................................................................................................................3 Key Features......................................................................................................................................................................................4 PSD9XX Family .................................................................................................................................................................................5 Package Information ..........................................................................................................................................................................5 PSD9XX Pin Descriptions ..................................................................................................................................................................6 Architectural Overview .......................................................................................................................................................................7 Memory ....................................................................................................................................................................................8 Page Register...........................................................................................................................................................................8 PLDs.........................................................................................................................................................................................8 I/O Ports ...................................................................................................................................................................................8 Microcontroller Bus Interface....................................................................................................................................................9 In-System Programming (ISP) Port via JTAG ..........................................................................................................................9 In-Application re-Programming (IAP) .......................................................................................................................................9 Power Management ...........................................................................................................................................................................9 Development Tools ..........................................................................................................................................................................10 Development and Programming Software .............................................................................................................................10 Development Kit .....................................................................................................................................................................10 PSDsoft Express Design Flow ...............................................................................................................................................11 PSD9XXF Register Description and Address Offset .......................................................................................................................12 Interfacing the PSD9XX with an 80C31 ...........................................................................................................................................12 Interfacing the PSD9XX with a 68HC11 (Muxed Address/Data Bus) ..............................................................................................13 Absolute Maximum Ratings .............................................................................................................................................................13 Operating Range..............................................................................................................................................................................13 Recommended Operating Conditions..............................................................................................................................................13 AC/DC Parameters ..........................................................................................................................................................................14 Example of PSD9XXF Typical Power Calculation at Vcc = 5.0 V ..........................................................................................14 Example of Typical Power Calculation at Vcc = 5.0 V in Turbo Off Mode..............................................................................15 PSD9XX DC Characteristics (5 V 10% Versions) .........................................................................................................................16 Microcontroller Interface - PSD9XX AC/DC Parameters (5 V 10% Versions) .............................................................................17 Read Timing ...........................................................................................................................................................................17 Write Timing ...........................................................................................................................................................................18 Combinatorial Timing .............................................................................................................................................................19 Package Dimensions .......................................................................................................................................................................20 Selector Guide .................................................................................................................................................................................20 Part Number Construction ...............................................................................................................................................................21 Ordering Information ........................................................................................................................................................................21 Worldwide Sales, Service and Technical Support ...........................................................................................................................22
For additional information, Call 800-TEAM-WSI (800-832-6974). Fax: 510-657-8495 Web Site: http://www.waferscale.com E-mail: info@waferscale.com
i
PSD913F2, PSD934F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers
Product Brief
New! EasyFLASH TM PSD9XX
An EasyFLASHTM PSD, Programmable System Device, is the first configurable memory system for your MCU to offer In-System Programmability (ISP) of blank devices. This is accomplished via a 4 pin ISP port, based on the JTAG standard, which allows code to flow directly into the PSD memory banks by-passing the MCU. As a result, blank devices can be soldered onto the circuit board, and programmed at the end of the assembly line, thus eliminating the need to inventory pre-programmed devices. EasyFLASH PSDs also offer concurrent memory arrays, to support In-Application re-Programmability (IAP), which allows execution out of one memory array, while the other is being updated, and vice versa. The EasyFLASH PSD9XX family, integrates up to 2Mbits of Flash, 256Kbits of concurrent Flash or EEPROM, up to 64Kbits of SRAM, additional I/O, power management, a security feature, and advanced ISP options onto a single chip. They are 100% configurable with PSDsoft Express, and programmable via the ISP port, your MCU's serial port, or a third party device programmer.
PSDsoft Express TM Simple! Point and Click Configuration.
PSDsoft ExpressTM allows for complete configuration of the PSD9XX family of PSDs. The simple point and click environment automatically configures the microcontroller interface based on the selected MCU, and then proceeds to step the designer through configuration, all the way through to programming your code and firmware into the PSD. It's never been easier to increase the functionality of your embedded design. Visit www.waferscale.com to download your embedded design. Visit www.waferscale.com to download your FREE fully functional copy of PSDsoft Express today!
Preliminary Information
1
PSD9XX Family
Product Brief
The PSD9XX family of Programmable System Devices (PSD) for 8-bit microcontrollers, brings In-SystemProgrammability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD9XX devices combine many of the peripheral functions found in MCU based applications:
1.0 Introduction
* Up to 2 Mbit of Flash memory * A secondary 256 Kbit Flash memory * Over 2,000 gates of Flash programmable logic * Up to 64 Kbit SRAM * Reconfigurable I/O ports * Programmable power management.
Figure 1. Block Diagram - PSD9XXF2 Programmable MCU Peripheral
2
Preliminary Information
Product Brief
PSD9XX Family
The PSD9XX family offers two methods to program PSD Flash memory while the PSD is soldered to a circuit board.
1.0 Introduction
(Cont.)
In-System Programming (ISP) via JTAG
An IEEE 1149.1 compliant JTAG interface is included on the PSD enabling the entire device (both flash memories, the PLD, and all configuration) to be programmed while soldered to the circuit board in a matter of seconds. This requires no MCU participation, which means the PSD can be programmed anytime, even when completely blank. The innovative JTAG interface to flash memories is an industry first, solving key problems faced by designers and manufacturing houses, such as:
*
First time programming - How do I get firmware into the flash the very first time? JTAG is the answer, program the PSD while blank with no MCU involvement. Inventory build-up of pre-programmed devices - How do I maintain an accurate count of pre-programmed flash memory and PLD devices based on customer demand? How many and what version? JTAG is the answer, build your hardware with blank PSDs soldered directly to the board and then custom program just before they are shipped to customer. No more labels on chips and no more wasted inventory. Expensive sockets - How do I eliminate the need for expensive and unreliable sockets? JTAG is the answer. Solder the PSD directly to the circuit board. Program first time and subsequent times with JTAG. No need to handle devices and bend the fragile leads.
*
*
In-Application re-Programming (IAP)
Two independent flash memory arrays are included so the MCU can execute code from one memory while erasing and programming the other. Robust product firmware updates in the field are possible over any communication channel (CAN, Ethernet, UART, J1850, etc) using this unique architecture. Designers are relieved of these problems:
*
*
Simultaneous read and write to flash memory - How can the MCU program the same memory from which it is executing code? It cannot. The PSD allows the MCU to operate the two flash memories concurrently, reading code from one while erasing and programming the other during IAP. Complex memory mapping - I have only a 64K-byte address space to start with.How can I map these two memories efficiently? A Programmable Decode PLD is the answer. The concurrent PSD memories can be mapped anywhere in MCU address space, segment by segment with extremely high address resolution. As an option, the secondary flash memory can be swapped out of the system memory map when IAP is complete. A built-in page register breaks the 64K-byte address limit. Separate program and data space - How can I write to flash memory while it resides in "program" space during field firmware updates, my MCU won't allow it! The flash PSD provides means to "reclassify" flash memory as "data" space during IAP, then back to "program" space when complete.
*
Preliminary Information
3
PSD9XX Family
Product Brief
PSDsoft Express - Waferscale's software development tool - guides you through the design process step-by-step making it possible to complete an embedded MCU design capable of ISP/IAP in just hours. Select your MCU and PSDsoft Express will take you through the remainder of the design with point and click entry, covering...PSD selection, pin definitions, programmable logic inputs and outputs, MCU memory map definition, ANSI C code generation for your MCU, and merging your MCU firmware with the PSD design. When complete, two different device programmers are supported directly from PSDsoft - FlashLINK (JTAG) and PSDpro. The PSD9XX is available in 52-pin PLCC and PQFP packages.
1.0 Introduction
(Cont.)
2.0 Key Features
t
A simple interface to 8-bit microcontrollers that use either multiplexed or non-multiplexed busses. The bus interface logic uses the control signals generated by the microcontroller automatically when the address is decoded and a read or write is performed. A partial list of the MCU families supported include: * Intel 8031, 80196, 80186, 80C251 * Motorola 68HC11, 68HC16, 68HC12, and 683XX * Philips 8031 and 8051XA * Zilog Z80, Z8, and Z180 * Infineon C500 * Dallas 80C320 Internal 1 or 2 Mbit flash memory. This is the main Flash memory. It is divided into eight equal-sized blocks that can be accessed with user-specified addresses. Internal secondary 256 Kbit Flash memory. It is divided into four equal-sized blocks that can be accessed with user-specified addresses. This secondary memory brings the ability to execute code and update the main Flash concurrently. 16 or 64 Kbit SRAM. The SRAM's contents can be protected from a power failure by connecting an external battery. General Purpose PLD (GPLD) with 19 outputs. The GPLD may be used to implement external chip selects or combinatorial logic function. Decode PLD (DPLD) that decodes address for selection of internal memory blocks. 27 individually configurable I/O port pins that can be used for the following functions: * MCU I/Os * PLD I/Os * Latched MCU address output * Special function I/Os. * 16 of the I/O ports may be configured as open-drain outputs.
t t t t t t
4
Preliminary Information
Product Brief
PSD9XX Family
t t t t t
Standby current as low as 50 A for 5 V devices. Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP). With it, you can program a blank device or reprogram a device in the factory or the field. Internal page register that can be used to expand the microcontroller address space by a factor of 256. Internal programmable Power Management Unit (PMU). The PMU can automatically detect a lack of microcontroller activity and put the PSD9XX into Power Down Mode. Erase/Write cycles: * Flash memory - 100,000 minimum * PLD - 1,000 minimum
2.0 Key Features
(cont.)
3.0 PSD9XX Family
There are 2 variants in the PSD9XX family. All PSD9XX devices provide these base features: 1 or 2 Mbit main Flash Memory, JTAG port, GPLD, DPLD, power management, and 27 I/O pins. The following table summarizes all the devices in the PSD9XX family. Additional devices will be introduced.
Table 1. PSD9XX Product Matrix
Part # PSD9XX Family
PSD9XX
Device
PSD913F2 PSD934F2
I/O Pins
27 27
No. of GPLD Output
19 19
Serial ISP JTAG/ISC Port
Yes Yes
Flash Main Memory Kbit (8 Sectors)
1024 2048
Secondary Flash Memory Kbit (4 Sectors)
256 256
SRAM Kbit
16 64
Turbo Mode
Yes Yes
Supply Voltage
5V 5V
CNTL2
7 PD2 PD1 PD0 PC7 PC6 PC5 PC4 VCC GND PC3 PC2 (VSTBY) PC1 PC0 8 9 10 11 12 13 14 15 16 17 18 19 20
6
5
4
3
2 1
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 VCC AD7 AD6 AD5 AD4
21 22 23 24 25 26 27 28 29 30 31 32 33
CNTL1
GND
AD1
RESET
AD2
CNTL0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Figure 2. Drawing M3 - 52-Pin Plastic Quad Flatpack (PQFP) (Package Type M)
CNTL1 GND PB0 PB2 PB3 PB6 PB1 PB4 PB5 PB7 CNTL2
52 51 50 49 48 47 46 45 44 43 42 41 40
PD2 PD1 PD0 PC7 PC6 PC5 PC4 VCC GND PC3 PC2 PC1 PC0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
AD0
AD3
39 38 37 36 35 34 33 32 31 30 29 28 27
CNTL0
GND
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
4.0 Package Information
Figure 1. Drawing J7 - 52-Pin Plastic Leaded Chip Carrier (PLCC) (Package Type J)
RESET
AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 VCC AD7 AD6 AD5 AD4
AD1
PA7
AD0
Preliminary Information
GND
AD2
AD3
PA2
PA5
PA4
PA3
PA6
PA1
PA0
5
PSD9XX Family
Product Brief
The following table describes the pin names and pin functions of the PSD9XX. Pins that have multiple names and/or functions are defined using PSDsoft's new Point and Click environment.
5.0 Table 2. PSD9XX Pin Descriptions
Pin Name
ADIO0-15 CNTL0-2 Reset PA0-PA7
Type
I/O I I I/O
Description
This is the lower Address/Data port. Connect your MCU address or address/data bus. Configurable MCU control signals. Active low reset input. Resets I/O Ports and some of the configuration registers. Must be active at power up. These pins make up Port A. These port pins are configurable and can have the following functions: 1. MCU I/O 2. General Purpose PLD outputs. 3. Inputs to the PLDs. 4. Latched address outputs. 5. As the data bus inputs D[0:7] for non-multiplexed address/data bus MCUs (PA0-PA7 only). These pins make up Port B. These port pins are configurable and can have the following functions: 1. MCU I/O 2. General Purpose PLD outputs. 3. Inputs to the PLDs. 4. Latched address outputs. PC0 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O 2. Input to the PLDs. 3. JTAG interface signals. 4. Battery backed SRAM connections. PD0 pin of Port D. This port pin can be configured to have the following functions: 1. ALE/AS input latches address output from the MCU (PD0 only). 2. MCU I/O -- write or read from a standard output or input port. 3. Input to the PLDs. 4. General Purpose PLD output. 5. CLKIN -- clock input to the automatic power-down unit's power-down counter, and the PLD AND array (PD1 only). 6. CSI -- chip select input. When low, the MCU can access the PSD memory and I/O. When high, the PSD memory blocks are disabled to conserve power (PD2 only). Power pins Ground pins
PB0-PB7
I/O
PC0-PC7
I/O
PD0-PD2
I/O
VCC GND
PSDsoft Express Pin Definition
6
Preliminary Information
Product Brief
PSD9XX Family
PSD9XX devices contain several major functional blocks. Figures 4 and 5 show the architecture of the PSD9XX device family. The functions of each block are described briefly in the following sections. Many of the blocks perform multiple functions and are user configurable.
6.0 Architectural Overview
Figure 4
Figure 5
Preliminary Information
7
PSD9XX Family
Product Brief 6.1 Memory
The PSD9XX contains the following memories: * A 1 or 2 Mbit Flash * A secondary 256 Kbit Flash memory * 16 or 64 Kbit SRAM. Each of the memories is briefly discussed in the following paragraphs. A more detailed discussion can be found in section 9. The 1 or 2 Mbit Flash is the main memory of the PSD9XX. It is divided into eight equally-sized sectors that are individually selectable. The 256 Kbit secondary Flash memory is divided into four equally-sized sectors. Each sector is individually selectable. This memory can hold boot code or data, and can be used by the MCU for operation during In-System re-Programming (IAP) of the main Flash. The 16 or 64 Kbit SRAM is intended for use as a scratchpad memory or as an extension to the microcontroller SRAM. If an external battery is connected to the PSD9XX's Vstby pin, data will be retained in the event of a power failure. Each block of memory can be located in a unique address space as defined by the user. The access times for all memory types includes the address latching and DPLD decoding time.
6.0 Architectural Overview
6.2 Page Register
The eight-bit Page Register expands the address range of the microcontroller by up to 256 times. The paged address can be used as part of the address space to access external memory and peripherals or internal memory and I/O. The Page Register can also be used to change the address mapping of blocks of Flash memory into different memory spaces IAP.
6.3 PLDs
The device contains two combinatorial PLD blocks, each optimized for a different function, as shown in Table 3. The functional partitioning of the PLDs reduces power consumption, optimizes cost/performance, and eases design entry. The Decode PLD (DPLD) is used to decode addresses and generate chip selects for the PSD9XX internal memory and registers. The General Purpose PLD (GPLD) can implement user-defined external chip selects and logic functions. The PLDs consume minimal power by using Zero-Power design techniques. The speed and power consumption of the PLD is controlled by the Turbo Bit in the PMMR0 register and other bits in the PMMR2 registers. These registers are set by the microcontroller at runtime.
6.4 I/O Ports
The PSD9XX has 27 I/O pins divided among four ports (Port A, B, C, and D). Each I/O pin can be individually configured for different functions. Ports A, B, C and D can be configured as standard MCU I/O ports, PLD I/O, or latched address outputs for microcontrollers using multiplexed address/data busses. The JTAG pins can be enabled on Port C for In-System Programming (ISP). Port A can also be configured as a data port for a non-multiplexed bus.
Table 3. PLD I/O Table Name
Decode PLD General Purpose PLD
Abbreviation
DPLD GPLD
Inputs
57 57
Outputs
15 19
Product Terms
39 114
8
Preliminary Information
Product Brief
PSD9XX Family 6.5 Microcontroller Bus Interface
The PSD9XX easily interfaces with most 8-bit microcontrollers that have either multiplexed or non-multiplexed address/data busses. The device is configured to respond to the microcontroller's control signals, which are also used as inputs to the PLDs. Section 9.3.5 contains microcontroller interface examples.
6.0 Architectural Overview
(cont.)
6.6 In-System Programming (ISP) Port via JTAG
In-System Programming can be performed through the JTAG pins on Port C. This serial interface allows complete programming of the entire PSD9XX device. A blank device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) are enabled on Port C when selected or when a device is blank.
6.7 In-Application re-Programming (IAP)
The main Flash memory can also be programmed in-system by the microcontroller executing the programming algorithms out of the Secondary Flash memory, or SRAM (IAP). The Secondary Flash memory can be programmed the same way by executing out of the main Flash memory. This includes all the memory blocks, the PLD, MCU interface and all other configuration. Table 4 indicates which programming methods can program different functional blocks of the PSD9XX.
Table 4. Methods of Programming Different Functional Blocks of the PSD9XX Functional Block
Main Flash Memory Secondary Flash Memory PLD Array (DPLD and GPLD) PSD Configuration
JTAG-ISP
Yes Yes Yes Yes
Device Programmer
Yes Yes Yes Yes
IAP
Yes Yes No No
7.0 Power Management
The PSD9XX offers configurable power saving options. These options may be used individually or in combinations, as follows: t All memory types in a PSD (Flash, Secondary Flash Block, and SRAM) are built with Zero-Power technology. In addition to using special silicon design methodology, Zero-Power technology puts the memories into standby mode when address/data inputs are not changing (zero DC current). As soon as a transition occurs on an input, the affected memory "wakes up", changes and latches its outputs, then goes back to standby. The designer does not have to do anything special to achieve memory standby mode when no inputs are changing--it happens automatically. The PLD sections can also achieve standby mode when its inputs are not changing, see PMMR registers below. t The Automatic Power Down (APD) logic allows the PSD to reduce to standby current automatically and keeps it in standby with no chance of noise or miscellaneous signals waking it up. The APD will block MCU address/data signals from reaching the memories and PLDs. This feature is available on all PSD9XX devices. Built in logic will monitor the address strobe of the MCU for activity. If there is no activity for a certain time period (MCU is asleep), the APD logic initiates Power Down Mode (if enabled). Once in Power Down Mode, all address/data signals are blocked from reaching PSD memories and PLDs, and the memories are deselected internally. This allows the memories and PLDs to remain in standby mode even if the address/data lines are changing state externally (noise, other devices on the MCU bus, etc.).
t
The PSD Chip Select Input (CSI) on all families can be used to disable the internal memories, placing them in standby mode even if inputs are changing. This feature does not block any internal signals or disable the PLDs. This is a good alternative to using the APD logic, especially if your MCU has a chip select output. There is a slight penalty in memory access time when the CSI signal makes its initial transition from deselected to selected. The PMMR registers can be written by the MCU at run-time to manage power. All PSD devices support "blocking bits" in these registers that are set to block designated signals from reaching both PLDs. Current consumption of the PLDs is directly related to the composite frequency of the changes on their inputs Significant power savings can be achieved by blocking signals that are not used in PLD equations. The PSD9XX devices have a Turbo Bit in the PMMR0 register. This bit can be set to disable the Turbo Mode feature (default is Turbo Mode on). While Turbo Mode is disabled, the PLDs can achieve standby current when no PLD inputs are changing (zero DC current). Even when inputs do change, significant power can be saved at lower frequencies (AC current), compared to when Turbo Mode is enabled.
t
t
Preliminary Information
9
PSD9XX Family
Product Brief Development and Programming Software
The PSD9XX family is supported by the new PSDsoft Express, a Windows-based (95, 98, NT) software development tool. A PSD is quickly configured in a point and click environment. The designer does not need to enter Hardware Definition Language (HDL) equations to define PSD pin functions and memory map information. The general design flow is shown in Figure 6. PSDsoft Express is available free from our web site (www.waferscale.com) or the Waferscale Literature CD. PSDsoft Express directly supports two low cost device programmers from Waferscale, PSDpro and FlashLINK (JTAG). Both of these programmers may be purchased through your local rep/distributor, or directly from our web site using a credit card. The PSD9XX is also supported by third party device programmers, see web site for current list.
8.0 Development Tools
Development Kit DK900 * Supports New Flash PSD9XX * FlashLINK TM Programmer * Example ISP and IAP Templates * Target Board for Programming using ISP
* *
via JTAG port PSDsoft Express for Free on Web $99 U.S. and can be ordered at www.waferscale.com or through any franchised distributor or sales representative
10
Preliminary Information
PSD9XX Family
Product Brief
Figure 6. PSDsoft Express Design Flow
Choose MCU and PSD
Automatically configures MCU bus interface and other PSD attributes.
Define PSD Pin and Node Functions
Point and click definition of PSD pin functions, internal nodes, and MCU system memory map.
C Code Generation
Generate C Code specific to PSD functions.
Merge MCU Firmware with PSD Configuration
A composite object file is created containing MCU firmware and PSD configuration.
MCU Firmware Hex or S-Record Format
User's choice of Microcontroller Compiler/Linker
*.OBJ File
Waferscale PSD Programmer
PSDPro or FlashLINK (JTAG)
*.OBJ file available for 3rd party programmers. (conventional or JTAG-ISC)
Preliminary Information
11
PSD9XX Family
Product Brief
Table 5 shows the offset addresses to the PSD9XX registers relative to the CSIOP base address. The CSIOP space is the 256 bytes of address that is allocated by the user to the internal PSD9XX registers. Table 5 provides brief descriptions of the registers in CSIOP space. For a more detailed description, refer to section 9.
9.0 PSD9XX Register Description and Address Offset
Table 5. Register Address Offset Register Name
Data In Control Data Out Direction
Port A Port B Port C
00 02 04 06 01 03 05 07 12 14 10
Port D Other*
11
Description
Reads Port pin as input, MCU I/O input mode Selects mode between MCU I/O or Address Out
13 15
Stores data for output to Port pins, MCU I/O output mode Configures Port pin as input or output Configures Port pins as either CMOS or Open Drain on some pins, while selecting high slew rate on other pins. C0 C2 B0 B4 E0 E2 Read only - Flash Sector Protection Read only - PSD Security and Secondary Flash Sector Protection Power Management Register 0 Power Management Register 2 Page Register Places PSD memory areas in Program and/or Data space on an individual basis.
Drive Select Flash Protection Secondary Flash Protection PMMR0 PMMR2 Page VM
08
09
16
17
*Other registers that are not part of the I/O ports.
10.0 Figure 7. Interfacing the PSD9XX with an 80C31
AD[ 7:0] AD[ 7:0]
80C31
31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 EA/VP X1 X2 RESET INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE/P TXD RXD 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14 A15 RD WR PSEN ALE AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 30 31 32 33 34 35 36 37
PSD9XXF
ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 29 28 27 25 24 23 22 21
RESET
39 40 41 42 43 44 45 46
ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
7 6 5 4 3 2 52 51 20 19 18 17 14 13 12 11
47 50 49 10 9 8 48
CNTL0 (WR) CNTL1(RD) CNTL2 (PSEN) PD0-ALE PD1 PD2 RESET
RESET RESET
12
Preliminary Information
Product Brief
PSD9XX Family
Figure 8. Interfacing the PSD9XX with a 68HC11 (Muxed Address/ Data Bus)
RESET
AD[7:0] AD[7:0]
PSD9XXF 68HC11
8 7 17 19 18 2 34 33 32 XT EX RESET IRQ XIRQ MODB PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 31 30 29 28 27 42 41 40 39 38 37 36 35 9 10 11 12 13 14 15 16 20 21 22 23 24 25 3 5 4 6 E AS R/W AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14 A15 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD105 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO11 AD1012 AD1013 ADIO14 ADIO15 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 29 28 27 25 24 23 22 21 7 6 5 4 3 2 52 51 20 19 18 17 14 13 12 11
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 MODA E AS R/W
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
43 44 45 46 47 48 49 50 52 51
PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 VRH VRL
47 50 49 10 9 8 48
CNTL0 (R _W) CNTL1(E) CNTL 2 PD0 - AS PD1 PD2 RESET
RESET
11.0 Absolute Maximum Ratings
Symbol
TSTG
Parameter
Storage Temperature
Condition
Commercial
Min
- 65 0 - 40 - 0.6 - 0.6 - 0.6
Max
+ 125 + 70 + 85 +7 + 14 +7
Unit
C C C V V V V
Operating Temperature Voltage on any Pin VPP VCC Device Programmer Supply Voltage Supply Voltage ESD Protection
Industrial With Respect to GND With Respect to GND With Respect to GND
>2000
NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not recommended. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.
12.0 Operating Range
Range
Commercial Industrial
Temperature
0 C to +70C -40 C to +85C
VCC Tolerance
+ 5 V 10% + 5 V 10%
Note: 3 V devices will be introduced at a later date.
13.0 Recommended Operating Conditions
Symbol
VCC
Parameter
Supply Voltage
Condition
All Speeds
Min
4.5
Typ
5
Max
5.5
Unit
V
Note: 3 V devices will be introduced at a later date.
Preliminary Information
13
PSD9XX Family
Product Brief
The following tables describe the AD/DC parameters of the PSD9XX family: t DC Electrical Specification t AC Timing Specification * PLD Timing - Combinatorial Timing * Microcontroller Timing - Read Timing - Write Timing - Power Down and Reset Timing Following are issues concerning the parameters presented: t In the DC specification the supply current is given for different modes of operation. Before calculating the total power consumption, determine the percentage of time that the PSD9XX is in each mode. Also, the supply power is considerably different if the Turbo bit is "OFF". t The AC power component gives the PLD, Flash memory, and SRAM mA/MHz specification. Figure 9 shows the PLD mA/MHz as a function of the number of Product Terms (PT) used. t In the PLD timing parameters, add the required delay when Turbo bit is "OFF".
14.0 AC/DC Parameters
Figure 9. PLD ICC /Frequency Consumption (VCC = 5 V 10%)
110 100 90 80
T O URB ON (100
VCC = 5V
%)
ICC - (mA)
70 60 50 40 30 20 10 0 0 5 10 15 20 25 HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
TU RB O OF F
TU R B O O FF
TUR
BO
ON
(25%
)
PT 100% PT 25%
Example of PSD9XX Typical Power Calculation at VCC = 5.0 V Conditions
Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash Access % SRAM access % I/O access Operational Modes % Normal % Power Down Mode Number of product terms used (from fitter report) % of total product terms Turbo Mode = = = = = = = = = = 8 MHz 4 MHz 80% 15% 5% (no additional power above base) 10% 90% 45 PT 45/153 = 29.4% ON
Calculation (typical numbers used)
ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc)) = Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE + %SRAM x 1.5 mA/MHz x Freq ALE + % PLD x 2 mA/MHz x Freq PLD + #PT x 400 A/PT = 50 A x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz + 0.15 x 1.5 mA/MHz x 4 MHz +2 mA/MHz x 8 MHz + 45 x 0.4 mA/PT) = 45 A + 0.1 x (8 + 0.9 + 16 + 18 mA) = 45 A + 0.1 x 42.9 = 45 A + 4.29 mA = 4.34 mA
This is the operating power with no Flash writes or erases. Calculation is based on IOUT = 0 mA.
14
Preliminary Information
Product Brief
PSD9XX Family Example of Typical Power Calculation at VCC = 5.0 V in Turbo Off Mode Conditions
Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash Access % SRAM access % I/O access Operational Modes % Normal % Power Down Mode Number of product terms used (from fitter report) % of total product terms Turbo Mode = = = = = = = = = = 8 MHz 4 MHz 80% 15% 5% (no additional power above base) 10% 90% 45 PT 45/153 = 29.4% Off
AC/DC Parameters
(cont.)
Calculation (typical numbers used)
ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc)) = Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE + %SRAM x 1.5 mA/MHz x Freq ALE + % PLD x (from graph using Freq PLD)) = 50 A x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz + 0.15 x 1.5 mA/MHz x 4 MHz + 24 mA) = 45 A + 0.1 x (8 + 0.9 + 24) = 45 A + 0.1 x 32.9 = 45 A + 3.29 mA = 3.34 mA This is the operating power with no Flash writes or erases. Calculation is based on IOUT = 0 mA.
Preliminary Information
15
PSD9XX Family PSD9XX DC Characteristics (5 V 10% Versions) Symbol
VCC VIH VIL VIH1 VIL1 VHYS VLKO VOL Supply Voltage High Level Input Voltage Low Level Input Voltage Reset High Level Input Voltage Reset Low Level Input Voltage Reset Pin Hysteresis VCC Min for Flash Erase and Program Output Low Voltage IOL = 20 A, VCC = 4.5 V IOL = 8 mA, VCC = 4.5 V Output High Voltage Except VSTBY On Output High Voltage VSTBY On SRAM Standby Voltage SRAM Standby Current (VSTBY Pin) Idle Current (VSTBY Pin) SRAM Data Retention Voltage Standby Supply Current for Power Down Mode Input Leakage Current Output Leakage Current VCC = 0 V VCC > VSBY Only on VSTBY CSI > VCC -0.3 V (Notes 2 and 3) VSS < VIN < VCC 0.45 < VIN < VCC PLD_TURBO = OFF, f = 0 MHz (Note 5) PLD ICC (DC) (Note 5) Operating Supply Current Flash PLD_TURBO = ON, f = 0 MHz During Flash Write/Erase Only Read Only, f = 0 MHz SRAM PLD AC Adder ICC (AC) (Note 5) FLASH AC Adder SRAM AC Adder NOTE: 1. 2. 3. 4. 5. Reset input has hysteresis. VIL1 is valid at or below .2VCC -.1. VIH1 is valid at or above .8VCC. CSI deselected or internal Power Down mode is active. PLD is in non-turbo mode and none of the inputs are switching Refer to Figure 32 for PLD current calculation. I OUT = 0 mA f = 0 MHz -1 -10 -0.1 2 50 .1 5 0 400 700 200 1 10 IOH = -20 A, VCC = 4.5 V IOH = -2 mA, VCC = 4.5 V IOH = 1 A 1 4.4 2.4 VSBY - 0.8 2.0 0.5 VCC 1 0.1
Product Brief
Parameter
All Speeds
Conditions
4.5 V < VCC < 5.5 V 4.5 V < VCC < 5.5 V (Note 1) (Note 1)
Min
4.5 2 -.5 .8 VCC -.5 0.3 2.5
Typ
5
Max
5.5 VCC +.5 0.8 VCC +.5 .2 VCC -.1 4.2
Unit
V V V V V V V V V V V V V A A V A A A mA A/PT
0.01 0.25 4.49 3.9
0.1 0.45
VOH VOH 1 VSBY ISBY IIDLE VDF ISB ILI ILO
15 0 0 Fig. 9 (Note 4) 2.5 1.5
30 0 0
mA mA mA
3.5 3.0
mA/MHz mA/MHz
16
Preliminary Information
Product Brief
PSD9XX Family
Microcontroller Interface - PSD9XX AC/DC Parameters
(5V 10% Versions)
Read Timing (5 V 10% Versions) -90 Symbol
t LVLX t AVLX t LXAX t AVQV t SLQV t RLQV t RHQX t RLRH t RHQZ t EHEL t THEH t ELTL t AVPV
NOTES: 1. 2. 3. 4. 5.
-15 Max Min
28 10 11 90 100 150 150 40 45 0 38 25 30 38 18 0 25 32
Parameter
ALE or AS Pulse Width Address Setup Time Address Hold Time Address Valid to Data Valid CS Valid to Data Valid RD to Data Valid 8-Bit Bus RD or PSEN to Data Valid 8-Bit Bus, 8-Bit Bus, 8031, 80251 RD Data Hold Time RD Pulse Width RD to Data High-Z E Pulse Width R/W Setup Time to Enable R/W Hold Time After Enable Address Input Valid to Address Output Delay
Conditions
(Note 3) (Note 3) (Note 3)
Min
20 6 8
Max
Turbo Off
Unit
ns ns ns
Add 10
ns ns ns ns ns ns ns ns ns ns ns
(Note 5) (Note 2) (Note 1) (Note 1) (Note 1) 32 10 0 (Note 4) 0 32
32 38
RD timing has the same timing as DS, LDS, UDS, and PSEN signals. RD and PSEN have the same timing. Any input used to select an internal PSD9XX function. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port. RD timing has the same timing as DS, LDS, and UDS signals.
Figure 10. Read Timing
tAVLX ALE/AS tLVLX A/D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS tSLQV CSI tRLQV tRLRH RD (PSEN, DS) tRHQZ tRHQX ADDRESS VALID tAVQV ADDRESS VALID DATA VALID tLXAX*
DATA VALID
tEHEL E tTHEH tELTL
R/W
tAVPV ADDRESS OUT
*tAVLX and tLXAX are not required for 80C251 in Page Mode or 80C51XA in Burst Mode.
Preliminary Information
17
PSD9XX Family
Product Brief
Microcontroller Interface - PSD9XX AC/DC Parameters
(5V 10% Versions)
Write Timing (5 V 10% Versions) -90 Symbol
t LVLX t AVLX t LXAX t AVWL t SLWL t DVWH t WHDX t WLWH t WHAX1 t WHAX2 t WHPV t AVPV
NOTES: 1. 2. 3. 4.
-15 Min
28 10 11 20 20 45 5 45 10 0 ns ns ns ns ns ns ns ns ns
Parameter
ALE or AS Pulse Width Address Setup Time Address Hold Time Address Valid to Leading Edge of WR CS Valid to Leading Edge of WR WR Data Setup Time WR Data Hold Time WR Pulse Width Trailing Edge of WR to Address Invalid Trailing Edge of WR to DPLD Address Input Invalid Trailing Edge of WR to Port Output Valid Using I/O Port Data Register Address Input Valid to Address Output Delay
Conditions
(Note 1) (Note 1) (Notes 1 and 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3 and 4)
Min
20 6 8 15 15 35 5 35 8 0
Max
Max
Unit
(Note 3) (Note 2)
30 25
38 30
ns ns
Any input used to select an internal PSD9XX function. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port. WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals. Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory.
Figure 11. Write Timing
tAVLX ALE /AS t LVLX A/D MULTIPLEXED BUS ADDRESS VALID tAVWL ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS tSLWL CSI tDVWH WR (DS) t WLWH t WHDX t WHAX ADDRESS VALID DATA VALID DATA VALID t LXAX
t EHEL E t THEH R/ W t WLMV tAVPV ADDRESS OUT t WHPV STANDARD MCU I/O OUT t ELTL
18
Preliminary Information
Product Brief
PSD9XX Family
Microcontroller Interface - PSD9XX AC/DC Parameters
(5V 10% Versions)
PLD Combinatorial Timing (5 V 10%)
-90 Symbol
t PD t ARD
-15 Max
25 16
Parameter
PLD Input Pin/Feedback to PLD Combinatorial Output PLD Array Delay
Conditions
Min
Min
Max
32 22
TURBO Slew OFF (Note 1) Unit
Add 10 Sub 2 ns ns
NOTE: 1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0].
Figure 12. Combinatorial Timing - PLD
CPLD INPUT t PD CPLD OUTPUT
Figure 13. Drawing J7 - 52-Pin Plastic Leaded Chip Carrier (PLCC) (Package Type J)
D D1
3 2 1 52 51
E1
E .025 .045 R
View A
B1 A2
C
B D3 D2 A1 A E3 E2
e1
View A
Family: Plastic Leaded Chip Carrier Symbol
A A1 A2 B B1 C D D1 D2 D3 E E1 E2 E3 e1 N
Min
4.19 2.54 3.66 0.33 0.66 0.246 19.94 19.05 17.53 15.24 19.94 19.05 17.53 15.24 1.27 52
Millimeters Max
4.57 2.79 3.86 0.53 0.81 0.261 20.19 19.15 18.54
Notes
Min
0.165 0.100 0.144 0.013 0.026 0.0097 0.785 0.750 0.690
Inches Max
0.180 0.110 0.152 0.021 0.032 0.0103 0.795 0.754 0.730 0.600
Notes
Reference 20.19 19.15 18.54 Reference Reference 0.785 0.750 0.690
Reference 0.795 0.754 0.730
0.600 0.050 52
Reference Reference
Preliminary Information
19
PSD9XX Family
Product Brief
Figure 14. Drawing M3 - 52-Pin Plastic Quad Flatpack (PQFP) (Package Type M)
D D1 D3
52
1 2 3
Index Mark E3 E1 E
Standoff: 0.05 mm Min. A2 A C
L B e1 Lead Coplanarity: 0.1mm Max.
Family: Plastic Quad Flatpack (PQFP) Symbol
A A2 B C D D1 D3 E E1 E3 e1 L N 0.73 52 13.15 9.95 7.80 0.65 1.03 13.15 9.95 7.80 13.25 10.05 Reference Reference 0.029 52
060198R0
Min
0 - 1.95 0.22
Millimeters Max
7 2.35 2.10 0.38 0.23 13.25 10.05
Notes
Min
0 - 0.077
Inches Max
7 0.093 0.083 0.015 0.009 0.522 0.396 0.307
Notes
Reference
0.009 0.518 0.392
Reference 0.518 0.392
Reference 0.522 0.396
0.307 0.026 0.041
Reference Reference
15.0 Selector Guide
Selector Guide - PSD9XX Family Part #
PSD @ 5V
MCU
Data Path Interface
PLDs/Decoders
PLD Inputs PLD Outputs Page Reg.
I/O
Ports
Memory
Flash Program Store 2nd Flash Boot SRAM
Other
ISP via JTAG Parallel ISP ISP Flash ISP PLDs Periph. Mode Security PMU APD
X X X X X X X X X X X X X X
PSD913F2 PSD934F2
8 8
PLUS1 PLUS1
57 57
19 19
8-Bit 8-Bit
27 27
1MB 2MB
256Kb 256Kb
16Kb 64Kb
Legend: PLUS1 = New Intel 80C251 and Philips 8051XA supported plus all standard MCUs. APD = Automatic Power Down.
20
Preliminary Information
Product Brief
PSD9XX Family
16.0 Part Number Construction
Flash PSD Part Number Construction
CHARACTER # 1 PART NUMBER I P 2 I S 3 I D 4 I 5 I 8 6 I 1 7 I 3 8 I F 9 I 10 11 12 13 14 15 16 17 18 19 I I I I I I I I I 2 -A-1 5J
PSD BRAND NAME PSD = Standard Zero Power Device FAMILY/SERIES 8 = Flash PSD for 8-bit MCUs with Complex PLD 9 = Flash PSD for 8-bit MCUs with Simple PLD SRAM SIZE 0 = 0Kb 1 = 16Kb 2 = 32Kb 3 = 64Kb
TEMP RANGE "Blank" = 0C to +70C (Commercial) I = -40C to +85C (Industrial)
PACKAGE TYPE J = PLCC U = TQFP (not available on some) M = PQFP
SPEED - 90 = 90ns - 15 = 150ns - 20 = 200ns
NVM SIZE 1 = 256Kb 2 = 512Kb 3 = 1Mb 4 = 2Mb
REVISION "Blank" = no rev. - A = Rev. A
I/O COUNT & OTHER F = 27 I/O
Vcc VOLTAGE "blank" = 5 Volt V = 3.0 Volt
2ND NVM TYPE, SIZE & CONFIGURATION 1 = EEPROM, 256Kb 2 = FLASH, 256Kb 3 = No 2nd Array
17.0 Ordering Information
Part Number
PSD913F2-90J PSD913F2-90M PSD913F2-90JI PSD913F2-90MI PSD913F2-15J PSD913F2-15M PSD934F2-90J PSD934F2-90M PSD934F2-90JI PSD934F2-90MI PSD934F2-15J PSD934F2-15M
Speed (ns)
90 90 90 90 150 150 90 90 90 90 150 150
Package Type
52 52 52 52 Pin Pin Pin Pin PLCC PQFP PLCC PQFP
Operating Temperature Range
Comm'l Comm'l Industrial Industrial Comm'l Comm'l Comm'l Comm'l Industrial Industrial Comm'l Comm'l
52 Pin PLCC 52 Pin PQFP 52 52 52 52 Pin Pin Pin Pin PLCC PQFP PLCC PQFP
52 Pin PLCC 52 Pin PQFP
Preliminary Information
21
Waferscale Worldwide Sales, Service and Technical Support
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DISTRIBUTORS
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WORLDWIDE
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12/14/99
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