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CY7C341
192-Macrocell MAX(R) EPLD
Features
* * * * * * 192 macrocells in 12 LABs 8 dedicated inputs, 64 bidirectional I/O pin 0.8-micron double-metal CMOS EPROM technology Programmable interconnect array 384 expander product terms Available in 84-pin HLCC, PLCC, and PGA packages Externally, the CY7C341 provides 8 dedicated inputs, one of which may be used as a system clock. There are 64 I/O pins that may be individually configured for input, output, or bidirectional data flow.
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves interconnect limitations by routing only the signals needed by each logic array block. The inputs to the PIA are the outputs of every macrocell within the device and the I/O pin feedback of every pin on the device. Unlike masked or programmable gate arrays, which induce variable delay dependent on routing, the PIA has a fixed delay. This eliminates undesired skews among logic signals, which may cause glitches in internal or external logic. The fixed delay, regardless of programmable interconnect array configuration, simplifies design by assuring that internal signal skews or races are avoided. The result is ease of design implementation, often in a single pass, without the multiple internal logic placement and routing iterations required for a programmable gate array to achieve design timing objectives.
Functional Description
The CY7C341 is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure logic functions within the device. The MAX architecture is 100% user-configurable, allowing the devices to accommodate a variety of independent logic functions. The 192 macrocells in the CY7C341 are divided into 12 Logic Array Blocks (LABs), 16 per LAB. There are 384 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB. Each LAB is interconnected with a programmable interconnect array, allowing all signals to be routed throughout the chip. The speed and density of the CY7C341 allows them to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 37 times the functionality of 20-pin PLDs, the CY7C341 allows the replacement of over 75 TTL devices. By replacing large amounts of logic, the CY7C341 reduces board space and part count, and increases system reliability. Each LAB contains 16 macrocells. In LABs A, F, G, and L, 8 macrocells are connected to I/O pins and 8 are buried, while for LABs B, C, D, E, H, I, J, and K, 4 macrocells are connected to I/O pins and 12 are buried. Moreover, in addition to the I/O and buried macrocells, there are 32 single product term logic expanders in each LAB. Their use greatly enhances the capability of the macrocells without increasing the number of product terms in each macrocell.
Timing Delays
Timing delays within the CY7C341 may be easily determined using Warp2(R) or Warp3(R) software. The CY7C341 has fixed internal delays, allowing the user to determine the worst case timing delays for any design. For complete timing information, the Warp3 software provides a timing simulator.
Design Recommendations
For proper operation, input and output pins must be constrained to the range GND < (VIN or VOUT) < V CC. Unused inputs must always be tied to an appropriate logic level (either VCC or GND). Each set of V CC and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2 F must be connected between VCC and GND. For the most effective decoupling, each VCC pin should be separately decoupled to GND, directly at the device. Decoupling capacitors should have good frequency response, such as monolithic ceramic types.
Logic Array Blocks
There are 12 logic array blocks in the CY7C341. Each LAB consists of a macrocell array containing 16 macrocells, an expander product term array containing 32 expanders, and an I/O block. The LAB is fed by the programmable interconnect array and the dedicated input bus. All macrocell feedbacks go to the macrocell array, the expander array, and the programmable interconnect array. Expanders feed themselves and the macrocell array. All I/O feedbacks go to the programmable interconnect array so that they may be accessed by macrocells in other LABs as well as the macrocells in the LAB in which they are situated.
Design Security
The CY7C341 contains a programmable design security feature that controls the access to the data programmed into the device. If this programmable feature is used, a proprietary design implemented in the device cannot be copied or retrieved. This enables a high level of design control to be obtained since programmed data within EPROM cells is invisible. The bit that controls this function, along with all other program data, may be reset simply by erasing the device.
MAX is a registered trademark of Altera Corporation. Warp is a trademark of Cypress Semiconductor Corporation. Warp2, and Warp3 are registered trademarks of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
* 408-943-2600 December 9, 1999
CY7C341
Selection Guide
7C341-25 Maximum Access Time (ns) Maximum Operating Current (mA) Commercial Industrial Military Maximum Standby Current (mA) Commercial Industrial Military 25 380 480 480 360 435 435 7C341-30 30 380 480 480 360 435 435 7C341-35 35 380 480 480 360 435 435
2
CY7C341
Logic Block Diagram
1 (A6) 2 (A5) 41 (K6) 42 (J6) INPUT/CLK INPUT INPUT INPUT INPUT INPUT INPUT INPUT (C6) 84 (C7) 83 (L7) 44 (J7) 43
SYSTEMCLOCK 4 (C5) 5 (A4) 6 (B4) 7 (A3) 8 (A2) 9 (B3) 10 (A1) 11 (B2) LAB A MACROCELL 1 MACROCELL 2 MACROCELL 3 MACROCELL 4 MACROCELL 5 MACROCELL 6 MACROCELL 7 MACROCELL 8 MACROCELL 9-16 LAB B 12 13 14 15 (C2) (B1) (C1) (D2) MACROCELL 17 MACROCELL 18 MACROCELL 19 MACROCELL 20 MACROCELL 21-32 LAB G MACROCELL 97 MACROCELL 98 MACROCELL 99 MACROCELL 100 MACROCELL 101 MACROCELL 102 MACROCELL 103 MACROCELL 104 MACROCELL 105-112 LAB H MACROCELL 113 MACROCELL 114 MACROCELL 115 MACROCELL 116 MACROCELL 117-128 54 55 56 57 (J10) (K11) (J11) (H10)
46 47 48 49 50 51 52 53
(L6) (L8) (K8) (L9) (L10) (K9) (L11) (K10)
16 (D1) 17 (E3) 20 (F2) 21 (F3)
LAB C MACROCELL 33 MACROCELL 34 MACROCELL 35 MACROCELL 36
P I A
LAB I MACROCELL 129 MACROCELL 130 MACROCELL 131 MACROCELL 132
58 59 62 63
(H11) (F10) (G9) (F9)
MACROCELL 37-48
MACROCELL 133-144
22 (G3) 23 (G1) 25 (F1) 26 (H1)
LAB D MACROCELL 49 MACROCELL 50 MACROCELL 51 MACROCELL 52
LAB J MACROCELL 145 MACROCELL 146 MACROCELL 147 MACROCELL 148
64 65 67 68
(F11) (E11) (E9) (D11)
MACROCELL 53-64
MACROCELL 149-160
27 (H2) 28 (J1) 29 (K1) 30 (J2)
LAB E MACROCELL 65 MACROCELL 66 MACROCELL 67 MACROCELL 68
LAB K MACROCELL 161 MACROCELL 162 MACROCELL 163 MACROCELL 164
69 70 71 72
(D10) (C11) (B11) (C10)
MACROCELL 69-80
MACROCELL 165-176
31 32 33 34 35 36 37 38
(L1) (K2) (K3) (L2) (L3) (K4) (L4) (J5)
LAB F MACROCELL 81 MACROCELL 82 MACROCELL 83 MACROCELL 84 MACROCELL 85 MACROCELL 86 MACROCELL 87 MACROCELL 88 MACROCELL 89-96
LAB L MACROCELL 177 MACROCELL 178 MACROCELL 179 MACROCELL 180 MACROCELL 181 MACROCELL 182 MACROCELL 183 MACROCELL 184 MACROCELL 185-192 VCC GND
73 74 75 76 77 78 79 80
(A11) (B10) (B9) (A10) (A9) (B8) (A8) (B6)
3, 24, 45, 66 (B5, G2, K7, E10) 18, 19, 39, 40, 60, 61, 81, 82 (E1, E2, K5, L5, G10, G11, A7, B7)
() - PERTAIN TO 84-PIN PGA PACKAGE C341-1
3
CY7C341
Pin Configurations
PLCC/HLCC Top View
INPUT/CLK INPUT INPUT INPUT L GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
PGA Bottom View
GND I/O INPUT I/O I/O I/O I/O
I/O I/O VCC
I/O I/O
I/O
I/O I/O
I/O
K 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 I/O I/O I/O I/O I/O I/O GND GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O 74 12 73 13 72 14 71 15 70 16 69 17 68 18 67 19 66 20 65 21 64 7C341 22 63 23 62 24 61 25 60 26 59 27 58 28 57 29 56 30 55 31 54 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 INPUT INPUT INPUT INPUT VCC I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND GND I/O I/O I/O I/O I/O I/O J
I/O
I/O
I/O
I/O
GND
INPUT
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INPUT INPUT
I/O
I/O
H
I/O
I/O
I/O
I/O
G
I/O
VCC
I/O 7C341
I/O
GND
GND
F
I/O
I/O
I/O
I/O
I/O
I/O
E
GND
GND
I/O
I/O
VCC
I/O
D
I/O
I/O
I/O
I/O
C
I/O
I/O
I/O
INPUT INPUT
I/O
I/O
B
I/O
I/O
I/O
I/O
VCC
I/O
GND
I/O
I/O
I/O
I/O
A
I/O
I/O 2
I/O 3
I/O 4
INPUT/ INPUT CLK GND 5 6 7
I/O 8
I/O 9
I/O 10
I/O
C341-2
1
11
C341-3
Design Security (continued)
The CY7C341 is fully functionally tested and guaranteed through complete testing of each programmable EPROM bit and all internal logic elements thus ensuring 100% programming yield.
The erasable nature of these devices allows test programs to be used and erased during early stages of the production flow. The devices also contain on-board logic test circuitry to allow verification of function and AC specification once encapsulated in non-windowed packages.
EXPANDER DELAY tEXP LOGIC ARRAY CONTROL DELAY tLAC LOGIC ARRAY DELAY tLAD
REGISTER tCLR tPRE tRSU tRH tCOMB tLATCH tRD OUTPUT DELAY tOD tXZ tZX INPUT/ OUTPUT
INPUT
INPUT DELAY tIN
SYSTEM CLOCK DELAY tICS PIA DELAY tPIA CLOCK DELAY tIC LOGIC ARRAY DELAY tFD I/O DELAY tIO
C341-4
Figure 1. CY7C341 Internal Timing Model
4
CY7C341
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .......................................-65C to +150C Ambient Temperature with Power Applied .................................................... 0C to +70C Maximum Junction Temperature (Under Bias)................................................................. 150C Supply Voltage to Ground Potential..................-2.0V to +7.0V Maximum Power Dissipation................................... 2500 mW DC VCC or GND Current......................................................500 mA DC Output Current, per Pin ........................ -25 mA to +25 mA DC Input Voltage[1] ................................................-3.0V to +7.0V DC Program Voltage..................................................... 13.0V Static Discharge Voltage................................................. >1100V (per MIL-STD-883, method 3015)
Operating Range
Range Commercial Industrial Military Ambient Temperature 0C to +70C -40C to +85C -55C to +125C (Case) VCC 5V 5% 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range[2]
Parameter VOH VOL VIH VIL IIX IOZ IOS ICC1 ICC2 tR (Recommended) tF (Recommended) Description Output HIGH Voltage Output LOW Voltage Input HIGH Level Input LOW Level Input Current Output Leakage Current Output Short Circuit Current Power Supply Current (Standby) Power Supply Current[5] Input Rise Time Input Fall Time GND VIN VCC VO = VCC or GND VCC = Max., VOUT = GND VI = VCC or GND (No Load) VI = VCC or GND (No Load) f = 1.0 MHz[3, 5]
[3, 4]
Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8 mA
Min. 2.4
Max. 0.45
Unit V V V V A A mA mA mA mA mA ns ns
2.2 -0.3 -10 -40 -30 Com'l Mil/Ind Com'l Mil/Ind
VCC+0.3 0.8 +10 +40 -90 360 435 380 480 100 100
Capacitance[6]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 10 20 Unit pF pF
Notes: 1. Minimum DC input is -0.3V. During transitions, the inputs may undershoot to -2.0V for periods less than 20 ns. 2. Typical values are for TA = 25C and VCC = 5V. 3. Guaranteed but not 100% tested. 4. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 5. This parameter is measured with device programmed as a 16-bit counter in each LAB and is tested periodically by sampling production material. 6. Part (a) in AC Test Load and Waveforms is used for all parameters except tER and tXZ, which is used for part (b) in AC Test Load and Waveforms. All external timing parameters are measured referenced to external pins of the device.
5
CY7C341
AC Test Loads and Waveforms
5V OUTPUT 50 pF INCLUDING JIG AND SCOPE (a) Equivalent to: R2 250 R1 464 5V OUTPUT 5 pF R2 250 R1 464 3.0V GND < 6 ns tR tF
C341-6
ALL INPUT PULSES 90% 10% 90% 10% < 6 ns
(b)
C341-5
THEVENIN EQUIVALENT (commercial/military) 163 OUTPUT 1.75V
External Synchronous Switching Characteristics Over the Operating Range[6] 7C341-25 Parameter tPD1 tPD2 tPD3 tPD4 tEA tER tCO1 tCO2 Description Dedicated Input to Combinatorial Output Delay[7] I/O Input to Combinatorial Output Delay[8] Com'l Mil Com'l Mil Min. Max 25 25 40 40 37 37 52 52 25 25 25 25 14 14 30 30 15 15 30 30 20 20 39 39 7C341-30 Min. Max 30 30 45 45 44 44 59 59 30 30 30 30 16 16 35 35 25 25 45 45 ns 7C341-35 Min. Max 35 35 55 55 55 55 75 75 35 35 35 35 20 20 42 42 ns ns ns ns ns ns ns ns Unit ns
Dedicated Input to Combinatorial Com'l Output Delay with Expander Delay[9] Mil I/O Input to Combinatorial Output Delay with Expander Delay[3, 10] Input to Output Enable Delay
[3, 7]
Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil
Input to Output Disable Delay[6] Synchronous Clock Input to Output Delay Synchronous Clock to Local Feedback to Combinatorial Output[3, 11]
tS1
Dedicated Input or Feedback Set-up Com'l Time to Synchronous Clock Mil Output[6, 12] I/O Input Set-up Time to Synchronous Clock Input[8] Com'l Mil
tS2
Notes: 7. This specification is a measure of the delay from input signal applied to a dedicated input to combinatorial output on any output pin. This delay assumes no expander terms are used to form the logic function. When this note is applied to any parameter specification it indicates that the signal (data, asynchronous clock, asynchronous clear, and/or asynchronous preset) is applied to a dedicated input only and no signal path (either clock or data) employs expander logic. If an input signal is applied to an I/O pin an additional delay equal to tPIA should be added to the comparable delay for a dedicated input. If expanders are used, add the maximum expander delay tEXP to the overall delay for the comparable delay without expanders. 8. This specification is a measure of the delay from input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to form the logic function. 9. This specification is a measure of the delay from an input signal applied to a dedicated input to combinatorial output on any output pin. This delay assumes expander terms are used to form the logic functions and includes the worst-case expander logic delay for one pass through the expander logic. 10. This specification is a measure of the delay from an input signal applied to an I/O macrocell pin to any output. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling production material. 11. This specification is a measure of the delay from synchronous register clock to internal feedback of the register output signal to the input of the LAB logic array and then to a combinatorial output. This delay assumes no expanders are used, register is synchronously clocked and all feedback is within the same LAB. This parameter is tested periodically by sampling production material. 12. If data is applied to an I/O input for capture by a macrocell register, the I/O pin set-up time minimums should be observed. These parameters are tS2 for synchronous operation and tAS2 for asynchronous operation.
6
CY7C341
External Synchronous Switching Characteristics Over the Operating Range[6] (continued) 7C341-25 Parameter tH tWH tWL tRW tRO tRR tPW tPR tPO tCF tP fMAX1 fMAX2 Description Input Hold Time from Synchronous Clock Input[6] Synchronous Clock Input High Time Synchronous Clock Input Low Time Asynchronous Clear Width[3, 6] Asynchronous Clear to Registered Output Delay[5] Asynchronous Clear Recovery[3, 7] Asynchronous Preset Width [3, 6] Asynchronous Preset Recovery Time[3, 6] Asynchronous Preset to Registered Output Delay[6] Synchronous Clock to Local Feedback Input[3, 13] External Synchronous Clock Period (1/fMAX3)[3] External Feedback Maximum Frequency (1/(tCO1 + tS1))[3, 14] Internal Local Feedback Maximum Frequency, lesser of (1/(tS1 + tCF)) or (1/tCO1)[3, 15] Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil 16 16 34.5 34.5 55.5 55.5 62.5 62.5 62.5 62.5 3 3 25 25 25 25 25 25 25 25 3 3 20 20 27.7 27.7 43 43 50 50 50 50 3 3 Min. 0 0 8 8 8 8 25 25 25 25 30 30 30 30 30 30 30 30 3 3 25 25 22.2 22.2 33 33 40.0 40.0 40.0 40.0 3 3 ns MHz MHz MHz MHz Max 7C341-30 Min. 0 0 10 10 10 10 30 30 30 30 35 35 35 35 35 35 35 35 5 5 ns ns ns ns ns Max 7C341-35 Min. 0 0 12.5 12.5 12.5 12.5 35 35 35 35 ns ns ns ns ns Max Unit ns
fMAX3
Data Path Maximum Frequency, least Com'l of 1/(tWL + tWH), 1/(tS1 + tH), or (1/tCO1)[3, Mil 16] Maximum Register Toggle Frequency Com'l (1/(tWL + tWH))[3, 17] Mil Output Data Stable Time from Synchronous Clock Input[3, 18] Com'l Mil
fMAX4 tOH
Notes: 13. This specification is a measure of the delay associated with the internal register feedback path. This is the delay from synchronous clock to LAB logic array input. This delay plus the register set-up time, tS1, is the minimum internal period for an internal synchronous state machine configuration. This delay is for feedback within the same LAB. This parameter is tested periodically by sampling production material. 14. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration with external feedback can operate. It is assumed that all data inputs and feedback signals are applied to dedicated inputs. All feedback is assumed to be local originating within the same LAB. 15. This specification indicates the guaranteed maximum frequency at which a state machine, with internal-only feedback, can operate. If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tCO1. 16. This frequency indicates the maximum frequency at which the device may operate in data path mode (dedicated input pin to output pin). This assumes data input signals are applied to dedicated input pins and no expander logic is used. If any of the data inputs are I/O pins, tS2 is the appropriate tS for calculation. 17. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycle by a clock signal applied to the dedicated clock input pin. 18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.
7
CY7C341
External Synchronous Switching Characteristics Over the Operating Range[6] (continued) 7C341-25 Parameter tACO1 tACO2 tAS1 tAS2 tAH tAWH tAWL tACF tAP fMAXA1 Description Dedicated Asynchronous Clock Input Com'l to Output Delay[6] Mil Asynchronous Clock Input to Local Com'l Feedback to Combinatorial Output[19] Mil Dedicated Input or Feedback Set-up Com'l Time to Asynchronous Clock Input[6] Mil I/O Input Set-Up Time to Asynchronous Clock Input[6] Input Hold Time from Asynchronous Clock Input[6] Asynchronous Clock Input HIGH Time[6] Asynchronous Clock Input LOW Time[6, 20] Asynchronous Clock to Local Feedback Input[21] External Asynchronous Clock Period (1/fMAX4) External Feedback Maximum Frequency in Asynchronous Mode 1/(tACO1 + tAS1)[22] Maximum Internal Asynchronous Frequency[23] Data Path Maximum Frequency in Asynchronous Mode[24] Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil 20 20 33.3 33.3 50 50 40 40 50 50 15 15 5 5 20 20 6 6 11 11 9 9 15 15 25 25 27 27 40 40 33.3 33.3 40 40 15 15 Min. Max 25 25 40 40 6 6 27 27 8 8 14 14 11 11 18 18 30 30 23 23 33.3 33.3 28.5 28.5 33.3 33.3 15 15 ns MHz MHz MHz MHz 7C341-30 Min. Max 30 30 46 46 8 8 30 30 10 10 16 16 14 14 22 22 ns ns ns ns ns ns 7C341-35 Min. Max 35 35 55 55 ns ns Unit ns
fMAXA2 fMAXA3 fMAXA4 tAOH
Maximum Asynchronous Register Com'l Toggle Frequency 1/(tAWH + tAWL)[25] Mil Output Data Stable Time from Asyn- Com'l chronous Clock Input[26] Mil
Notes: 19. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register output signal to the input of the LAB logic array and then to a combinatorial output. This delay assumes no expanders are used in the logic of combinatorial output or the asynchronous clock input. The clock signal is applied to the dedicated clock input pin and all feedback is within a single LAB. This parameter is tested periodically by sampling production material. 20. This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge triggering, the tAWH and tAWL parameters must be swapped. If a given input is used to clock multiple registers with both positive and negative polarity, tAWH should be used for both tAWH and tAWL. 21. This specification is a measure of the delay associated with the internal register feedback path for an asynchronous clock to LAB logic array input. This delay plus the asynchronous register set-up time, tAS1, is the minimum internal period for an internal asynchronously clocked state machine configuration. This delay is for feedback within the same LAB, and assumes there is no expander logic in the clock path and the clock input signal is applied to a dedicated input pin. This parameter is tested periodically by sampling production material. 22. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can operate. It is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs, and that no expander logic is employed in the clock signal path or data path. 23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate. This parameter is determined by the lesser of (1/tACF + tAS1)) or (1/(tAWH +tAWL)). If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tACO1. 24. This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. This specification is determined by the least of 1/(tAWH + tAWL), 1/(tAS1 + tAH) or 1/tACO1. It assumes data and clock input signals are applied to dedicated input pins and no expander logic is used. 25. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode by a clock signal applied to an external dedicated input pin. 26. This parameter indicates the minimum time that the previous register output data is maintained on the output after an asynchronous register clock input applied to an external dedicated input pin.
8
CY7C341
Internal Switching Characteristics Over the Operating Range[2]
7C341-25 Parameter tIN tIO tEXP tLAD tLAC tOD tZX tXZ tRSU tRH tLATCH tRD tCOMB tCH tCL tIC tICS tFD tPRE tCLR Description Dedicated Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Expander Array Delay Logic Array Data Delay Logic Array Control Delay Output Buffer and Pad Delay Output Buffer Enable Delay
[27]
7C341-30 Min. Max 7 7 6 6 14 14 14 14 12 12 5 5 11 11 11 11 8 8 8 8
7C341-35 Min. Max 9 9 9 9 20 20 16 16 13 13 6 6 13 13 13 13 10 10 10 10 ns 4 4 2 2 4 4 12.5 12.5 12.5 12.5 ns 18 18 3 3 2 2 7 7 7 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit ns
Min. Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil Com'l Mil 6 6 6 6
Max 5 5 6 6 12 12 12 12 10 10 5 5 10 10 10 10
Output Buffer Disable Delay Register Set-Up Time Relative to Clock Signal at Register Register Hold Time Relative to Clock Signal at Register Flow-Through Latch Delay Register Delay Transparent Mode Delay Clock High Time Clock Low Time
[28]
3 3 1 1 3 3 8 8 8 8 14 14 2 2 1 1 5 5 5 5 10 10 10 10
4 4 2 2 4 4
Com'l Mil Com'l Mil Com'l Mil
Asynchronous Clock Logic Delay Com'l Mil Synchronous Clock Delay Feedback Delay Asynchronous Register Preset Time Asynchronous Register Clear Time Com'l Mil Com'l Mil Com'l Mil Com'l Mil
16 16 2 2 1 1 6 6 6 6
9
CY7C341
Internal Switching Characteristics Over the Operating Range[2] (continued)
7C341-25 Parameter tPCW tPCR tPIA Description Asynchronous Preset and Clear Pulse Width Asynchronous Preset and Clear Recovery Time Programmable Interconnect Array Delay Com'l Mil Com'l Mil Com'l Mil Min. 5 5 5 5 14 Max 7C341-30 Min. 6 6 6 6 16 16 Max 7C341-35 Min. 7 7 7 7 20 20 ns ns Max Unit ns
Notes: 27. Sample tested only for an output change of 500 mV. 28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial operation.
Switching Waveforms
External Combinatorial
DEDICATED INPUT/ I/O INPUT tPD1/tPD2 COMBINATORIAL OUTPUT
tER
COMBINATORIAL REGISTERED OUTPUT HIGH IMPEDANCE 3-STATE HIGH-IMPEDANCE 3-ST ATE
tEA
VALID OUTPUT
C341-7
External Synchronous
DEDICATED INPUT/ I/O INPUT [7] tS1 SYNCHRONOUS CLOCK tCO1 ASYNCHRONOUS CLEAR/PRESET [7] REGISTERED OUTPUTS tCO2 COMBINATORIAL OUTPUT FROM REGISTERED FEEDBACK[10]
C341-8
tH
tWH
tWL
tRW/tPW
tRR/tPR
tOH tRO/tPO
10
CY7C341
Switching Waveforms (continued)
External Asynchronous
DEDICATEDINPUT/ I/OINPUT[7] tAS1 ASYNCHRONOUS CLOCK INPUT tACO1 ASYNCHRONOUS CLEAR/PRESET [7] ASYNCHRONOUS REGISTERED OUTPUTS tACO2 COMBINATORIAL OUTPUT FROM ASYNCH. REGISTERED FEEDBACK tAOH tRO/tPO tRW/tPW tRR/tPR tAH tAWH tAWL
C341-9
Internal Combinatorial
tIN INPUT PIN tIO I/O PIN tEXP EXPANDER ARRAY DELAY tLAC, tLAD LOGIC ARRAY INPUT tPIA
LOGIC ARRAY OUTPUT
C341-10
11
CY7C341
Switching Waveforms (continued)
Internal Asynchronous
tIOR t CLOCK PIN tIN CLOCK INTO LOGIC ARRAY CLOCK FROM LOGIC ARRAY DATA FROM LOGIC ARRAY tRD,tLATCH REGISTER OUTPUT TO LOCAL LAB LOGIC ARRAY tPIA REGISTER OUTPUT TO ANOTHER LAB
C341-11
tAWH
tAWL
tF
tIC
tRSU
tRH
tFD
tCLR,tPRE
tFD
Internal Synchronous
tCH SYSTEM CL OCK PIN tIH SYSTEM CLOCK AT REGISTER DATA FROM LOGIC ARRAY
C341-12
tCL
tICS
tRSU
tRH
Internal Synchronous
CLOCK FROM LOGIC ARRAY DATA FROM LOGIC ARRAY
tRD
tOD
tXZ OUTPUT PIN
tXZ tZX HIGH IMPEDANCE STATE
C341-13
12
CY7C341
Ordering Information
Speed (ns) 25 Ordering Code CY7C341-25HC/HI CY7C341-25JC/JI CY7C341-25RC/RI 30 CY7C341-30HC/HI CY7C341-30JC/JI CY7C341-30RC/RI CY7C341-30HMB CY7C341-30RMB 35 CY7C341-35HC/HI CY7C341-35JC/JI CY7C341-35RC/RI CY7C341-35HMB CY7C341-35RMB Package Name H84 J83 R84 H84 J83 R84 H84 R84 H84 J83 R84 H84 R84 Package Type 84-Lead Windowed Leaded Chip Carrier 84-Lead Plastic Leaded Chip Carrier 84-Lead Windowed Pin Grid Array 84-Lead Windowed Leaded Chip Carrier 84-Lead Plastic Leaded Chip Carrier 84-Lead Windowed Pin Grid Array 84-Lead Windowed Leaded Chip Carrier 84-Lead Windowed Pin Grid Array 84-Lead Windowed Leaded Chip Carrier 84-Lead Plastic Leaded Chip Carrier 84-Lead Windowed Pin Grid Array 84-Lead Windowed Leaded Chip Carrier 84-Lead Windowed Pin Grid Array Military Commercial/Industrial Military Commercial/Industrial Operating Range Commercial/Industrial
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameter VOH VOL VIH VIL IIX IOZ ICC1 Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
Switching Characteristics
Parameter tPD1 tPD2 tPD3 tCO1 tS1 tH tACO1 tACO2 tAS1 tAH Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11
Document #: 38-00499-A
13
CY7C341
Package Diagrams
84-Leaded Windowed Leaded Chip Carrier H84
51-80081
14
CY7C341
Package Diagrams (continued)
84-Lead Plastic Leaded Chip Carrier J83
51-85006-A
84-Lead Windowed Pin Grid Array R84
51-80026-A
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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