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CY7C343
64-Macrocell MAX(R) EPLD
Features
* * * * * * 64 MAX macrocells in 4 LABs 8 dedicated inputs, 24 bidirectional I/O pins Programmable interconnect array 0.8-micron double-metal CMOS EPROM technology Available in 44-pin HLCC, PLCC Lowest power MAX device The CY7C343 contains 64 highly flexible macrocells and 128 expander product terms. These resources are divided into four Logic Array Blocks (LABs) connected through the Programmable Inter-connect Array (PIA). There are 8 input pins, one that doubles as a clock pin when needed. The CY7C343 also has 28 I/O pins, each connected to a macrocell (6 for LABs A and C, and 8 for LABs B and D). The remaining 36 macrocells are used for embedded logic. The CY7C343 is excellent for a wide range of both synchronous and asynchronous applications.
Functional Description
The CY7C343 is a high-performance, high-density erasable programmable logic device, available in 44-pin PLCC and HLCC packages.
Logic Block Diagram
9 INPUT 11 INPUT 12 INPUT 13 INPUT DEDICATED INPUTS SYSTEM CLOCK LAB A 2 4 5 6 7 8 MACROCELL1 MACROCELL2 MACROCELL3 MACROCELL4 MACROCELL5 MACROCELL6 MACROCELLS 7-16 LAB D MACROCELL56 MACROCELL55 MACROCELL54 MACROCELL53 MACROCELL52 MACROCELL51 MACROCELL50 MACROCELL49 1 44 42 41 40 39 38 37 INPUT 35 INPUT/CLK 34 INPUT 33 INPUT 31
I/O PINS
I/O PINS
LAB B 15 16 17 18 19 20 22 23 MACROCELL17 MACROCELL18 MACROCELL19 MACROCELL20 MACROCELL21 MACROCELL22 MACROCELL23 MACROCELL24 MACROCELLS 25-32 (3, 14, 25, 36) (10, 21, 32, 43)
P I A
MACROCELLS 57-64 LAB C MACROCELL38 MACROCELL37 MACROCELL36 MACROCELL35 MACROCELL34 MACROCELL33
I/O PINS
30 29 28 27 26 24
I/O PINS
MACROCELLS 39-48
VCC GND
C343-1
MAX is a registered trademark of Altera Corporation. Warp2 and Warp3 are registered trademarks of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
* 408-943-2600 December 9, 1999
CY7C343
Selection Guide
7C343-20 Maximum Access Time (ns) Maximum Operating Current (mA) Commercial Military Industrial Maximum Standby Current (mA) Commercial Military Industrial 20 135 225 225 125 200 200 7C343-25 25 135 225 225 125 200 200 7C343-30 30 135 225 225 125 200 200 7C343-35 35 135 225 225 125 200 200
Pin Configuration
HLCC, PLCC Top View
GND V CC I/O I/O I/O I/O I/O I/O I/O I/O I/O
6 I/O I/O INPUT GND INPUT INPUT INPUT VCC I/O I/O I/O 7 8 9 10 11 12 13 14 15 16 17
5
4
3
2
1
44 43 42 41 40 39 38 37 36 35 34 33 32 I/O I/O I/O VCC INPUT INPUT/CLK INPUT GND INPUT I/O I/O
7C343
31 30 29
18 19 20 21 22 23 24 25 26 27 28 GND I/O I/O I/O I/O I/O I/O I/O I/O V CC I/O C343-2
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to+150C Ambient Temperature with Power Applied ................................................... 0C to+70C Maximum Junction Temperature (Under Bias)................................................................. 150C Supply Voltage to Ground Potential ............... -2.0V to +7.0V Maximum Power Dissipation................................... 2500 mW DC VCC or GND Current ............................................ 500 mA
DC Output Current, per Pin ......................-25 mA to +25 mA DC Input Voltage[1] .........................................-3.0V to +7.0V DC Program Voltage..................................................... 13.0V Static Discharge Voltage ........................................... >1100V (per MIL-STD-883, method 3015)
Operating Range
Range Commercial Industrial Military Ambient Temperature 0C to +70C -40C to +85C -55C to +125C (Case) VCC 5V 5% 5V 10% 5V 10%
Note: 1. Minimum DC input is -0.3V. During transitions, the inputs may undershoot to -2.0V for periods less than 20 ns.
2
CY7C343
Electrical Characteristics Over the Operating Range[2]
Parameter VOH VOL VIH VIL IIX IOZ IOS ICC1 ICC2 tR tF Description Output HIGH Voltage Output LOW Voltage Input HIGH Level Input LOW Level Input Current Output Leakage Current Output Short Circuit Current Power Supply Current (Standby) Power Supply Current
[5]
Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8 mA
Min. 2.4
Max. 0.45
Unit V V V V A A mA mA mA mA mA ns ns
2.2 -0.3 GND < V IN < VCC VO = VCC or GND VCC = Max., VOUT = 0.5V[3, 4] VI = V CC or GND (No Load) VI = V CC or GND (No Load) f = 1.0 MHz[4, 5] Commercial Military/Industrial Commercial Military/Industrial -10 -40 -30
VCC+0.3 0.8 +10 +40 -90 125 200 135 225 100 100
Recommended Input Rise Time Recommended Input Fall Time
Capacitance[6]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions VIN = 2V, f = 1.0 MHz VOUT = 2.0V, f = 1.0 MHz Max. 10 10 Unit pF pF
AC Test Loads and Waveforms[6]
R1 464 5V OUTPUT 50 pF INCLUDING JIG AND SCOPE R2 250 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 250 3.0V 10% GND < 6 ns R1 464 ALLINPUTPULSES 90% 90% 10% < 6 ns
C343-4
C343-3
(a)
(b)
Equivalent to: OUTPUT
THEVENIN EQUIVALENT (commercial/military) 163 1.75V
Notes: 2. Typical values are for TA = 25C and VCC = 5V. 3. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 4. Guaranteed but not 100% tested. 5. Measured with device programmed as a 16-bit counter in each LAB. This parameter is tested periodically by sampling production material. 6. Part (a) in AC Test Load and Waveforms is used for all parameters except tER and tXZ, which is used for part (b) in AC Test Load and Waveforms. All external timing parameters are measured referenced to external pins of the device.
3
CY7C343
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves interconnect limitations by routing only the signals needed by each logic array block. The inputs to the PIA are the outputs of every macrocell within the device and the I/O pin feedback of every pin on the device. Unlike masked or programmable gate arrays, which induce variable delay dependent on routing, the PIA has a fixed delay. This eliminates undesired skews among logic signals, which may cause glitches in internal or external logic. The fixed delay, regardless of programmable interconnect array configuration, simplifies design by ensuring that internal signal skews or races are avoided. The result is simpler design implementation, often in a single pass, without the multiple internal logic placement and routing iterations required for a programmable gate array to achieve design timing objectives.
Timing Considerations
Unless otherwise stated, propagation delays do not include expanders. When using expanders, add the maximum expander delay tEXP to the overall delay. Similarly, there is an additional tPIA delay for an input from an I/O pin when compared to a signal from a straight input pin. When calculating synchronous frequencies, use tS1 if all inputs are on the input pins. tS2 should be used if data is applied at an I/O pin. If tS2 is greater than tCO1, 1/tS2 becomes the limiting frequency in the data path mode unless 1/(tWH + tWL) is less than 1/tS2. When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tS1. Determine which of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tS1) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for the synchronous configuration. When calculating external asynchronous frequencies, use tAS1 if all inputs are on dedicated input pins. If any data is applied to an I/O pin, tAS2 must be used as the required set-up time. If (tAS2 + tAH) is greater than tACO1, 1/(tAS2 + tAH) becomes the limiting frequency in the data path mode unless 1/(tAWH + tAH) is less than 1/(tAS2 + tAH). When expander logic is used in the data path, add the appropriate maximum expander delay, tEXP to tAS1. Determine which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the lowest frequency. The lowest of these frequencies is the maximum data path frequency for the asynchronous configuration. The parameter tOH indicates the system compatibility of this device when driving other synchronous logic with positive input hold times, which is controlled by the same synchronous clock. If tOH is greater than the minimum required input hold time of the subsequent synchronous logic, then the devices are guaranteed to function properly with a common synchronous clock under worst-case environmental and supply voltage conditions. The parameter tAOH indicates the system compatibility of this device when driving subsequent registered logic with a positive hold time and using the same clock as the CY7C343. In general, if tAOH is greater than the minimum required input hold time of the subsequent logic (synchronous or asynchronous), then the devices are guaranteed to function properly under worst-case environmental and supply voltage conditions, provided the clock signal source is the same. This also applies if expander logic is used in the clock signal path of the driving device, but not for the driven device. This is due to the expander logic in the second device's clock signal path adding an additional delay (tEXP), causing the output data from the preceding device to change prior to the arrival of the clock signal at the following device's register.
Timing Delays
Timing delays within the CY7C343 may be easily determined using Warp2(R) or Warp3(R) software or by the model shown in Figure 1. The CY7C343 has fixed internal delays, allowing the user to determine the worst case timing delays for any design. For complete timing information, the Warp3 software provides a timing simulator.
Design Recommendations
Operation of the devices described herein with conditions above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. The CY7C343 contains circuitry to protect device pins from high static voltages or electric fields; however, normal precautions should be taken to avoid applying any voltage higher than maximum rated voltages. For proper operation, input and output pins must be constrained to the range GND < (VIN or VOUT) < VCC. Unused inputs must always be tied to an appropriate logic level (either VCC or GND). Each set of VCC and GND pins must be connected together directly at the device. Power supply decoupling capacitors of at least 0.2 F must be connected between VCC and GND. For the most effective decoupling, each VCC pin should be separately decoupled to GND, directly at the device. Decoupling capacitors should have good frequency response, such as monolithic ceramic types.
4
CY7C343
EXPANDER DELAY tEXP
REGISTER OUTPUT DELAY tOD tXZ tZX
INPUT INPUT DELAY tIN
LOGIC ARRAY CONTROL DELAY tLAC LOGIC ARRAY DELAY tLAD
tCLR tPRE tRSU tRH tRD tCOMB tLATCH
INPUT/ OUTPUT
SYSTEM CLOCK DELAY tICS PIA DELAY tPIA CLOCK DELAY tIC
FEEDBACK DELAY tFD
I/O DELAY tIO
C343-5
Figure 1. CY7C343 Internal Timing Model
5
CY7C343
External Synchronous Switching Characteristics[6] Over Operating Range
7C343-20 Parameter tPD1 tPD2 tPD3 tPD4 tEA tER tCO1 tCO2 tS1 tS2 tH tWH tWL tRW tRR tRO tPR tPO tCF tP Description Dedicated Input to Combinatorial Output Delay[7] I/O Input to Combinatorial Output Delay[8] Dedicated Input to Combinatorial Output Delay with Expander Delay[9] I/O Input to Combinatorial Output Delay with Expander Delay[4, 10] Input to Output Enable Delay
[4, 7]
7C343-25 Min. Max. 25 25 39 39 37 37 51 51 25 25 25 25 14 14 30 30 15 15 30 30 0 0 8 8 8 8 25 25 25 25 ns 25 25 25 25 ns 25 25 3 3 16 16 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit ns
Min. Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil
[4, 7]
Max. 20 20 32 32 30 30 42 42 20 20 20 20 12 12 25
Input to Output Disable Delay[4, 7] Synchronous Clock Input to Output Delay Synchronous Clock to Local Feedback to Combinatorial Output[4, 11] Dedicated Input or Feedback Set-Up Time to Synchronous Clock Input[7] I/O Input Set-Up Time to Synchronous Clock Input[7, 12] Input Hold Time from Synchronous Clock Input[7] Synchronous Clock Input HIGH Time Synchronous Clock Input LOW Time Asynchronous Clear Width[4, 7] Asynchronous Clear Recovery Time
12 24 24 0 0 6 6 6 6 20 20 20 20 20 20 20 20 20 20 3 3 12 12
Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil
Asynchronous Clear to Registered Output Delay[7] Asynchronous Preset Recovery Time
[4, 7]
Asynchronous Preset to Registered Output Delay[7] Synchronous Clock to Local Feedback Input[4, 13] External Synchronous Clock Period (1/fMAX3)[4]
6
CY7C343
External Synchronous Switching Characteristics[6] Over Operating Range (continued)
7C343-20 Parameter fMAX1 fMAX2 fMAX3 fMAX4 tOH tPW Description External Maximum Frequency (1/(tCO1 + tS1))[4, 14] Com'l/Ind Mil Min. 41.6 41.6 66.6 66.6 83.3 83.3 83.3 83.3 3 3 20 20 Max. 7C343-25 Min. 34 34 55 55 62.5 62.5 62.5 62.5 3 3 25 25 ns ns MHz MHz MHz Max. Unit MHz
Internal Local Feedback Maximum Frequen- Com'l/Ind cy, lesser of (1/(tS1 + tCF)) or (1/tCO1)[4, 15] Mil Data Path Maximum Frequency, least of 1/(tWL + tWH), 1/(tS1 + tH), or (1/tCO1)[4, 16] Maximum Register Toggle Frequency (1/(tWL+tWH))[4, 17] Output Data Stable Time from Synchronous Clock Input[4, 18] Asynchronous Preset Width
[4, 7]
Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil
Notes: 7. This specification is a measure of the delay from input signal applied to a dedicated input (44-pin PLCC input pin 9, 11, 12, 13, 31, 33, 34, or 35) to combinatorial output on any output pin. This delay assumes no expander terms are used to form the logic function. When this note is applied to any parameter specification it indicates that the signal (data, asynchronous clock, asynchronous clear, and/or asynchronous preset) is applied to a dedicated input only and no signal path (either clock or data) employs expander logic. If an input signal is applied to an I/O pin, an additional delay equal to tPIA should be added to the comparable delay for a dedicated input. If expanders are used, add the maximum expander delay tEXP to the overall delay for the comparable delay without expanders. 8. This specification is a measure of the delay from input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to form the logic function. 9. This specification is a measure of the delay from an input signal applied to a dedicated input (44-pin PLCC input pin 9, 11, 12, 13, 31, 33, 34, or 35) to combinatorial output on any output pin. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling production material. 10. This specification is a measure of the delay from an input signal applied to an I/O macrocell pin to any output. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling production material. 11. This specification is a measure of the delay from synchronous register clock to internal feedback of the register output signal to the input of the LAB logic array and then to a combinatorial output. This delay assumes no expanders are used, register is synchronously clocked and all feedback is within the same LAB. This parameter is tested periodically by sampling production material. 12. If data is applied to an I/O input for capture by a macrocell register, the I/O pin set-up time minimums should be observed. These parameters are tS2 for synchronous operation and tAS2 for asynchronous operation. 13. This specification is a measure of the delay associated with the internal register feedback path. This is the delay from synchronous clock to LAB logic array input. This delay plus the register set-up time, tS1, is the minimum internal period for an internal synchronous state machine configuration. This delay is for feedback within the same LAB. This parameter is tested periodically by sampling production material. 14. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration with external feedback can operate. It is assumed that all data inputs and feedback signals are applied to dedicated inputs. 15. This specification indicates the guaranteed maximum frequency at which a state machine, with internal-only feedback, can operate. If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tCO1. All feedback is assumed to be local, originating within the same LAB.. 16. This frequency indicates the maximum frequency at which the device may operate in data path mode. This delay assumes data input signals are applied to dedicated inputs and no expander logic is used. 17. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycled. 18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.
7
CY7C343
External Synchronous Switching Characteristics[6] Over Operating Range (continued)
7C343-30 Parameter tPD1 tPD2 tPD3 tPD4 tEA tER tCO1 tCO2 tS1 tS2 tH tWH tWL tRW tRR tRO tPR tPO tCF tP Description Dedicated Input to Combinatorial Output Delay[7] I/O Input to Combinatorial Output Delay[8] Dedicated Input to Combinatorial Output Delay with Expander Delay[9] I/O Input to Combinatorial Output Delay with Expander Delay[4, 10] Input to Output Enable Delay
[4, 7]
7C343-35 Min. Max. 35 35 53 53 55 55 73 73 35 35 35 35 20 20 42 42 25 25 42 42 0 0 12.5 12.5 12.5 12.5 35 35 35 35 ns 35 35 35 35 ns 35 35 5 5 25 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit ns
Min. Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil
[4, 7]
Max. 30 30 44 44 44 44 58 58 30 30 30 30 16 16 35 35
Input to Output Disable Delay[4, 7] Synchronous Clock Input to Output Delay Synchronous Clock to Local Feedback to Combinatorial Output[4, 11] Dedicated Input or Feedback Set-Up Time to Synchronous Clock Input[7] I/O Input Set-Up Time to Synchronous Clock Input[7, 12] Input Hold Time from Synchronous Clock Input[7] Synchronous Clock Input HIGH Time Synchronous Clock Input LOW Time Asynchronous Clear Width[4, 7] Asynchronous Clear Recovery Time
20 20 35 35 0 0 10 10 10 10 30 30 30 30 30 30 30 30 30 30 3 3 20 20
Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil
Asynchronous Clear to Registered Output Delay[7] Asynchronous Preset Recovery Time
[4, 7]
Asynchronous Preset to Registered Output Delay[7] Synchronous Clock to Local Feedback Input[4, 13] External Synchronous Clock Period (1/fMAX3)[4]
8
CY7C343
External Synchronous Switching Characteristics[6] Over Operating Range (continued)
7C343-30 Parameter fMAX1 fMAX2 fMAX3 fMAX4 tOH tPW Description External Maximum Frequency (1/(tCO1 + tS1))[4, 14] Com'l/Ind Mil Min. 27 27 43 43 50 50 50 50 3 3 30 30 Max. 7C343-35 Min. 22.2 22.2 33 33 40 40 40 40 3 3 35 35 ns ns MHz MHz MHz Max. Unit MHz
Internal Local Feedback Maximum Frequen- Com'l/Ind cy, lesser of (1/(tS1 + tCF)) or (1/tCO1)[4, 15] Mil Data Path Maximum Frequency, least of 1/(tWL + tWH), 1/(tS1 + tH), or (1/tCO1)[4, 16] Maximum Register Toggle Frequency (1/(tWL+tWH))[4, 17] Output Data Stable Time from Synchronous Clock Input[4, 18] Asynchronous Preset Width
[4, 7]
Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil
External Asynchronous Switching Characteristics Over Operating Range[6]
7C343-20 Parameter tACO1 tACO2 tAS1 tAS2 tAH tAWH tAWL tACF tAP fMAXA1 fMAXA2 fMAXA3 Description Asynchronous Clock Input to Output Delay
[7]
7C343-25 Min. 12 25 25 40 40 5 5 20 20 6 6 11 11 ns ns 15 15 20 20 33 50 50 MHz MHz MHz ns ns ns ns ns Max. Unit ns ns
Min. Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil 16 16 41.6 41.6 58.8 58.8 50 50 4 4 15 15 5 5 9 9 7 7
Max. 20 20 32 32
Asynchronous Clock Input to Local Feedback to Combinatorial Output[19] Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input[7] I/O Input Set-Up Time to Asynchronous Clock Input[7] Input Hold Time from Asynchronous Clock Input[7] Asynchronous Clock Input HIGH Time[7] Asynchronous Clock Input LOW Time
[7, 20]
Asynchronous Clock to Local Feedback Input[4, 21] External Asynchronous Clock Period (1/fMAXA4)[4] External Maximum Frequency in Asynchronous Mode 1/(tACO1 + tAS1)[4, 22] Maximum Internal Asynchronous Frequency[4, 23]
13 13
9 9
Data Path Maximum Frequency in Asynchro- Com'l/Ind nous Mode[4, 24] Mil
9
CY7C343
External Asynchronous Switching Characteristics Over Operating Range[6] (continued)
7C343-20 Parameter fMAXA4 tAOH Description Maximum Asynchronous Register Toggle Frequency 1/(tAWH + tAWL)[4, 25] Output Data Stable Time from Asynchronous Clock Input[4, 26] Com'l/Ind Mil Com'l/Ind Mil Min. 62.5 62.5 12 12 Max. 7C343-25 Min. 40 40 15 15 ns Max. Unit MHz
Notes: 19. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register output signal to the input of the LAB logic array and then to a combinatorial output. This delay assumes no expanders are used in the logic of combinatorial output or the asynchronous clock input. The clock signal is applied to a dedicated input pin and all feedback is within a single LAB. This parameter is tested periodically by sampling production material. 20. This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the tAWH and tAWL parameters must be swapped. If a given input is used to clock multiple registers with both positive and negative polarity, tAWH should be used for both tAWH and tAWL. 21. This specification is a measure of the delay associated with the internal register feedback path for an asynchronous clock to LAB logic array input. This delay plus the asynchronous register set-up time, tAS1, is the minimum internal period for an internal asynchronously clocked state machine configuration. This delay is for feedback within the same LAB, assumes no expander logic in the clock path, and assumes that the clock input signal is applied to a dedicated input pin. This parameter is tested periodically by sampling production material. 22. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can operate. It is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs, and that no expander logic is employed in the clock signal path or data path. 23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate. This parameter is determined by the lesser of (1/tACF + tAS1)) or (1/(tAWH +tAWL)). If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tACO1. 24. This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. This specification is determined by the least of 1/(tAWH + tAWL), 1/(tAS1 + tAH) or 1/tACO1. It assumes data and clock input signals are applied to dedicated input pins and no expander logic is used. 25. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode by a clock signal applied to an external dedicated input pin. 26. This parameter indicates the minimum time that the previous register output data is maintained on the output after an asynchronous register clock input.
External Asynchronous Switching Characteristics Over Operating Range[6]
7C343-30 Parameter tACO1 tACO2 tAS1 tAS2 tAH tAWH tAWL tACF tAP fMAXA1 Description Asynchronous Clock Input to Output Delay Asynchronous Clock Input to Local Feedback to Combinatorial Output[19] Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input[7] I/O Input Set-Up Time to Asynchronous Clock Input[7] Input Hold Time from Asynchronous Clock Input[7] Asynchronous Clock Input HIGH Time
[7] [7]
7C343-35 Min. Max. 35 35 55 55 8 8 30 30 10 10 16 16 14 14 ns 22 22 30 30 23 23 MHz ns ns ns ns ns ns ns Unit ns
Min. Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil 25 25 27 27 6 6 25 25 8 8 14 14 11 11
Max. 30 30 46 46
Asynchronous Clock Input LOW Time[7, 20] Asynchronous Clock to Local Feedback Input[4, 21] External Asynchronous Clock Period (1/fMAXA4)[4] External Maximum Frequency in Asynchronous Mode 1/(tACO1 + tAS1)[4, 22]
18 18
10
CY7C343
External Asynchronous Switching Characteristics Over Operating Range[6] (continued)
7C343-30 Parameter fMAXA2 fMAXA3 fMAXA4 tAOH Description Maximum Internal Asynchronous Frequency[4, 23] Data Path Maximum Frequency in Asynchronous Mode[4, 24] Maximum Asynchronous Register Toggle Frequency 1/(tAWH + tAWL)[4, 25] Output Data Stable Time from Asynchronous Clock Input[4, 26] Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Min. 40 40 33 33 40 40 15 15 Max. 7C343-35 Min. 33 33 28 28 33 33 15 15 ns MHz MHz Max. Unit MHz
Internal Switching Characteristics Over Operating Range[6]
7C343-20 Parameter tIN tIO tEXP tLAD tLAC tOD tZX tXZ tRSU tRH tLATCH tRD tCOMB Description Dedicated Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Expander Array Delay Logic Array Data Delay Logic Array Control Delay Output Buffer and Pad Delay Output Buffer Enable Delay[27] Output Buffer Disable Delay Register Set-Up Time Relative to Clock Signal at Register Register Hold Time Relative to Clock Signal at Register Flow-Through Latch Delay Register Delay Transparent Mode Delay[28] Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/ Ind Mil Com'l/Ind Mil 4 4 4 4 2 2 1 1 2 2 Min. Max. 4 4 4 4 10 10 10 10 8 8 4 4 8 8 8 8 6 6 6 6 3 3 1 1 3 3 ns ns ns ns 7C343-25 Min. Max. 5 5 5 5 12 12 12 12 10 10 5 5 10 10 10 10 ns ns ns ns ns ns ns ns Unit ns
11
CY7C343
Internal Switching Characteristics Over Operating Range[6] (continued)
7C343-20 Parameter tCH tCL tIC tICS tFD tPRE tCLR tPCW tPCR tPIA Clock HIGH Time Clock LOW Time Asynchronous Clock Logic Delay Synchronous Clock Delay Feedback Delay Asynchronous Register Preset Time Asynchronous Register Clear Time Description Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Asynchronous Preset and Clear Pulse Width Com'l /Ind Mil Asynchronous Preset and Clear Recovery Time Programmable Interconnect Array Delay Time Com'l/Ind Mil Com'l/Ind Mil 4 4 4 4 12 12 Min. 6 6 6 6 12 12 2 2 1 1 4 4 4 4 5 5 5 5 14 14 ns ns Max. 7C343-25 Min. 8 8 8 8 14 14 2 2 1 1 5 5 5 5 ns ns ns ns ns ns ns Max. Unit ns
Notes: 27. Sample tested only for an output change of 500 mV. 28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial operation.
Internal Switching Characteristics Over Operating Range[6]
7C343-30 Parameter tIN tIO tEXP tLAD tLAC tOD Description Dedicated Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Expander Array Delay Logic Array Data Delay Logic Array Control Delay Output Buffer and Pad Delay Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Min. Max. 7 7 5 5 14 14 14 14 12 12 5 5 7C343-35 Min. Max. 9 9 7 7 20 20 16 16 13 13 6 6 ns ns ns ns ns Unit ns
12
CY7C343
Internal Switching Characteristics Over Operating Range[6] (continued)
7C343-30 Parameter tZX tXZ tRSU tRH tLATCH tRD tCOMB tCH tCL tIC tICS tFD tPRE tCLR tPCW tPCR tPIA Description Output Buffer Enable Delay
[27]
7C343-35 Min. Max. 13 13 13 13 10 10 12 12 ns 4 4 2 2 4 4 12.5 12.5 12.5 12.5 ns 18 18 3 3 2 2 7 7 7 7 7 7 7 7 ns 20 20 ns ns ns ns ns ns ns ns ns ns ns ns ns Unit ns
Min. Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil Com'l/Ind Mil 6 6 6 6 10 10 10 10 8 8 8 8
Max. 11 11 11 11
Output Buffer Disable Delay Register Set-Up Time Relative to Clock Signal at Register Register Hold Time Relative to Clock Signal at Register Flow-Through Latch Delay Register Delay Transparent Mode Delay[28] Clock HIGH Time Clock LOW Time Asynchronous Clock Logic Delay Synchronous Clock Delay Feedback Delay Asynchronous Register Preset Time Asynchronous Register Clear Time
4 4 2 2 4 4
16 16 2 2 1 1 6 6 6 6
Asynchronous Preset and Clear Pulse Width Com'l/Ind Mil Asynchronous Preset and Clear Recovery Time Programmable Interconnect Array Delay Time Com'l/Ind Mil Com'l/Ind Mil
16 16
13
CY7C343
Switching Waveforms
External Combinatorial
DEDICATED INPUT/ I/O INPUT t PD1 /tPD2 COMBINATORIAL OUTPUT t ER COMBINATORIAL OR REGISTERED OUTPUT HIGH-IMPEDANCE THREE-STATE t ER VALID OUTPUT
C343-6
HIGH-IMPEDANCE THREE-STATE
External Synchronous
DEDICATED INPUTS OR [7] REGISTERED FEEDBACK tS1 SYNCHRONOUS CLOCK tCO1 ASYNCHRONOUS CLEAR/PRESET[7] tOH tRO /tPO REGISTERED OUTPUTS tCO2 COMBINATORIAL OUTPUT FROM REGISTERED FEEDBACK [11]
C343-7
tH
t WH
tWL
tRW /tPW
tRR /tPR
External Asynchronous
DEDICATEDINPUTSOR REGISTERED FEEDBACK [7 ] ASYNCHRONOUS CLOCK INPUT
tAS1
tAH
tAWH
tAWL
tACO1 tAOH
tRW/tPW
tRR/tPR
ASYNCHRONOUS CLEAR/PRESET [7 ]
tRO/tPO ASYNCHRONOUS REGISTERED OUTPUTS tACO2 COMBINATORIAL OUTPUT FROM ASYNCH. REGISTERED FEEDBACK
C343-8
14
CY7C343
Switching Waveforms (continued)
Internal Combinatorial
tIN INPUT PIN tIO I/O PIN tEXP EXPANDER ARRAY DELAY tLAC, tLAD LOGIC ARRAY INPUT tPIA
LOGIC ARRAY OUTPUT
C343-9
Internal Asynchronous
tIOR t CLOCK PIN tIN CLOCK INTO LOGIC ARRAY tIC CLOCK FROM LOGIC ARRAY tRSU DATA FROM LOGIC ARRAY tRD,tLATCH REGISTER OUTPUT TO LOCAL LAB
C343-10
tAWH
tAWL
tF
tRH
tFD
tCLR,tPRE
tFD
Internal Synchronous
tCH SYSTEM CLOCK PIN tIN SYSTEM CLOCK AT REGISTER tRSU DATA FROM LOGIC ARRAY
C343-12
tCL
tICS
tRH
15
CY7C343
Switching Waveforms (continued)
Output Mode
CLOCK FROM LOGIC ARRAY
tRD
tOD
DATA FROM LOGIC ARRAY tXZ OUTPUT PIN tZX HIGH IMPEDANCE STATE
C343-11
Ordering Information
Speed (ns) 20 25 30 Ordering Code CY7C343-20JC/JI CY7C343-25HC/HI CY7C343-25JC/JI CY7C343-30HC/HI CY7C343-30JC/JI CY7C343-30HMB 35 CY7C343-35HC/HI CY7C343-35JC CY7C343-35HMB Package Name J67 H67 J67 H67 J67 H67 H67 J67 H67 Package Type 44-Lead Plastic Leaded Chip Carrier 44-Pin Windowed Leaded Chip Carrier 44-Lead Plastic Leaded Chip Carrier 44-Pin Windowed Leaded Chip Carrier 44-Lead Plastic Leaded Chip Carrier 44-Pin Windowed Leaded Chip Carrier 44-Pin Windowed Leaded Chip Carrier 44-Lead Plastic Leaded Chip Carrier 44-Pin Windowed Leaded Chip Carrier Military Military Commercial/Industrial Commercial/Industrial Operating Range Commercial/Industrial Commercial/Industrial
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameters VOH VOL VIH VIL IIX IOZ ICC1 Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
Switching Characteristics
Parameters tPD1 tPD2 tPD3 tCO1 tS tH tACO1 tACO2 tAS tAH Subgroups 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11
Document #: 38-00128-I
16
CY7C343
Package Diagrams
44-Pin Windowed Leaded Chip Carrier H67
51-80079
17
CY7C343
Package Diagrams (continued)
44-Lead Plastic Leaded Chip Carrier J67
51-85003-A
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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