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L6671
ANGULAR ACCELEROMETER
PRODUCT PREVIEW
s s s s s s s s
HIGH SENSITIVITY 2.5 rad/sec2 7 BIT A/D CONVERTER (+1 SIGN BIT) 800 Hz BANDWIDTH 200 rad/sec2 FULL SCALE VALUE DIGITAL DOWNSAMPLING DIGITAL FILTERING 3.3V 3WIRES SERIAL INTERFACE (5V TOLLERANCE) EMBEDDED PLL
SO24 ORDERING NUMBER: L6671
DESCRIPTION The L6671 is a complete rotational accelerometer system based on a architecture, followed by a digital downsampling block and a digital filter, featuring high sensitivity, 800 Hz signal bandwidth and a complete serial port interface for a direct connection BLOCK DIAGRAM to microprocessor environment. An embedded PLL allows internal clock generation from an external synchronization signal.
SENSOR A/D CONVERTER DIGITAL FILTER SER. IFC
SPE SPD SPC
D00IN1117-Mod
Clk-IN
PLL
July 2001
This is preliminary information on a new product now in development. Details are subject to change without notice.
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L6671
PIN FUNCTION
N. Pin 1 to 6 7 8 9 10 11 12 19 to 24 13 14 15 16 17 18 Name NC Vdd_Analog Ref_Cap HV_Eprom Vdd_Digital SPC SPD NC SPE CLK_In Gnd_Digital Funct_Test Test_ST Gnd_Analog Not Connected Analog Voltage Supply Reference Voltage Bypass EPROM Programming Voltage (test mode only) Digital Voltage Supply Serial Port Clock Signal Serial Port Data Signal Not Connected Serial Port Enable Signal External Clock / PLL Reference Input Digital Ground Pin Self Test Test Pin Analog Ground Pin Tied to GND Tied to GND 5V Typ. 5V Typ. Function Typ. Condition
PIN CONNECTIONS (Top view)
N.C. N.C. N.C. N.C. N.C. N.C. VDD_ANALOG REF_CAP HV_EPROM VDD_DIGITAL SPC SPD
1 2 3 4 5 6 7 8 9 10 11 12
D00IN1116Mod
24 23 22 21 20 19 18 17 16 15 14 13
N.C. N.C. N.C. N.C. N.C. N.C. GND_ANALOG TEST_ST FUNCT_TEST GND_DIGITAL CLK_IN SPE
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L6671
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value 7 7 -0.3 to VddDig + 0.3 Unit V V
VddAnalog Max Maximum analog supply voltage VddDigital Max Maximum digital supply voltage Vin Voltage Range on SPC, SPE, SPD, CLK_In, Funct_Test
ELECTRICAL CHARACTERISTCS
Symbol DC VddAnalog Max Analog Supply Voltage VddDigital Max Digital Supply Voltage IddAnalog IddDigital Vref Voh Vol Vih Vil ADC ADC SNR (30-800Hz, 4.48MHz Ext.Clk) ADC SNR (30-10000Hz, 4.48MHz Ext.Clk) Phase error ADC Full Scale 30-800Hz (relative to a ref. Accelerometer) TBD 15 38 20 -30 200 TBD TBD dB dB deg rad/ sec2 Hz dB Analog Circuitry Supply Current Digital Circuitry Supply Current Voltage on Ref_Cap pin (on SPD and Funct_Test) @ Ioh = TBD 4.5 4.5 5.0 5.0 15 11 2.25 TBD TBD TBD TBD 5.5 5.5 V V mA mA V V V V V Parameter Test Condition Min. Typ. Max. Unit
ADC Bandwidth ADC Dynamic Range ADC Differential Linearity ADC Integral Linearity Mclk Clock Frequency on CLK_In pin
30-800 38 TBD TBD TBD
Full Scale MHz
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L6671
SERIAL PORT TIMINGS
Symbol Pin SPC Fpc TcH Pin SPE Tec Tce Twe SPE to SPC SPC to SPE SPE low TBD TBD TBD MHz SPC frequency High clock timeout during packet transmission 25pF maximum load Mclk 30 TBD 4 MHz s Parameter Test Condition Min. Typ. Max. Unit
Pin SPD (input) Tds Tdh SPD to SPC SPC to SPD TBD TBD ns V
Pin SPD (output) Tpd SPC to SPD TBD V
Figure 1. Application Diagram
18 VCC 7 8 C1 22F 6V GND 9 10 C2 0.22F C3 220pF C4 0.22F C5 0.22F 17 16 15 EXTERNAL CLK / PLL REF. 14 13 12 11
D00IN1118/MOD
SPE SPD SPC SERIAL I/O
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L6671
SERIAL PORT, REGISTERS, EPROM and TEST MODES 1.0 SERIAL PORT 1.1 READ & WRITE REGISTERS Figure 2.
SPE
SPC SPD RW ID2 ID1 ID0 AD3 AD2 AD1 AD0 D7 D6 D5 D4 D3 D2 D1 D0
D00IN1119
SPE is the Serial Port Enable. It goes high at the start of the transmission and goes back low at the end. SPC is the Serial Port Clock. It is stopped high when SPE is low (no transmission). SPD is the Serial Port Data. It is driven by the falling edge of SPC. It should be captured at the rising edge of SPC. The Read Register or Write Register command consists of 16 clocks or bit. A bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the rising edge of SPE and the last bit (bit 15) starts at the last falling edge of SPC just before the falling edge of SPE. s bit 0 : RW bit. When 0, the data (D7:0) is written into the device. When 1, the data (D7:0) from the device is read. In this case, the L6671 will drive SPD at the start of bit 8.
s
bit 1-3 : chip ID. The chip ID for the L6671 is ID(2:0)=110. The device accepts the command only when the ID is valid (equal to 110). bit 4-7 : address AD(3:0). This is the address field for the registers. See section 2 for more details. bit 8-15 : data D(7:0). This is the data that will be written (read) into (from) the register whose address is AD(3:0).
s s
1.2 READ FIFO Figure 3.
SPE
SPC SPD RW ID2 ID1 ID0 AD3 AD2 AD1 AD0 D7-0 D6-0 ..... D0-0 D7-1 D6-1 ..... D0-1
D00IN1120
The Read FIFO command consists of 24 clocks or bits. bit 0 : READ bit. The value is 1. bit 1-3 : chip ID. ID(2:0)=110. bit 4-7 : FIFO address. bit 8-23: FIFO data.
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L6671
The FIFO has four registers grouped into two banks. The first bank consists of the first and the second register. The first register is the one written first since the last read. The second bank consists of the third and fourth register. 0000: address for the first bank 0010: address for the second bank The device puts out first the data of the first register of the bank with the MSB first. 2.0 L6671 REGISTERS The registers are grouped into two banks. The following table summarizes their mapping.
Address 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 FIFO_Low not used FIFO_High not used CTRL_Reg1 CTRL_Reg2 PLL_PRESC_MULT PLL_MULT IIR_A0 IIR_A1 IIR_A2 IIR_B1 IIR_B2 IIR_SIGN_BIT DSC_Reg MISC_Reg Reg. Bank 0 FIFO_Low not used FIFO_High not used CTRL_Reg1 CTRL_Reg2 FLASH_Reg1 FLASH_Reg2 GAIN_Low GAIN_High OFFSET_Low OFFSET_High CURR_BANDGAP BAND_CSACT_Reg CS_TRIM MISC_Reg Reg. Bank 1
2.1 Registers Bank 0 AD(3:0) = 0100 CTRL_Reg1 This is the first control register. It has 8 bit whose function is summarized below. Note: x means don't care value. Note: default value after Power On Reset is 0100 0000 1xxx xxxx Chip in Power Down mode xx00 xxxx xx01 xxxx xx10 xxxx xx11 xxxx Clock from CLK pin Clock derived from the internal oscillator Clock from the PLL locking on CLK_in Clock from the PLL locking on FIFO_Low reading
xxxx 1xxx Internal Oscillator in Power Down mode
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L6671
xxxx x001 Bitstream in mode. The bitstream is sent in via pin Funct_Test while the bitstream clock is sent via CLK_pin. The output can be checked via the serial interface. xxxx x010 Bistream out mode. The bitstream is sent out through pin SPD while the bitstream clock is sent through pin SPC. The pin TEST_ST must be tied to 1.5V. xxxx x011 Internal clock check mode. The decimation signal is sent out through pin SPD while the main clock can be checked through pin SPC. The pin TEST_ST must be tied to 1.5V. xxxx x100 Flash write mode xxxx x101 Flash read mode xxxx x11x Sensor trimming AD(3:0) = 0101 CTRL_Reg2 This is the second control register. It has 8 bit whose function is summarized below. Note: x means don't care value. Note: default value after Power On Reset is 0110 0011 0xxx xxxx Delayed Synchronous Conversion reference coming from CLK_pin/FIFO_Low reading signal. 1xxx xxxx Low rate Delayed Synchronous Conversion reference signal. x1xx xxxx Delayed Synchronous Conversion enabled. xx1x xxxx Clip on. The result of the measuring chain is clipped when exceding the maximum/minimum limit. xxx0 0xxx 8 bit output word length xxx0 1xxx 16 bit output word length xxx1 xxxx 32 bit output word length xxxx x1xx Bypass the embedded IIR filter xxxx xx0x Set the decimation factor to 16. 32 when the bit is 1. xxxx xxx0 Set the sinc order to 2. 3rd order when the bit is 1. AD(3:0) = 0110 PLL_PRESC_MULT This register contain the division factor used in the PLL prescaler and the most significant bit of the PLL multiplication factor. AD(3:0) = 0111 PLL_PRESC_MULT This register contain the least significant bit of the PLL multiplication factor. AD(3:0) = 1000 IIR_A0 This register contain the A0 coefficient used in the embedded IIR register. AD(3:0) = 1001 IIR_A1 This register contain the A1 coefficient used in the embedded IIR register. AD(3:0) = 1010 IIR_A2 This register contain the A2 coefficient used in the embedded IIR register. AD(3:0) = 1011 IIR_B1 This register contain the B1 coefficient used in the embedded IIR register.
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L6671
AD(3:0) = 1100 IIR_B2 This register contain the B2 coefficient used in the embedded IIR register. AD(3:0) = 1101 IIR_SIGN_BIT This register contain the sign bit of the coefficients used in the embedded IIR register. AD(3:0) = 1110 DSC_Reg This register contain the threshold value used to trigger the decimation when the Delayed Synchronous Conversion mode is enabled. AD(3:0) = 1111 MISC_Reg This is the miscellaneous register. Note: default value after Power On Reset is 0010 0000 1xxx 0x0x Force a SW reset. x1xx xx0x Enters PLL test mode. Bit 2-5 Define the internal oscillator division factor. xxxx xx01 Switch to Registers Bank 1.
2.2 Registers Bank 1 AD(3:0) = 0100 CTRL_Reg1 This is the second control register. AD(3:0) = 0101 CTRL_Reg2 This is the second control register. AD(3:0) = 0110 FLASH_REG1 This register is used to program the embedded memory. AD(3:0) = 0111 FLASH_REG1 This register is used to program the embedded memory. AD(3:0) = 1000 GAIN_Low These are the 8 LSB of gain for the adjustment unit. AD(3:0) = 1001 GAIN_High These are the 8 MSB of gain for the adjustment unit. AD(3:0) = 1010 OFFSET_Low These are the 8 LSB of offset for the adjustment unit. AD(3:0) = 1011 OFFSET_High These are the 8 MSB of offset for the adjustment unit.
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L6671
AD(3:0) = 1100 CURR_BANDGAP This register is used for references trimming. AD(3:0) = 1101 BAND_CSACT_Reg This register is used for interface trimming and sensor actuation. AD(3:0) = 1110 CSTRIM_Reg This register is used for sensor trimming. AD(3:0) = 1111 MISC_Reg This is the miscellaneous register. 3.0 L6671 COMPATIBILITY VERSUS L6670 Externally L6671 presents the same pin-out of L6670. To have full compatibility with L6670 in terms of bitstream processing it is necessary to write the following configuration inside the L6671 registers: CTRL_REG1: 0100 0000 CTRL_REG2: 0010 0111
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L6671
DIM. MIN. A A1 A2 B C D E e H h k L 0.40 10.0 0.25 0.33 0.23 15.20 7.40 2.35 0.10
mm TYP. MAX. 2.65 0.30 2.55 0.51 0.32 15.60 7.60 1.27 10.65 0.75 0.394 0.010 0.013 0.009 0.598 0.291 MIN. 0.093 0.004
inch TYP. MAX. 0.104 0.012 0.100 0.0200 0.013 0.614 0.299 0,050 0.419 0.030
OUTLINE AND MECHANICAL DATA
0 (min.), 8 (max.)
SO24
1.27 0.016 0.050
h x 45
A2
A1
A
0.10mm .004 Seating Plane
B
e
K L H
A1
C
D
24
13
1
12
SO24
10/11
E
L6671
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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