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 M7040N
64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE
DATA BRIEFING
FEATURES SUMMARY s 64K DATA ENTRIES IN 72-BIT MODE
s
Figure 1. 388-ball PBGA Package
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TABLE MAY BE PARTITIONED INTO UP TO EIGHT (8) OCTANTS (Data entry width in each octant is configurable as 36, 72, 144, or 288 bits.) UP TO 100 MILLION SUSTAINED SEARCHES PER SECOND IN 72-BIT and 144-BIT CONFIGURATIONS UP TO 50 MILLION SEARCHES PER SECOND IN 36-BIT and 288-BIT CONFIGURATIONS SEARCHES ANY SUB-FIELD IN A SINGLE CYCLE OFFERS BIT-BY-BIT and GLOBAL MASKING SYNCHRONOUS, PIPELINED OPERATION UP TO 31 SEARCH ENGINES CASCADABLE WITHOUT PERFORMANCE DEGRADATION WHEN CASCADED, THE DATABASE ENTRIES CAN SCALE FROM 496K TO 3968K DEPENDING ON THE WIDTH OF THE ENTRY GLUELESS INTERFACE TO INDUSTRYSTANDARD SRAMS SIMPLE HARDWARE INSTRUCTION INTERFACE IEEE 1149.1 TEST ACCESS PORT OPERATING SUPPLY VOLTAGES INCLUDE: VDD (Operating Core Supply Voltage) = 1.5V for 66 and 83MSPS; 1.65V for 100MSPS VDDQ (Operating Supply Voltage for I/O) = 2.5 or 3.3V 388 PBGA, 35mm x 35mm
388-ball PBGA 35mm x 35mm
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April 2002
Complete data available on Data-on-Disc CD-ROM or at www.st.com
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M7040N
DESCRIPTION Overview ST Microelectronics, Inc.'s M7040N Search Engine incorporates patent-pending Associative Processing TechnologyTM (APT) and is designed to be a high-performance, pipelined, synchronous, 64K-entry network database search engine. The M7040N database entry size can be 72 bits, 144 bits, or 288 bits. In the 72-bit entry mode, the size of the database is 64K entries. In the 144-bit mode, the size of the database is 32K entries, and in the 288-bit mode, the size of the database is 16K entries. The M7040N is configurable to support multiple databases with different entry sizes. The 36-bit entry table can be implemented using the Global Mask Registers (GMRs) building-database size of 128K entries with a single device. Performance The Search Engine can sustain 100 million transactions per second when the database is programmed or configured as 72 or 144 bits. When the database is programmed to have an entry size Table 1. Product Range
Part Number M7040N-100ZA1 M7040N-083ZA1 M7040N-066ZA1 Operating Supply Voltage 1.65V 1.5V 1.5V Operating I/O Voltage 2.5 or 3.3V 2.5 or 3.3V 2.5 or 3.3V Speed 100MHz 83MHz 66MHz Temperature Range Commercial Commercial Commercial
of 36 or 288 bits, the Search Engine will perform at 50 million transactions per second. STM's M7040N can be used to accelerate network protocols such as Longest-prefix Match (CIDR), ARP, MPLS, and other Layer 2, 3, and 4 protocols. Applications This high-speed, high-capacity Search Engine can be deployed in a variety of networking and communications applications. The performance and features of the M7040N make it attractive in applications such as Enterprise LAN switches and routers and broadband switching and/or routing equipment supporting multiple data rates at OC- 48 and beyond. The Search Engine is designed to be scalable in order to support network database sizes to 3968K entries specifically for environments that require large network policy databases. Figure 4, page 5 shows the block diagram for the M7040N device.
Figure 2. Switch/Router Implementation Using the M7040N
Sys
tem
Bus
m Progra ry Memo
Host ASIC
Switch Fabric
h Searc e Engin
SRAM Bank
Ne
two
rk L
ine
Inte
Switch or rocess P
rfac
es
AI04272
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M7040N
Table 2. Signal Names
Symbol Type(1) Description SADR[23:0] CE_L WE_L OE_L ALE_L SRAM Interface T T T T T SRAM Address SRAM Chip Enable SRAM Write Enable SRAM Output Enable Address Latch Enable
Clocks and Reset CLK_MODE CLK2X_CLK1X PHS_L TEST_CO(2) TEST TEST_FM RST_L TEST_PB(3) CFG_L I I I I I I I I I Clock Mode Master Clock Phase Test Output (ST Use Only) Test Input (ST Use Only) Test Input (ST Use Only) Reset Test Input (ST Use Only)
Cascade Interface LHI[6:0] LHO[1:0] BHI[2:0] BHO[2:0] I O I O I O O Local Hit In Local Hit Out Block Hit In Block Hit Out Full In Full Out Full Flag
Configuration
FULI[6:0] FULO[1:0] FULL
Command and DQ Bus CMD[10:0] CMDV DQ[71:0] ACK(4) EOT SSF SSV MULTI_HIT HIGH_SPEED CLKTUNE[3:0]
(4)
I I I/O T T T T O I I
Command Bus Command Valid Address/Data Bus READ Acknowledge End of Transfer SEARCH Successful Flag SEARCH Successful Flag Valid Multiple Hit Flag 100MHz Indicator PLL Tuner
Device Identification ID[4:0] I Device Identification Supplies VDD n/a Chip Core Supply (1.5V for 66 and 83MSPS; 1.65 for 100MSPS) Chip I/O Supply (2.5 or 3.3V)
VDDQ
n/a
Test Access Port TDI TCK TDO TMS TRST_L I I T I I Test Access Port's Test Data In Test Access Port's Test Clock Test Access Port's Test Data Out Test Access Port's Test Mode Select Test Access Port's Reset
Note: 1. Signal types are: I = Input only; I/O = Input or Output; O = Output; and T = Tristate See DESCRIPTIONS FOR CONNECTION DIAGRAM (Figure 3, page 9), page 152 for individual connection details. 2. In the previous versions of this specification, this signal was called, "CLK_OUT." 3. In previous versions of this specification, this signal was called, "PLL_BYPASS." 4. ACK and EOT Signals require a weak, external pull-down resistor of 47 K or 100 K.
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M7040N
Figure 3. Connections
1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 2 3 4
DQ67
5
DQ63
6
VDDQ
7
DQ57
8
DQ53
9
DQ51
10
DQ43
11
DQ41
12
DQ37
13
DQ35
14
DQ31
15
VDDQ
16
DQ25
17
DQ21 VDDQ
18
DQ17
19
VDDQ
20
DQ9
21
DQ5
22
DQ3
23
24
25
26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
CLK DQ71 VDDQ TUNE3 VSS
TEST_ V HIGH_ CLK DDQ FM SPEED TUNE0 TEST_ CFG_L PB VDD VDD VSS SADR 0
TDI
DQ69
DQ65
DQ61
DQ59
DQ55
VDDQ
DQ47
DQ45
DQ39
VDDQ
DQ33
DQ29
DQ27
DQ23
DQ15
DQ11
DQ7
VDDQ VDD
DQ1
TCK TRST_ L ID0
TMS
VDD
VDD VSS
VDD
VDD VSS
VDD
NC8
DQ49
VDDQ VSS
VDD
VDD
VDD
VDD
VDD
VDD
DQ19
DQ13
NC7
VDD
VDD
SADR V DDQ 1 SADR 3 SADR 5 SADR 2 SADR 4
TDO
VDD
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS VSS
VDD
VDDQ VDD
VSS
VDD VDD
ID1
ID2
VDD
VSS
VSS
SADR V DDQ 6 SADR SADR 8 7 VDDQ SADR 9
ID3
ID4
VDD
VSS
VSS VSS VSS
VDD
LHI0
LHI1
NC1
VSS VSS
NC6
LHI2
LHI3
VDDQ
SADR SADR SADR 11 12 10 SADR SADR V DDQ 14 13 VDD SADR 15 SADR 16
LHI6
LHI4
LHI5
VSS
VSS
LHO0
LHO1
VDD
VDD
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VDD
VDDQ
BHI0
VDD
VDD
VDD
VDD
VDDQ SADR 17 SADR SADR 18 19 SADR SADR 21 20 SADR V DDQ 22 CLK_ SADR MODE 23
BHI1
BHI2
VDD
VDD
VSS
VSS
VSS VSS VSS
VSS
VSS VSS VSS
VSS VSS VSS
VDD
VDD
BHO0 MULTI_ VDD HIT VDDQ BHO1 VDD
VDD
VSS VSS
VSS VSS
VSS VSS VSS
VDD
VDD
VDD
VDD
VDD
BHO2
VSS
VDD
VDD VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
FULI0 VDDQ FULI1
VSS
CLK1x/ OE_L PHS_L CLK2x CE_L VDDQ WE_L
FULI2 FULI3
FULI4
VSS
VSS
VDDQ FULI5
NC2
VSS
VSS VSS
NC5 CMDV ALE_L
FULI6 FULO0
VDD
VSS
VDD
CMD1 CMD0
FULO1 VDDQ
VDD
VSS
VSS
VDD
CMD3 CMD2
FULL
ACK
VDD
VSS
VSS
VDD
CMD5 CMD4
VSS
EOT
VDD
VSS VDD
VSS VDD
VSS VDD
VSS VDD
VSS
VSS VDDQ
VSS
VDD
VDD VDD
VDD
VDD VDD
VDD VDD
VDD VDD
VSS
VSS
VSS
VSS VDD
VSS VDD
VSS
VSS
VDD
CMD6 VDDQ
RST_L VDDQ
VDD
NC3
DQ46
VDD
VDD VDDQ
DQ20 VDDQ
DQ16
NC4
VDD
VDD
VDD VDDQ
CMD8 CMD7 CLK TUNE1
TEST
VSS
DQ70
VDDQ
DQ64
DQ60
DQ58
DQ54
DQ50
DQ44
DQ42
DQ38
DQ32
DQ28
DQ26
DQ18
DQ12
DQ10
DQ6
VDDQ
DQ0
VSS
TEST_ CLK DQ68 CO TUNE2
DQ66
DQ62
VDDQ
DQ56
DQ52
DQ48
VDDQ DQ40
DQ36
DQ34
DQ30
VDDQ
DQ24
DQ22
DQ14
VDDQ
DQ8
DQ4
DQ2
SSV
SSF CMD10 CMD9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
AI04646
Note: This diagram is TOP VIEW perspective (view through package).
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M7040N
Figure 4. M7040N Block Diagram
PHS_L CLK1X_CLK2X RST_L CLK_MODE Comparand Registers[15:0] Global Mask Registers [15:0] Information and Command Register Burst Read Register Burst Write Register Next Free Address Register Search Successful Index Registers [7:0] (All registers are 72-bit-wide) TAP Controller TAP
DQ [71:0]
Compare/PIO Data
Cmd Compare/PIO Data
Address Decode
CMD [10:0] CMDV ACK EOT
Priority Encode
Match Logic
Command Decode and PIO Access
Configurable as 128K x 36 64K x 72 32K x 144 16K x 288 Data Array Configurable as 128K x 36 64K x 72 32K x 144 16K x 288 Mask Array
SADR [23:0] Pipeline and SRAM Control OE_L WE_L CE_L ALE_L
ID [4:0]
FULL [6:0]
Full Logic FULL LHI [6:0] BHI [2:0] Arbitration Logic FULO [1:0] LHO [1:0] BHO [2:0] SSF SSV
AI04645
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M7040N
PART NUMBERING Table 3. Ordering Information Scheme
Example: M70 40 N -100 ZA 1 T
Device Type M70 Search Engine
Density 40 = 4.5Mb (64K x 72-bit Table Entries)
Operating Supply Voltage N = VDD = 1.5V for -066 and -083 speed grades VDD = 1.65V for -100 speed grade
Speed -100 = 100 Million Searches per Second -083 = 83 Million Searches per Second -066 = 66 Million Searches per Second
Package PBGA = 388-ball count, 35mm x 35mm(1), 1.27mm ball pitch
Temperature Range 1 = 0 to 70C
Shipping Option Tape & Reel Packing = T
Note: 1. Where "Z" is the symbol for BGA packages and "A" denotes 1.27mm ball pitch
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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M7040N
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com
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