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M68AF031A
256 Kbit (32K x 8) 5.0V Asynchronous SRAM
FEATURES SUMMARY s SUPPLY VOLTAGE: 4.5 to 5.5V
s s s s s s
Figure 1. Packages
32K x 8 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIME: 55, 70ns LOW STANDBY CURRENT LOW VCC DATA RETENTION: 2V TRI-STATE COMMON I/O AUTOMATIC POWER DOWN
SO28 (MS)
28
1
PDIP28 (B)
TSOP28 (N) 8 x 13.4mm
TSOP28 (NS) 8 x 13.4 mm (Reverse)
April 2003
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M68AF031A
TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 3. SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 4. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 5. TSOP Connections (Normal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 6. TSOP Connections (Reverse) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 7. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 9. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. DC Characteristics (M68AF031A-55 and M68AF031A-70) . . . . . . . . . . . . . . . . . . . . . . . . . 7 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 10. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 11. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . 9 Figure 12. Chip Enable Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 13. Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 14. Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 15. Low V CC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9. Low V CC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SO28 - 28 lead Plastic Small Outline, 300 mils body width, Package Outline . . . . . . . . . . . . . . . . 15 SO28 - 28 lead Plastic Small Outline, 300 mils body width, Package Mechanical Data . . . . . . . . . 15 PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PDIP28 - 28 pin Plastic DIP, n600 mils width, Package Mechanical Data . . . . . . . . . . . . . . . . . . . 16 TSOP28 - 28 lead Normal and Reverse Pinout Plastic Small Outline, Package Outline . . . . . . . . 17 TSOP28 - 28 lead Normal and Reverse Pinout Plastic Small Outline, Package Mechanical Data . 17 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 13. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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M68AF031A
SUMMARY DESCRIPTION The M68AF031A is a 256 Kbit (262,144 bit) CMOS SRAM, organized as 32,768 bytes. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 4.5 to 5.5V supply. This device has an automatic power-
down feature, reducing the power consumption by over 99% when deselected. The M68AF031A is available in SO28 (28-lead Small Outline), PDIP28 (28-pin Plastic Dual-InLine) and TSOP28 (28-lead Thin Small Outline, Standard and Reverse Pinout) packages.
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A14 Address Inputs Data Input/Output Chip Enable Output Enable Write Enable Supply Voltage Ground Not Connected Internally
VCC
DQ0-DQ7 E
16 A0-A14 W M68AF031A E G
8 DQ0-DQ7
G W VCC VSS NC
VSS
AI05920C
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M68AF031A
Figure 3. SO Connections Figure 5. TSOP Connections (Normal)
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 M68AF031A 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC W A4 A3 A2 A1 G A0 E DQ7 DQ6 DQ5 DQ4 DQ3
AI05921C
G A1 A2 A3 A4 W VCC A5 A6 A7 A8 A9 A10 A11
22
21
28 1
M68AF031A 15 (Normal) 14
7
8
AI07200C
A0 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A14 A13 A12
Figure 4. DIP Connections
Figure 6. TSOP Connections (Reverse)
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 M68AF031A 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VCC W A4 A3 A2 A1 G A0 E DQ7 DQ6 DQ5 DQ4 DQ3
A11 A10 A9 A8 A7 A6 A5 VCC W A4 A3 A2 A1 G
7
8
1 28
M68AF031A (Reverse)
14 15
22
21
AI07201C
A12 A13 A14 DQ0 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 DQ7 E A0
AI05922C
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M68AF031A
Figure 7. Block Diagram
A14 ROW DECODER A7 MEMORY ARRAY
DQ7
I/O CIRCUITS COLUMN DECODER
DQ0
A0 E W
A6
G
AI05919
MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 2. Absolute Maximum Ratings
Symbol IO (1) PD TA TSTG VCC VIO (2) Output Current Power Dissipation Ambient Operating Temperature Storage Temperature Supply Voltage Input or Output Voltage Parameter
plied. Exposure to Absolute Maximum Rating conditions for periods greater than 1 sec periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Value 20 1 -55 to 125 -65 to 150 -0.5 to 6.5 -0.5 to VCC +0.5
Unit mA W C C V V
Note: 1. One output at a time, not to exceed 1 second duration. 2. Up to a maximum operating VCC of 6.0V only.
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M68AF031A
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Parameter VCC Supply Voltage Range 1 Ambient Operating Temperature Range 6 Load Capacitance (CL) Output Circuit Protection Resistance (R1) Load Resistance (R2) Input and Output Timing Ref. Voltages Input Rise and Fall Times Input Pulse Voltages Output Transition Timing Ref. Voltages -40 to 85C 100pF 3.0k 3.1k VCC/2 1ns/V 0 to VCC VRL = 0.3VCC; VRH = 0.7VCC M68AF031A 4.5 to 5.5V 0 to 70C
Figure 8. AC Measurement I/O Waveform
Figure 9. AC Measurement Load Circuit
VCC
I/O Timing Reference Voltage VCC VCC/2 0V DEVICE UNDER TEST CL Output Timing Reference Voltage VCC 0.7VCC 0.3VCC
AI05831
R1
OUT
R2
0V
CL includes probe capacitance
AI05932
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M68AF031A
Table 4. Capacitance
Symbol CIN COUT Parameter(1,2) Input Capacitance on all pins (except DQ) Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 8 Unit pF pF
Note: 1. Sampled only, not 100% tested. 2. At TA = 25C, f = 1 MHz, VCC = 5.0V.
Table 5. DC Characteristics (M68AF031A-55 and M68AF031A-70)
Symbol Parameter Test Condition VCC = 5.5V, f = 1/tAVAV, IOUT = 0mA VCC = 5.5V, f = 1MHz, IOUT = 0mA VCC = 5.5V, f = 0, E VCC -0.2V 0V VIN VCC 0V VOUT VCC Range 1 Range 6 -1 -1 2.2 -0.3 IOH = -1.0mA IOL = 2.1mA 2.4 0.4 0.1 0.1 Min Typ Max 50 5 5 10 1 1 VCC + 0.3 0.8 Unit mA mA A A A A V V V V
ICC1 (1,2) Operating Supply Current ICC2 (3) ISB ILI ILO (4) VIH VIL VOH VOL
Note: 1. 2. 3. 4.
Operating Supply Current
Standby Supply Current CMOS Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage
Average AC current, cycling at tAVAV minimum. E = VIL, VIN = V IL OR VIH. E 0.2V, VIN 0.2V OR VIN VCC -0.2V. Output disabled.
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M68AF031A
OPERATION The M68AF031A has a Chip Enable power down feature which invokes an automatic standby mode whenever Chip Enable is de-asserted (E = High). An Output Enable (G) signal provides a high speed tri-state control, allowing fast read/write cyTable 6. Operating Modes
Operation Deselected Read Write Output Disabled
Note: 1. X = VIH or VIL.
cles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W and E, as summarized in the Operating Modes table (see Table 6).
E VIH VIL VIL VIL
W X VIH VIL VIH
G X VIL X VIH
DQ0-DQ7 Hi-Z Data Output Data Input Hi-Z
Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Read Mode The M68AF031A is in the Read mode whenever Write Enable (W) is High with Output Enable (G) Low, and Chip Enable (E) is asserted. This provides access to data of the 262,144 locations in the static memory array, specified by the 15 address inputs. Valid data will be available at the eight output pins within tAVQV after the last stable
address, providing G is Low and E is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (tELQV or tGLQV) rather than the address. Data out may be indeterminate at tELQX and tGLQX but data lines will always be valid at tAVQV.
Figure 10. Address Controlled, Read Mode AC Waveforms
tAVAV A0-A14 tAVQV VALID tAXQX
DQ0-DQ7
DATA VALID
AI05939
Note: E = Low, G = Low, W = High.
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M68AF031A
Figure 11. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.
tAVAV A0-A14 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 VALID
AI05940
VALID tAXQX tEHQZ
tGHQZ
Note: Write Enable (W) = High.
Figure 12. Chip Enable Controlled, Standby Mode AC Waveforms
E ICC ISB tPU 50% tPD
AI05956
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M68AF031A
Table 7. Read and Standby Mode AC Characteristics
M68AF031A Symbol Parameter Min. tAVAV tAVQV tAXQX (1) tEHQZ (2,3) tELQV tELQX (1) tGHQZ (2,3) tGLQV tGLQX (1) tPD (4) tPU (4) Read Cycle Time Address Valid to Output Valid Data hold from address change Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Chip Enable Low to Output Lo-Z Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Chip Enable High to Power Down Chip Enable Low to Power Up 0 5 55 0 5 20 25 5 70 5 20 55 5 25 35 55 55 5 25 70 55 Max. Min. 70 70 70 Max. ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Test conditions assume transition timing reference level = 0.3VCC or 0.7VCC. 2. At any given temperature and voltage condition, tGHQZ is less than tGLQX and tEHQZ is less than t ELQX for any given device. 3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4. Tested initially and after any design or process changes that may affect these parameters.
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M68AF031A
Write Mode The M68AF031A is in the Write mode whenever the W and E are Low. Either the Chip Enable input (E) or the Write Enable input (W) must be deasserted during Address transitions for subsequent write cycles. When E (W) is Low, write cycle begins on the W (E)'s falling edge. Therefore, address setup time is referenced to Write Enable or Chip Enable as tAVWL and t AVEL respectively, and is determined by the latter occurring edge.
The Write cycle can be terminated by the earlier rising edge of E or W. If the Output is enabled (E = Low, G = Low), then W will return the outputs to high impedance within tWLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for t DVEH before the rising edge of E, whichever occurs first, and remain valid for tWHDX and tEHDX respectively.
Figure 13. Write Enable Controlled, Write AC Waveforms
tAVAV A0-A14 VALID tAVWH tELWH E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA (1) DATA INPUT tDVWH
AI05941
tWHAX
tWHQX
DATA (1)
Note: 1. During this period DQ0-DQ7 are in output state and input signals should not be applied.
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M68AF031A
Figure 14. Chip Enable Controlled, Write AC Waveforms
tAVAV A0-A14 VALID tAVEH tAVEL E tWLEH W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI05942
tELEH
tEHAX
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M68AF031A
Table 8. Write Mode AC Characteristics
M68AF031A Symbol Parameter Min. tAVAV tAVEH tAVEL tAVWH tAVWL tDVEH tDVWH tEHAX tEHDX tELEH tELWH tWHAX tWHDX tWHQX (1) tWLEH tWLQZ (1,2) tWLWH Write Cycle Time Address Valid to Chip Enable High Address valid to Chip Enable Low Address Valid to Write Enable High Address Valid to Write Enable Low Input Valid to Chip Enable High Input Valid to Write Enable High Chip Enable High to Address Transition Chip enable High to Input Transition Chip Enable Low to Chip Enable High Chip Enable Low to Write Enable High Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Output Transition Write Enable Low to Chip Enable High Write Enable Low to Output Hi-Z Write Enable Low to Write Enable High 45 55 45 0 45 0 25 25 0 0 45 45 0 0 5 45 20 50 55 Max. Min. 70 60 0 60 0 30 30 0 0 60 60 0 0 5 60 25 70 Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. At any given temperature and voltage condition, tWLQZ is less than tWHQX for any given device. 2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
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M68AF031A
Figure 15. Low VCC Data Retention AC Waveforms
DATA RETENTION MODE 5.5V VCC 4.5V
VDR > 2.0V tCDR E VDR - 0.2V E tR
AI05925
Table 9. Low V CC Data Retention Characteristics
Symbol ICCDR (1) Parameter Supply Current (Data Retention) Test Condition VCC = 2.0V, E VCC -0.2V, f = 0 (3) 0 tAVAV E VCC -0.2V, f = 0 2.0 Min Typ Max 6 Unit A ns ns V
Chip Deselected to Data Retention tCDR (1,2) Time tR (2) VDR (1) Operation Recovery Time Supply Voltage (Data Retention)
Note: 1. All other Inputs at V IH VCC -0.2V or VIL 0.2V. 2. Tested initially and after any design or process changes that may affect these parameters. tAVAV is Read cycle time. 3. No input may exceed VCC +0.2V.
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M68AF031A
PACKAGE MECHANICAL Figure 16. SO28 - 28 lead Plastic Small Outline, 300 mils body width, Package Outline
D
14 1
h x 45
C E H
15
28
A B SO-E
Note: Drawing is not to scale.
e
A1
ddd A1 L
Table 10. SO28 - 28 lead Plastic Small Outline, 300 mils body width, Package Mechanical Data
millimeters Symbol Typ A A1 A2 B C D ddd E e H L N 1.27 7.39 - 11.68 0.79 0 28 Min 2.38 0.05 2.28 0.35 0.20 18.03 Max 2.79 0.35 2.43 0.50 0.30 18.41 0.10 7.62 - 12.19 1.27 8 0.050 0.291 - 0.460 0.031 0 28 Typ Min 0.094 0.002 0.090 0.014 0.008 0.710 Max 0.110 0.014 0.096 0.020 0.012 0.725 0.004 0.300 - 0.480 0.050 8 inches
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M68AF031A
Figure 17. PDIP28 - 28 pin Plastic DIP, 600 mils width, Package Outline
A2 A1 B1 B D2 D S
N
A L eA eB C
e1
E1
1
E
PDIP
Note: Drawing is not to scale.
Table 11. PDIP28 - 28 pin Plastic DIP, n600 mils width, Package Mechanical Data
millimeters Symbol Typ A A1 A2 B B1 C D D2 E E1 e1 eA eB L S N 2.54 14.99 33.02 15.24 1.52 Min - 0.38 3.56 0.38 - 0.20 36.83 - - 13.59 - - 15.24 3.18 1.78 0 28 Max 5.08 - 4.06 0.51 - 0.30 37.34 - - 13.84 - - 17.78 3.43 2.08 10 0.100 0.590 1.300 0.600 0.060 Typ Min - 0.015 0.140 0.015 - 0.008 1.450 - - 0.535 - - 0.600 0.125 0.070 0 28 Max 0.200 - 0.160 0.020 - 0.012 1.470 - - 0.545 - - 0.700 0.135 0.082 10 inches
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M68AF031A
Figure 18. TSOP28 - 28 lead Normal and Reverse Pinout Plastic Small Outline, Package Outline
A2
22 21
e
28 1
E B
7 8
D1 D
A CP
DIE
C
TSOP-c
Note: Drawing is not to scale.
A1
L
Table 12. TSOP28 - 28 lead Normal and Reverse Pinout Plastic Small Outline, Package Mechanical Data
millimeters Symbol Typ A A1 A2 B C CP D D1 E e L N 0.550 13.200 11.700 7.900 - 0.500 0 28 0.950 0.170 0.100 Min Max 1.250 0.200 1.150 0.270 0.210 0.100 13.600 11.900 8.100 - 0.700 5 0.0217 0.5197 0.4606 0.3110 - 0.0197 0 28 0.0374 0.0067 0.0039 Typ Min Max 0.0492 0.0079 0.0453 0.0106 0.0083 0.0039 0.5354 0.4685 0.3189 - 0.0276 5 inches
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M68AF031A
PART NUMBERING Table 13. Ordering Information Scheme
Example: Device Type M68 Mode A = Asynchronous Operating Voltage F = 4.5 to 5.5V Array Organization 031 = 256 Kbit (32K x8) Option 1 A = 1 Chip Enable Option 2 L = L-Die M = M-Die Speed Class 55 = 55ns 70 = 70ns Package MS = SO28 B = PDIP28 N = TSOP28 8x13.4mm NS = TSOP28 8x13.4mm (Reverse Pinout) Operative Temperature 1 = 0 to 70C 6 = -40 to 85 C Shipping T = Tape & Reel Packing M68AF031 A L 70 MS 6 T
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
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M68AF031A
REVISION HISTORY Table 14. Document Revision History
Date January 2002 07-Feb-2002 08-Feb-2002 06-Mar-2002 19-Apr-2002 Version -01 -02 -03 -04 -05 First Issue ISB clarified TSOP28 Package removed AC Measurement Load Circuit changed (Figure 9) Operating and AC Measurement Conditions clarified (Table 3) Document status changed to Data Sheet Absolute Maximum current value added (Table 2) Operating and AC Measurement Conditions clarified (Table 3) Absolute Maximum Ratings Table clarified (Table 2) Operating and AC Measurement Conditions Table clarified (Table 3) DC Characteristics Table clarified (Table 5) Write Mode AC Characteristics Table clarified (Table 8) Low VCC Data Retention AC Waveforms clarified (Figure 15) Low VCC Data Retention Characteristics Table clarified (Table 9) DC Characteristics Table clarified (Table 5) Low VCC Data Retention Characteristics Table clarified (Table 9) TSOP28 8x13.4mm Standard and Reverse pinout added (Figure 1, 5, 6, Table 12) Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 08 equals 8.0). New part number added. Datasheet number simplified. 55ns speed-class added Revision Details
26-Apr-2002
-06
20-May-2002 29-May-2002
-07 -08
02-Oct-2002
8.1
09-Oct-2002 23-Apr-2003
8.2 8.3
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M68AF031A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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