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INDEX PRELIMINARY
MX9691
SINGLE CHIP SOLID STATE DISK CONTROLLER
FEATURES
Host Interface * Fully compatible with PCMCIA Release 2.1, and PC Card ATA Release 1.02 specification. * Compatible with all PC Card Services and Socket Service. * Fast ATA host-to-buffer burst transfer rates up to 20MB/ sec. which support PIO mode 4(16.6MB/sec) and DMA mode 3(16.6MB/sec). * Automatic sensing of PCMCIA or ATA host interface. * Integrated PCMCIA attribute memory of 256 bytes (CIS). - CIS and Buffer RAM use same SRAM area to simplify internal bus design * PCMCIA card configuration register support. * Polarity control for host reset signal. * PCMCIA twin card support. * PCMCIA based ATA address decode support. * Emulate the IBM task file for PC/AT. * Separate status for Bus reset and Host program reset. * Separate Host and Disk interrupt pins. Flash Memory Interface * Support all the control signals to execute read/write/ erase operation for flash memory. * Upto 32MB(unformatted) capacity for 16 pcs. 16Mbit flash memory or 64MB(unformatted) capacity for 16 pcs. 32Mbit flash memory. * Flash Memory Power Down or write protect control support. - Don't power down the flash memory chip which used to store firmware * Flash Memory Ready/Busy status detect. * Inverted data bus control to reduce program operation in DOS FAT and ECC code field. * Optional store firmware in flash memory array w/o externalROM. - Shadow ROM control to allow code fetch during data program or erase * Media speed is upto 8MB/sec, sustain read data rate and 125KB/sec write data rate. Buffer RAM control * Dual port circular Buffer RAM control * 1KB data Buffer RAM. * Automatically correct error data in Buffer RAM. - Single word error correct and double word detect. * Provide logic to speed up Buffer RAM access. * Support 8 bit as well as 16 bit transfer on host bus. DSP core * High performance MX93011 DSP (21Mips) core. * 4KB Internal RAM(direct access). * 2KB Internal expansion RAM(indirect access) for store data or shadow ROM space. * ICE debugging mode supported to ease system verifi cation. * Lower power and automatic power saving operation Operating current for 25MHz system speed - Active mode < 40mA - Idle mode < 35mA - Standby mode < 10mA - Sleep mode < 1mA Technology * 128 pin TQFP * 0.6um Low-power, High-speed CMOS technology. * Five-volt-only power supply. Utility Support * * * * Upload firmware from Host. Physical Devices test. Preformat. CIS Manufacturer code and Model code edit.
P/N:PM0502
REV. 1.2, NOV. 27, 1997
1
INDEX
MX9691
GENERAL DESCRIPTION
The Macronix's Solid State Disk controller is fully integrated flash memory controller that provides all the control logic for a PC Card ATA flash memory. The MX9691 combines 1KB dual-port buffer and buffer manager, integrated MX93011 DSP core , and a complete host interface for both the PC Card ATA and ATA standard. The MX9691 is typically configured with up to 32MB(unformatted) capacity for 16 pcs. 16Mbit flash memory or 64MB(unformatted) capacity for 16 pcs. 32Mbit flash memory. The MX9691 supports all the control signals to execute read/write/erase operation for flash memory chip. The MX9691 is fully compliant with the PC Card ATA specification. It includes 256 bytes of integrated attribute memory(for the required Card Information Structure) and four Card Configuration registers. The PCMCIA device driver can access the MX9691 ATA command block through four different modes by writing the different modes by writing the configuration index of the attribute memory configuration option register.
PIN DESCRIPTION
Host Interface Symbol HA[10:0] No. Type 92,94, 96-97, I 99,101-103, 106,109,113 84-89,116-117, I/O 121-128 104,111 107,110 100 I I I Description Host address line 10-0. These pins include internal pull-up resistors. Host data line 15-0. These pins include internal bus holder circuit that keep previous state when tri-state. Host memory read/write/mode select : Both pins include internal pullup resistors that is default in PCMCIA mode. Host I/O access. Both pins include internal pull-up resistors. The host reset signal, when active, initializes the control/status registers and stops any command in process.In PCMCIA mode, the signal is active high. In ATA extension mode, this signal is active low. This signal include internal pull-down resistor. WAIT or INPUT CHANNEL READY : In both PCMCIA and ATA extension modes, this signal holds host transfers until the controller is ready to respond. READY/BUSY or HOST INTERRUPT : In PCMCIA mode, this signal has two functions. In PCMCIA common memory mode, this signal is ready/busy. It is asserted busy by the reset logic, and can be deasserted by the local uC. In PCMCIA I/O mode, this signal is IREQ#. In ATA extension mode, this active high signal is HOSTINT, which, when enable, send an interrupt to the host.
HD[15:0]
HOE#,HWE# IOR#,IOW# HRESET/ HRESET#
WAIT/ IOCHRDY RDY/BSY#/ IREQ#/ HOSTINT
98
O,OD
119
O,Z
2
INDEX
MX9691
Symbol WP/IOCS16# No. 83 Type O,OD Description WRITE PROTECT or 16-bit I/O TRANSFER : In PCMCIA mode, this bit has two functions. In PCMCIA common-memory mode,this signal indicates write protect. In PCMCIA I/O mode, when IOIS16# is as serted low, it indicates that a 16-bit data transfer is active on PCMCIA bus. In ATA extension mode, the IOCS16# signal indicates that a 16-bit buffer transfer is active on the host bus. This open drain signal is only driven on assertion(low). Attribute memory and I/O select : In PCMCIA mode, this signal is used to select attribute memory and I/O space. In ATA extension mode, this signal is used during DMA with the DREQ, IOR# and IOW# signals to transfer data between the host and the MX9691. This pin includes an internal pull-up resistor. Card enable 1 or Chip select 0: In PCMCIA mode,this signal is card enable 1. This signal can enable either even or odd numbered-address bytes onto HD7:0. In ATA extension mode, this signal accesses the MX9691 command block registers. This input is ignored during DMA data transfer, i.e. when the DACK# signal is low. This pin includes an internal pull-up resistor. Card enable 2 or Chip select 1: In PCMCIA mode,this signal is card enable 2. This signal can enable odd numbered-address bytes onto HD15:8. In ATA extension mode, this signal accesses the MX9691 control block registers. This pin includes an internal pull-up resistor. Input Acknowledge or DMA request : In PCMCIA mode, this signal is asserted when the MX9691 is configured to respond to I/O card read cycles at all addresses. In ATA extension mode, this signal is DREQ and is issued during DMA transfers to indicate that the MX9691 is ready for DMA transfer. Speaker or slave present : In PCMCIA mode, the output-enable for this signal is controlled by the card configuration registers. In ATA extension mode, this signal is used as the slave-present detector. Status change or pass diagnostics : In PCMCIA mode, this signal is used to indicate changes in the RDY/BSY#,WP signals in card con figuration registers. In ATA extension mode, this active low signal is used between two embedded ATA drive to indicate that the drive in slave mode has passed diagnostics.
REG#/DACK# 95
I
HCE1#/ CS1FX#
115
I
HCE2#/ CS3FX#
114
I
INPACK#/ DREQ
118
O
SPKR/DASP# 93
I/O
STSCHG/ PDIAG#
90
I/O
3
INDEX
MX9691
Microcontroller interface : Symbol D[15:0] No. 33-37, 39-41, 55-58, 60-63 3-5, 8-11, 22-24, 26-31 Type I/O Description DSP IO/RAM/ROM/FLASH memory array external data bus. These pins in clude internal pull-up resistors.
A[15:0]
I/O
PCE#
67
I/O
DCE#
68
I/O
RD#
65
I/O
WR#
66
I/O
NMI# INT1#
15 14
I I/O
In normal mode, these signals are output that used as DSP IO/RAM/ ROM external address. A14-A0 are for flash memory array address also. In upgrade mode, these address is used for ROM address that controlled by CYH,CYL registers. In ICE debugging mode, these ad dress are input,asserted by external MX93011 DSP. The internal DSP is disabled. These pins include internal pull-up resistors. In normal mode, this signal is output that is used as external program chip enable. In upgrade mode, this signal is drived to high. In ICE de bugging mode, this signal is input, asserted by external MX93011 DSP. The internal DSP is disabled. This pin includes a bus holder circuit. In normal mode, this signal is output that is used as external data chip enable. In upgrade mode, this signal is drived to high. In ICE debug ging mode, this signal is input, asserted by external MX93011 DSP. The internal DSP is disabled. This pin includes a bus holder circuit. In normal mode, this signal is output that is used as DSP IO/RAM/ ROM external read. In upgrade mode, this signal is output and as serted when the data register is read in host interface. In ICE debug ging mode, this signal is input, asserted by external MX93011 DSP. The internal DSP is disabled. This pin includes a bus holder circuit. In normal mode, this signal is output that is used as DSP IO/RAM/ ROM external write. In upgrade mode, this signal is drived to high. In ICE debugging mode, this signal is input, asserted by external MX93011 DSP. The internal DSP is disabled. This pin includes a bus holder cir cuit. Non maskable interrupt pin. This pin includes an pull-up resistor. In normal mode, this signal is input that is used as interrupt pin. Interrupt will be internally asserted also when data transfer done, or command end. In ICE debugging mode, this signal is output and as serted when data transfer done, or command end. This pin includes an pull-up resistor.
4
INDEX
MX9691
Symbol HOLD# No. 16 Type I/O Description In normal mode, this signal is input that is used as holding DSP clock down and release bus. Bus hold will be internally asserted also when upgrade mode enable. In ICE debugging mode, this signal is output and asserted when upgrade mode enable. In ICE debugging mode, this signal is output and asserted when upgrade mode enable. This pin includes an pull-up resistor. In normal mode, this signal is output that is used as ack to HOLD# signal. This signal will be internally sent to PCMCIA/ATA interface also when upgrade mode enable. In ICE debugging mode, this signal is input and ack to HOLD# when upgrade mode enable. This pin in cludes an pull-up resistor. External flag, this pin can be directly written by one DSP instruction. Default inactive (5 Volt output). In ICE debugging mode, this signal is used to reset CPU.
HLDA#
73
I/O
XF#/CPURST# 74
O
Flash Memory Interface : Symbol FA19/CLE No. 12 Type O Description In random mode, this signal is used as flash memory chip high address line 19. In sequential mode, this signal is used as flash memory chip command latch enable. In random mode, this signal is used as flash memory chip high address line 18. In sequential mode, this signal is used as flash memory chip address latch enable. This signal is used to select whether the MX9691 initializes in normal mode or in ICE debugging mode at poweron reset. If this pin go high, then the MX9691 will switch to normal mode at power-on reset,and if this pin remains low, then the MX9691 will initializes in ICE debugging mode. This pin includes an internal pull-up resistor. ICEMODE ICE debugging mode select : ICEMODE=1 --> Normal mode ICEMODE=0 --> ICE debugging mode
FA18/ALE/
20
I/O
5
INDEX
MX9691
Symbol FA17/EROM No. 21 Type I/O Description This signal is used as flash memory chip high address line 17. This signal is used to select whether the firmware store in flash memory array or in separate external ROM at power-on reset. If this pin go high, then the firmware will be executed in flash memory array, and if this pin remains low, then the firmware will be executed in separate external ROM. Store firmware in external ROM or Flash memory array: EROM = 0 --> Store in External ROM EROM = 1 --> Store in flash memory array This pin includes an internal pull-up resistor. This signal is used as flash memory chip high address line 16-15. These signals are used to select configuration in ATA extension mode at poweron reset. ATADET1 is connected to DSP's IPT1. ATADET0 is connected to DSP's IPT0. VDD is connected to IPT2. Master/Slave selection in ATA mode : ATADET1 ATADET0 mode selected 1 1 one drive 0 0 master of two drives 1 0 slave of two drives This power-on configuration can be accessed from PCMCIA/ATA port 601Ch bit3-2. These pins include internal pull-up resistors. Flash memory ouptut enable 1 for bank1: This signal will be asserted by flash memory read operation when flash memory read address latch, port 601Dh bit 8 = 1(i.e. FA23=1). Note: Flash memory access window is mapped to 32KW data and code space 8000h~ffffh. Flash memory ouptut enable 0 for bank0: This signal will be asserted by flash memory read operation when flash memory read address latch, port 601Dh bit 8 = 0(i.e. FA23=0). Flash memory write enable 1 for bank1: This signal will be asserted by flash memory write operation when flash memory write address latch, port 601Fh bit 8 = 1(i.e. FA23=1). Flash memory write enable 0 for bank0: This signal will be asserted by flash memory write operation when flash memory write address latch, port 601Fh bit 8 = 0(i.e. FA23=0).
FA[16:15]/ ATADET[1:0]
1-2
I/O
RDFLASH1#
54
O
RDFLASH0#
42
O
WRFLASH1#
19
O
WRFLASH0#
18
O
6
INDEX
MX9691
Symbol FCE[7:0]# No. 43-44,46-47, 49-52 Type O Description Flash memory chip enable 7-0 : In random mode, These signals are decoded from port 601Dh bit 7-5 when flash memory read or port 601Fh bit 7-5 when flash memory write. Decoding combination : bit7 bit6 bit5 FCE[7:0]# 000 11111110 001 11111011 010 11101111 011 10111111 100 11111101 101 11110111 110 11011111 111 01111111 In sequential mode, These are decoded from port 601Dh bit 7-5 only when port 601Eh bit 2 is set. Deep power down output 0 for bank0: This signal will put the flash memory chips of bank0 in deep power-down mode. PWD0# is active low;PWD0# high enables normal operation. PWD0# also locks out erase or program operation when active low providing data protection during power transitions. Power down pin PWD0# will be active if FA23=1. Deep power down output 1 for bank1: This signal will put the flash memory chips of bank1 in deep power-down mode. PWD1# is active low;PWD1# high enables normal operation. PWD1# also locks out erase or program operation when active low providing data protection during power transitions. Power down pin PWD1# will be active if FA23=0. Flash memory Ready/busy input: This signal indicate the state of erase or program operation in flash memory chips.This pin includes an internal pull-up resistor.
PWD0#
32
O
PWD1#
64
O
FRY/FBY#
13
I
7
INDEX
MX9691
Control ROM interface : Symbol ROMCS#/ FWIN# No. 75 Type O Description ROM chip select/Flash memory data buffer enable : In normal mode, this signal is used as ROM chip enable if firmware that stored in external ROM. In ICE debugging mode, this signal is used as flash memory data buffer (74640) enable if firmware that stored in flash memory array. ROM write enable/Flash memory data buffer direction control: In normal mode, this signal is used as ROM write enable if firmware that stored in external ROM. In ICE debugging mode, this signal is used as flash memory data buffer (74640) direction control if firmware that stored in flash memory array.
ROMWR#/ FDIR
76
O
Miscellaneous : Symbol X1 X2 X32I X32O TEST No. 79 78 71 70 81 Type I O I I I Description Crystal input. Crystal ouput. 32K Crystal input. 32K Crystal output. This signal is used to select the main system clock, either from external clock source if this signal is high or from internal PLL circuit if this signal is low. This pin includes an internal pull-up resistor. Power on reset, CMOS Schmite-triggered: The MX9691 include debouncing circuit to stabilize internal DSP reset signal. LED output: This signal is connected to external LED in debugging system to indicate system status. The LED will be turn-on during reset. The contorl firmware will turn off the LED after H/W initialization and pass diagnostics. If system fail, the control firmware will flash the LED to indicate some error occur. This signal will be high if port 601Ch bit0 set to 1 or OPTR bit2 set to 1. 5 volt Power pin Ground pin
PWR_RST# LED#
82 6
I O
VCC GND
17,45,53,72, 80,105,112 7,25,38,48, 59,69,77,91, 108,120
8
INDEX
MX9691
Power-on detection: (1). Store firmware in external ROM or Flash memory array : FA17/EROM = 0 --> Store in External ROM FA17/EROM = 1 --> Store in flash memory array (2). Master/Slave selection in ATA extension mode : FA16/ATADET1 FA15/ATADET0 mode selected 1 1 one drive 0 0 master of two drives 1 0 slave of two drives (3). ICE debugging mode select : FA18/ICEMDOE = 0 --> ICE debugging mode FA18/ICEMODE = 1 --> Normal mode (4). Flash memory data buffer control ROMCS# is replaced by FWIN# if ICE debugging mode & firmware in flash memory array ROMWR# is replaced by FDIR if ICE debugging mode & firmware in flash memory array (5). PCMCIA or ATA extension select HOE# HWE# mode 0 0 ATA extension mode others PCMCIA mode
System Memory Map : (1). Data Space : Address 0000h~007fh 0080h~07ffh 0800h~5fffh 6000h~63ffh 6400h~6fffh 7000h~73ffh 7400h~77ffh 7800h~7fffh 8000h~ffffh
Function & Usage Internal RAM (128W) to store control variables Internal RAM(1920W) for flash memory algorithm usage User define (22kW) I/O range(1kW): ATA CTL. use I/O range (6000h~601fh) User define (3kW) User define (1kW) Internal RAM (1kW) for expansion RAM or shadow ROM space ROM Data space(2kW) Flash memory access windows(32kW)
(2). Program Space : Address 0000h~77ffh 7800h~7fffh 8000h~ffffh
Function & Usage ROM program space (32kW) Unused Flash memory access windows(32kW)
9
INDEX
MX9691
Registers definition: (1). Register List : Type of Register PCMCIA/ATA Interface PC INTERRUPT CONTROL BUFFER MANAGER AND DMA ECC Control Flash Memory Interface
Location 6000h, 6001h, 6002h, 6003h, 6004h, 6005h, 6006h, 6007h, 600Bh, 6010h, 6011h, 6012h, 6013h, 6019h, 601Ah, 601Bh, 601Ch 6009h, 600Ah 6008h, 6014h, 6015h, 6016h, 6017h, 6018h 600Ch, 600Dh, 600Eh, 600Fh 601Dh, 601Eh, 601Fh
(2). Register Description : Port 6000h : Bit
Function Description AT CONTROL/STATUS REGISTER Default reset value : 01h R/W: DRIVE READY (drive 0) R/W: DRIVE SEEK COMPLETE (drive 0) R/W: CORRECTED DATA R: ATA INT. ENABLE R: AT SOFTWARE RESET R/W: HOST INTERRUPT R/W: ERROR BIT R/W: BUSY BIT
7 6 5 4 3 2 1 0
Port 6001h : Bit 7:0
Function Description Default reset value : 00h R/W: ERROR REGISTER (map to command block 1f1h)
Port 6002h : Bit 7:0
Function Description Default reset value : 01h R/W: SECTOR COUNT REGISTER (map to command block 1f2h)
10
INDEX
MX9691
Port 6003h : Bit 7:0
Function Description Default reset value : 01h R/W: SECTOR NUMBER REGISTER (map to command block 1f3h)
Port 6004h : Bit 7:0
Function Description Default reset value : 00h R/W: CYCLINDER LOW REGISTER (map to command block 1f4h)
Port 6005h : Bit 7:0
Function Description Default reset value : 00h R/W: CYCLINDER HIGH REGISTER (map to command block 1f5h)
Port 6006h : Bit 7:0
Function Description Default reset value : A0h R/W: DRIVE/HEAD REGISTER (map to command block 1f6h)
Port 6007h : Bit 7:0
Function Description Default reset value : 00h R: COMMAND REGISTER (map to command block 1f7h)
Port 6008h : Bit
Function Description BUFFER RAM SIZE CONTROL REGISTER Default reset value : 40h R/W: TEST MODE 1 for HAP/DAP test 0 : DISABLE 1 : ENABLE R/W: BIT WRITE GATE STATE OF DRIVE 0 : ENABLE 1 : DISABLE
7
6
11
INDEX
MX9691
Bit 5 Function Description R: PCMCIA/ATA 0 : ATA extension mode 1 : PCMCIA mode R/W: Auto DAP increment 0 : Disable 1 : Enable R/W: Shadow ROM control 0 : Disable 1 : Enable R/W: BUFFER RAM SIZE CONTROL 00x : 32KW 010 : 16KW 011 : 8KW 100 : 4KW 101 : 2KW 110 : 1KW 111 : 512W
4
3
2:0
Port 6009h : Bit
7 6 5 4 3 2 1 0
Function Description HOST INTERRUPT STATUS Default reset value : 00h R: Power-Down timer time-out detected R: Card configuration register write detected R: CIS accessed detected R: Hreset detected R: PC SRST(or PCMCIA SRST) DETECTED R: PC STATUS READ DETECTED R: PC SELECTION R: PC TRANSFER DONE
12
INDEX
MX9691
Port 600Ah : Bit
7 6 5 4 3 2 1 0
Function Description HOST INTERRUPT ENABLE Default reset value : 00h R/W: Power-Down timer time-out detected enable. R/W: Card configuration register write detected enable R/W: CIS accessed detected enable R/W: Hreset detected enable R/W: PC SRST(PCMCIA SRST) DETECTED ENABLE R/W: PC STATUS READ DETECTED ENABLE R/W: PC SELECTION ENABLE R/W: PC TRANSFER DONE ENABLE
Port 600Bh : Bit 7:0
Function Description Default reset value : 00h R: Feature register (map to command block 1f1h)
Port 600Ch : Bit
7
6
Function Description ECC CONTROL REGISTER Default reset value : 00h R/W: ECC FUNCTION SUSPEND 0 : NORMAL 1 : SUSPEND R/W: CORRECTION SPEED SELECT 0 : FULL SPEED 1 : HALF SPEED R/W: ENCODE/DECODE FUNCTION SELECTION 0 : ENCODE 1 : DECODE R/W: RESET ECC CIRCUIT 0 : RESET 1 : NORMAL R: UNCORRECTABLE ERROR FLAG R: CORRECTABLE ERROR FLAG R: CORRECTION DONE FLAG R/W: START ECC CORRECT FUNCTION ENABLE/DISABLE 0 : DISABLE 1 : ENABLE
5
4
3 2 1 0
13
INDEX
MX9691
Port 600Dh : Bit 15:0
Function Description Default reset value : 0000h R/W : ECC 0 REGISTER
Port 600Eh : Bit 15:0
Function Description Default reset value : 0000h R/W : ECC 1 REGISTER
Port 600Fh : Bit 15:0
Function Description Default reset value : 0000h R/W : ECC 2 REGISTER
Port 6010h : Bit 7:0
Function Description Default reset value : 00h R: Configuration Option register (map to attribute memory 200h)
Port 6011h : Bit 7:0
Function Description Default reset value : 00h R: Card Configuration and status register (map to attribute memory 202h)
Port 6012h : Bit 7:0
Function Description Default reset value : 0Ch R: Pin replacement register (map to attribute memory 204h)
Port 6013h : Bit 7:0
Function Description Default reset value : 00h R: Socket and copy register (map to attribute memory 206h)
14
INDEX
MX9691
Port 6014h : Bit 15:0
Function Description Default reset value : 0000h R/W : HOST ADDRESS POINTER
Port 6015h : Bit 15:0
Function Description Default reset value : 00ffh R/W : AT STOP POINTER
Port 6016h : Bit 15:0
Function Description Default reset value : 0000h R/W : DISK ADDRESS POINTER
Port 6017h : Bit
7 6 5
4
Function Description DMA CONTROL REGISTER Default reset value : 08h R/W: DRIVE READY (drive 1) R/W: DRIVE SEEK COMPLETE (drive 1) R/W: set BSY upon XFER done 0 : DISABLE 1 : ENABLE R/W: ENABLE AUTO INTERRUPTS - AT ONLY 0 : DISABLE 1 : ENABLE R/W: BUFFER RAM CHIP ENABLE 0 : ENABLE 1 : DISABLE R/W: HOST BUS DIRECTION 0 : START BUFFER -> AT BUS 1 : START AT BUS -> BUFFER WHEN SET R: A COMPLETION OF AT DMA XFER R/W: START DATA TRANSFER BETWEEN AT BUS AND BUFFER RAM 0 : DISABLE 1 : ENABLE
3
2
1 0
15
INDEX
MX9691
Port 6018h : Bit 15:0
Function Description R/W : ACCESS PORT INTO BUFFER RAM
Port 6019h : Bit 7 6 5 4 3 2
1 0
Function Description PCMCIA control register R: ATA extension mode R: Common memory mode R: I/O mode R/W: host ready R/W: no drive address R/W: Internal registers write pulse width 0 : 2 system clock 1 : 1 system clock R/W: Force ATA mode R/W: Force PCMCIA mode
Port 601Ah : Bit
7 6
5 4 3
Function Description Auxi_ctl_1 reg. Default reset value : 00h R/W : DASP R/W : Host Interrupt level mode or pulse mode select 0: Level mode 1: Pulse mode R/W : PDIAG R/W : DASP output enable R/W: write protect enable 0: Disable 1: Enable R/W: PDIAG output enable R/W: master/slave mode enable 0: Disable 1: Enable R/W: master/salve of ATA mode 0: master 1: slave
2 1
0
16
INDEX
MX9691
Port 601Bh : Bit
Function Description Auxi_ctl_2 reg. Default reset value : 00h Reserved. R/W: Force the CPU that fetch codes from flash memory array R/W: Force the system that become ICE debugging mode R/W: Host interface RESET polarity 0: Low active 1: High active R/W: Disk interrupt polarity 0: Low active 1: High active
7:4 3 2 1
0
Port 601Ch : Bit
Function Description Auxi_ctl_3 reg. Default reset value : 0000h Reserved R/W : Test mode 2 for timer 0 : Normal mode 1 : Test mode enable R : DRQ R : Time out status 1 : Time out event occurence R/W: Timer enable/disable 0 : Disable 1 : Enable
15 14
13 12 11
17
INDEX
MX9691
Port 601Ch : Bit 10:9
8
7
6
5:4
3:2
1
Function Description R/W: Power-down timer time-out select for 25MHz main clock 00 : 16 x 1.28 = 20.48 sec. 01 : 8 x 1.28 = 10.24 sec. 10 : 4 x 1.28 = 5.12 sec. 11 : 2 x 1.28 = 2.56 sec. R : ICE debugging mode detected 0 : ICE debugging mode 1 : Normal R/W : Inverted data bus for access flash memory. 0 : Inverted 1 : Non-inverted R: External ROM detect. 0: Firmware stored in external ROM 1: Firmware stored in flash memory array R/W: Shadow ROM space control 00 : 512 bytes, Range: 7400h ~ 74ffh 01 : 1Kbytes, Range: 7400h ~ 75ffh 10 : 1.5Kbytes, Range: 7400h ~ 76ffh 11 : 2Kbytes, Range: 7400h ~ 77ffh R : Master/Slave mode detect in ATA mode 00 : Master of two drives 10 : Slave of two drives 11 : One drive R/W: PIO/DMA mode select 0: PIO mode 1: DMA mode R/W: LED output
0
Port 601Dh : Bit 9:0
Function Description Default reset value : 0000h R/W : Flash memory Read address FA[24:15] latch for random mode When data space 8000h ~ ffffh is read, the output of the flash memory read address latch will be used.
18
INDEX
MX9691
For sequential mode this register has different definitions Default reset value : 0000h 9:8 Reserved 7:5 R/W: FCE select for sequential mode 000: FCE0 001: FCE2 010: FCE4 011: FCE6 100: FCE1 101: FCE3 110: FCE5 111: FCE7 4 R/W: Command latch enable (FA19/CLE) 0 : Disable 1 : Enable 3 R/W: Address latch enable (FA18/ALE) 0 : Disable 1 : Enable 2:0 Reserved
Port 601Eh : Bit
Function Description Flash memory control register Default reset value : 08Ah R/W: Flash memory deep power down control 0 0 : Enable Power Down pin PWD0# active or FA23=1 for 16Mbit Random access flash memory 1 : Disable R : Ready / Busy status 0 : BUSY 1 : READY R/W: Flash memory type select 00 : 4M flash memory /Bank 0 select for sequential select 01 : 16M flash memory /Bank 1 select for sequential select 10 : Reserved 11 : Reserved
7
6
5:4
19
INDEX
MX9691
Bit 3 Function Description R/W: Flash memory deep power down control 1 0 : Enable Power Down pin PWD1# active or FA23=0 for 16Mbit Random access flash memory 1 : Disable
Port 601Eh : Bit 2
1
0
Function Description R/W: CE# enable for sequential mode 0 : Disable 1 : Enable R/W: Sequential mode select 0 : Random mode 1 : Sequential mode R/W: Flash memory write pulse width control 0 : 1 system clock 1 : 2 system clock
Port 601Fh : Bit
Function Description Default reset value : 0000h R/W : Flash memory Write address FA[24:15] latch for random mode When data space 8000h ~ ffffh is write or program space 8000h ~ ffffh is read, the output of the flash memory write address latch will be used. For sequential mode this register is reserved.
20
INDEX
MX9691
ELECTRICAL SPECIFICATIONS
DC Characteristics: Ta = 0C to 70C, VCC = 5V10% Symbol VCC VIL VIH VOL VOH ICC1 ICC2 ICC3 ICC4 IL CIN COUT Parameter Power Supply voltage Input Low voltage Input High voltage Output Low voltage Output High voltage Supply Current 1 Supply Current 2 Supply Currect 3 Supply Current 4 Input Leakage Input Capacitance Output Capacitance Min 4.5 2.0 0.4 2.4 40 35 10 1 10 14 16 Max 5.5 0.8 Units V V V V V mA mA mA mA uA pf pf Conditions VCC=5V IOL=12mA f = 25Mhz, Activemode, CL = 0pf, VCC=5.5Volt, Temperature = 0C f = 25Mhz, Idle mode, CL = 0pf, VCC=5.5Volt, Temperature = 0C f = 25Mhz, Standby mode, CL = 0pf, VCC=5.5Volt, Temperature = 0C f = 0Mhz, Sleep mode, CL = 0pf, VCC=5.5Volt, Temperature = 0C 0< VIN < VCC VIN = 0V VOUT = 0V
Note: During transitions, inputs may undershoot to -2.0V for periods less than 20ns and overshoot to VCC + 2.0V for periods less than 20ns.
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MX9691
AC Characteristics : Ta = 0C to 70C, VCC = 5V10% DSP Interface Timing : Symbol Parameter Tcs Chip select access time Taa Address access time Trds Data setup time before RD# high Tdh Data hold time after RD# high Trd RD# to output delay from external access
Min 1.5Tc 1.5Tc 12 0
Max 4.5Tc 4.5Tc
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Units ns ns ns ns ns
Conditions
RD#
D[15:0] Trd
DCE#/PCE#
Tcs
Taa A[15:0] RD#
D[15:0]
Trds
Tdh
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MX9691
Reset Timing: Symbol Tw(rst)
Parameter Reset low pulse width
Min 3Tc
Max
Units ns
Conditions
Clock Timing: Symbol Tc(c) Tlpd(c) Thpd(c)
Description Clock cycle time Clock low pulse duration(Tc=40ns) Clock high pulse duration(Tc=40ns)
Min. 40 16 16
Typ.
Max. 24 24
Unit ns ns ns
CLK IN Thp PWR RST# Tc Tw(rst) Tlpd
Interrupt Timing: Symbol Description Tw INT1# low pulse duration Tf INT1# fall time
Min. 1.5Tc
Typ.
Max. 10
Unit ns ns
HOLD# Timing: Symbol Description Td(al-h) HLDA# low to address tri-state Td(hh-ha) HOLD# high to HLDA# high Ten(ah-a) Address driven after HLDA# high
Min. 0 0 0.5T-10
Typ. 0.5Tc 0.5Tc
Max. 0.5Tc+10 Tc
Unit ns ns ns
INT1
Tf Tw
HOLD# HLDA# Td(al-h) AD[15:0]
Td(hh-ha)
Ten(ah-a)
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MX9691
PCMCIA Bus Timing: Symbol Tdf(ha-iocs16) Tdr(ha-iocs16) Td(ior) Tha Tds Tdh
Description Min. IOCS16# fall time IOCS16# rise time HD bus asserted time from IOR# active Address hold time from IOW# or IOR# HD set up time before IOW# rising edge HD hold time after IOW# rising edge
Typ.
Max. 15 30 27 20 0 3
Unit ns ns ns ns ns ns
HA[10:0]
IOCS16#
Tdr(ha-iocs16) HCE[1:0]# IOR#
Tdr(ha-iocs16)
HD[15:0]
Td(ior)
Tha
HCE[1:0]#
LOW#
HD[15:0]
Tds
Tdr
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MX9691
Flash Memory Interface Timing: Symbol Parameter T(a-ce) FCE# fall time after DSP address decode Tas FCE# setup time before WRFLASH# falling edge Tw(wrflash) WRFLASH# low pulse duration T(rd-oe) RDFLASH# fall time after NRD# falling edge
Min 9 3 50 7
Max 14 5 11
Units 16 6 12
Conditions ns ns ns ns
A[15:0] FCE[7:0]#
WRFLASH
T(a-ce) RD#
Tas
Tw(wrflash)
RDFLASH#
T(rd-oe)
Latchup Characteristics : Input Voltage with respect to GND on all VCC pins Input Voltage with respect to GND on all I/O pins Current Includes all pins except GND. Test conditions : VCC=5.0V, one pin at a time. Min -2.0V -2.0V -100mA Max 12.0V VCC+2.0V +100mA
Revision History : Revison 1.2 Description Append Singal flows to Block Diagram(Page 14) Date NOV. 27, 1997
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MX9691
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-8888 FAX:+886-3-578-8887
EUROPE OFFICE:
TEL:+32-2-456-8020 FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100 FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-747-2309 FAX:+65-748-4090
TAIPEI OFFICE:
TEL:+886-3-509-3300 FAX:+886-3-509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088 FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900 FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
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