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| STLVDS385 +3.3V PROGRAMMABLE LVDS TRANSMITTER 24-BIT FLAT PANEL DISPLAY (FPD) LINK-85MHZ s s s s s s s s s s s 20 TO 85 MHz SHIFT CLOCK SUPPORT BEST-IN-CLASS SET & HOLD TIMES ON TxINPUTs Tx POWER CONSUMPTION <130 mW (typ) @85MHz GRAYSCALE Tx POWER-DOWN MODE <200W (max) SUPPORTS VGA, SVGA, XGA aND SINGLE/ DUAL PIXEL SXGA. NARROW BUS REDUCES CABLE SIZE AND COST UP TO 2.38 Gbps THROUGHPUT UP TO 297.5 Megabytes/sec BANDWIDTH 345 mV (typ) SWING LVDS DEVICES FOR LOW EMI PLL REQUIRES NO EXTERNAL COMPONENTS COMPATIBLE WITH TIA/EIA -644 LVDS STANDARD TSSOP56 DESCRIPTION The STLVDS385 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS ORDERING CODES Type STLVDS385BTR Temperature Range -10 to 70C link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 297.5 Mbytes/sec. The transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will inter operate with a Falling edge strobe Receiver without any translation logic. Package TSSOP56 (Tape & Reel) Comments 2000 parts per reel August 2003 1/14 STLVDS385 PIN CONFIGURATION PIN DESCRIPTION PlN N 1, 9, 26 2, 3, 4, 6, 7, 8, 10, 11, 12, 14, 15, 16, 18, 19, 20, 22, 23, 24, 25, 27, 28, 30, 50, 51, 52, 54, 55, 56 5, 13, 21, 29 17 31 32 33, 35 34 36, 43, 49 37, 41, 45, 47 38, 42, 46, 48 39 40 44 2/14 SYMBOL VCC TXIN GND R_FB TxCLKIN PWRDWN PLL GND PLL VCC LVDS GND TxOUT+ TxOUTTxCLK OUT+ TxCLK OUTLVDS VCC NAME AND FUNCTION Power Supply pins for TTL Inputs TTL level input. This includes: 8 Red, 8 Green, 8 Blue and 4 control linesFPLINE, FPFRAME, and DRDY (also referred to as HSYNC, VSYNC, Data Enable) Ground pins for TTL Inputs Programmable strobe select (See Table 1) TTL level clock input. Pin name TxCLK IN TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at power down Ground pins for PLL Power Supply pin for PLL Ground pins for LVDS outputs Positive LVDS differential data output Negative LVDS differential data output Positive LVDS differential clock output Negative LVDS differential clock output Power Supply pin for LVDS outputs STLVDS385 TABLE 1 PROGRAMMABLE TRANSMITTER PlN R_FB R_FB CONDITION R_FB = VCC R_FB = GND or NC STROBE STATUS Rising edge strobe Falling edge strobe ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VDO IOSD ESD ILATCH TJ Tstg Supply Voltage CMOS/TTL Input Voltage LVDS Driver Output Voltage LVDS Output Short Circuit Duration HBM EIAJ Latch Up Tolerance Junction Temperature Storage Temperature Range Parameter Value -0.3 to 4 -0.5 to (VCC + 0.3) -0.3 to (VCC + 0.3) Continuous 7 500 300 +150 -65 to +150 KV V mA C C Unit V V V Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. RECOMMENDED OPERATING CONDITIONS Symbol VCC TA VCC fTxCLKIN Supply Voltage Operating Free Air Temperature Supply Noise Voltage TxCLKIN frequency 20 Parameter Min. 3.0 0 Typ. 3.3 Max. 3.6 70 100 85 Unit V C mVPP MHz RECOMMENDED TRANSMITTER INPUT CHARACTERISTICS (VCC = 3.3V, TJ = -10 to 70C unless otherwise noted. Typical values are referred to TA = 25C) Symbol tCIT tCIP tCIH tCIL tXIT Parameter TxCLK IN Transition Time (Fig. 5) TxCLK IN Period (Fig. 6) TxCLK IN High Time (Fig. 6) TxCLK IN Low Time (Fig. 6) TxIN Transition Time Min. 1.0 11.76 0.35T 0.35T 1.5 T 0.5T 0.5T Typ. Max. 6.0 50 0.65T 0.65T 6.0 Unit ns ns ns ns ns ELECTRICAL CHARACTERISTICS LVCMOS/LVTTL DC SPECIFICATIONS (VCC = 3.3V, TJ = -10 to 70C unless otherwise noted. Typical values are referred to TA = 25C) Symbol VIH VIL VCL II Parameter High Level Input Voltage Low Level Input Voltage Input Clamp Voltage Input Current ICL = -18mA VI =0.4 V, 2.5 or VCC VI = GND -10 0 Test Conditions Min. 2.0 GND -0.79 Typ. Max. VCC 0.8 -1.5 10 Unit mV mV V A A 3/14 STLVDS385 LVDS DC SPECIFICATIONS (VCC = 3.3V, TJ = -10 to 70C unless otherwise noted. Typical values are referred to TA = 25C) Symbol VOD VOD Parameter Differential Output Voltage Change in VOD between Complimentary Output States Offset Voltage (Note 2) RL = 100 RL = 100 Test Conditions Min. 250 Typ. 345 Max. 450 35 Unit mV mV VOS VOS RL = 100 1.125 1.25 1.375 35 V mV IOS IOZ Change in VOS between RL = 100 Complimentary Output States Output Short Circuit Current VO = 0, Output Tri-State Current RL = 100 -3.5 1 -5 10 mA A POWERDOWN = 0, VO = 0 or VCC TRANSMITTER SUPPLY CURRENT (VCC = 3.3V, TJ = -10 to 70C unless otherwise noted. Typical values are referred to TA = 25C) Symbol ICCTW Parameter Transmitter Supply Current Worst Case Test Conditions RL = 100, CL = 5pF, Worst Case Pattern (Fig. 1, 3) RL = 100, CL = 5pF, 16 Grayscale Pattern (Fig. 1, 3) f = 32.5 MHz f = 40 MHz f = 65 MHz f = 85 MHz f = 32.5 MHz f = 40 MHz f = 65 MHz f = 85 MHz Min. Typ. 31 32 37 42 29 30 35 39 10 Max. 45 50 55 60 38 40 45 50 55 Unit mA ICCTG Transmitter Supply Current 16 Grayscale mA ICCTZ Transmitter Supply Current Power Down Powerdown = Low Driver Outputs in Tri-State under Power Down Mode A 4/14 STLVDS385 TRANSMITTER SWITCHING CHARACTERISTICS (VCC = 3.3V, TJ = -10 to 70C unless otherwise noted. Typical values are referred to TA = 25C) Symbol tLLHT tLLLT tTPP0 tTPP1 tTPP2 tTPP3 tTPP4 tTPP5 tTPP6 tTPP0 tTPP1 tTPP2 tTPP3 tTPP4 tTPP5 tTPP6 tTPP0 tTPP1 tTPP2 tTPP3 tTPP4 tTPP5 tTPP6 tSTC tHTC tCCD tCCD tJCC Parameter LVDS Low-to-High Transition Time (Fig. 4) LVDS High-to-Low Transition Time (Fig. 4) Transmitter Output Pulse Position for BIT 0 (Fig.11 - Note 3) Transmitter Output Pulse Position for BIT 1 Transmitter Output Pulse Position for BIT 2 Transmitter Output Pulse Position for BIT 3 Transmitter Output Pulse Position for BIT 4 Transmitter Output Pulse Position for BIT 5 Transmitter Output Pulse Position for BIT 6 Transmitter Output Pulse Position for BIT 0 (Fig.11 - Note 3) Transmitter Output Pulse Position for BIT 1 Transmitter Output Pulse Position for BIT 2 Transmitter Output Pulse Position for BIT 3 Transmitter Output Pulse Position for BIT 4 Transmitter Output Pulse Position for BIT 5 Transmitter Output Pulse Position for BIT 6 Transmitter Output Pulse Position for BIT 0 (Fig.11 - Note 3) Transmitter Output Pulse Position for BIT 1 Transmitter Output Pulse Position for BIT 2 Transmitter Output Pulse Position for BIT 3 Transmitter Output Pulse Position for BIT 4 Transmitter Output Pulse Position for BIT 5 Transmitter Output Pulse Position for BIT 6 TxIN Setup to TxCLK IN (Fig. 6) TxIN Hold to TxCLK IN (Fig. 6) TxCLK IN to TxCLK OUT Delay (Fig. 7) TxCLK IN to TxCLK OUT Delay (Fig. 7) Transmitter Jitter Cycle-to-Cycle (Fig. 12 - Note 4) f = 85 MHz f = 65 MHz f = 40 MHz TA = 25C, VCC = 3.3V f = 85 MHz f = 65 MHz f = 40 MHz -0.25 3.32 6.89 10.46 14.04 17.61 21.18 -0.20 2.00 4.20 6.39 8.59 10.79 12.99 -0.20 1.48 3.16 4.84 6.52 8.20 9.88 2.5 0 3.8 2.8 110 210 350 6.3 7.1 150 230 370 10 100 Test Conditions Min. Typ. 0.75 0.75 0 3.57 7.14 10.71 14.29 17.86 21.43 0 2.20 4.40 6.59 8.79 10.99 13.19 0 1.68 3.36 5.04 6.72 8.40 10.08 Max. 1.5 1.5 0.25 3.82 7.39 10.96 14.54 18.11 21.68 0.20 2.40 4.60 6.79 8.99 11.19 13.99 0.20 1.88 3.56 5.24 6.92 8.60 10.28 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps tPLLS tPDD Transmitter Phase Lock Loop Set (Fig. 8) Transmitter Power Down Delay (Fig. 10) ms ns Note 1: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except VOD and VOD). Note 2: VOS previously referred as VCM. Note 3: The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature range. This parameter is functionality tested only on Automatic Test Equipment (ATE). Note 4: The limits are based on bench characterization of the device's jitter response over the power supply voltage range. Output clock jitter is measured with a cycle-to-cycle jitter of 3ns applied to the input clock signal while data inputs are switching (See Figures 15 and 16). A jitter event of 3ns, represents worse case jump in the clock edge from most graphics controller VGA chips currently available. Note 5: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 6: The 16 grayscale test pattern tests device power consumption for a "typical" LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical stripes across the display. Note 7: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT). Note 8: Recommended pin to signal mapping. Customer may choose to define differently. 5/14 STLVDS385 AC TIMING DIAGRAMS Figure 1 : "Worst Case" Test Pattern (Note 5) 6/14 STLVDS385 Figure 2 : "16 Grayscale" Test Patter (Notes 6, 7, 8) 7/14 STLVDS385 Figure 3 : (Transmitter) LVDS Output Load Figure 4 : (Transmitter) LVDS Transition Time Figure 5 : (Transmitter) Input Clock Transition Time 8/14 STLVDS385 Figure 6 : (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe) Figure 7 : (Transmitter) Clock In to Clock Out Delay 9/14 STLVDS385 Figure 8 : (Transmitter) Phase Lock Loop Set Time Figure 9 : 28 Parallel TTL Data Inputs Mapped to LVDS Outputs 10/14 STLVDS385 Figure 10 : Transmitter Power Down Delay Figure 11 : Transmitter LVDS Output Pulse Position Measurement 11/14 STLVDS385 TSSOP56 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.45 0.17 0.09 13.9 7.95 6.0 0.5 BSC 8 0.75 0 0.020 0.05 0.9 0.27 0.20 14.1 8.25 6.2 0.0067 0.0035 0.547 0.313 0.236 0.0197 BSC 8 0.030 TYP MAX. 1.2 0.15 0.002 0.035 0.011 0.0079 0.555 0.325 0.244 MIN. TYP. MAX. 0.047 0.006 inch A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 7065590B 12/14 STLVDS385 Tape & Reel TSSOP56 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 8.7 17.2 1.4 3.9 11.9 12.8 20.2 60 30.4 8.9 17.4 1.6 4.1 12.1 0.342 0.677 0.055 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 1.197 0.350 0.685 0.063 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch 13/14 STLVDS385 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com 14/14 |
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