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SDRAM (Rev.0.2)
MITSUBISHI LSIs
Dec.9 8
Preliminary
M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
M2V56S20TP is a 4-bank x 16777216-word x 4-bit, M2V56S30TP is a 4-bank x 8388608-word x 8-bit, M2V56S40TP is a 4-bank x 4194304-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V56S20/30/40TP achieve very high speed data rate up to 100MHz, and are suitable for main memory or graphic memory in computer systems.
FEATURES
- Single 3.3v0.3V power supply - Clock frequency 100MHz - Fully Synchronous operation referenced to clock rising edge - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/full page (programmable) - Burst type- sequential / interleave (programmable) - Column access - random - Auto precharge / All bank precharge controlled by A10 - 8192 refresh cycles /64ms (4 banks concurrent refresh) - Auto refresh and Self refresh - Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16) - LVTTL Interface - 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
Max. Frequency
CAS Latency @100MHz
M2V56S20/30/40TP-7 M2V56S20/30/40TP-8
100MHz 100MHz
2 3
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Preliminary
M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM PIN CONFIGURATION (TOP VIEW) x4 x8 x16
Vdd Vdd NC DQ0 VddQ VddQ NC NC DQ0 DQ1 VssQ VssQ NC NC NC DQ2 VddQ VddQ NC NC DQ1 DQ3 VssQ VssQ NC NC Vdd Vdd NC NC /WE /WE /CAS /CAS /RAS /RAS /CS /CS BA0 BA0 BA1 BA1 A10/AP A10/AP A0 A0 A1 A1 A2 A2 A3 A3 Vdd Vdd
Vdd DQ0 VddQ DQ1 DQ2 VssQ DQ3 DQ4 VddQ DQ5 DQ6 VssQ DQ7 Vdd LDQM /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 Vdd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
Vss DQ15 VssQ DQ14 DQ13 VddQ DQ12 DQ11 VssQ DQ10 DQ9 VddQ DQ8 Vss NC,Vref UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 Vss
Vss DQ7 VssQ NC DQ6 VddQ NC DQ5 VssQ NC DQ4 VddQ NC Vss NC,Vref DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 Vss
Vss NC VssQ NC DQ3 VddQ NC NC VssQ NC DQ2 VddQ NC Vss NC,Vref DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 Vss
CLK CKE /CS /RAS /CAS /WE DQ0-15 DQM, DQMU/L A0-12 BA0,1 Vdd VddQ Vss VssQ
: Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O : Output Disable / Write Mask : Address Input : Bank Address Input : Power Supply : Power Supply for Output : Ground : Ground for Output
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400mil x 875mil 54pin 0.8mm pitch TSOP(II)
SDRAM (Rev.0.2)
MITSUBISHI LSIs
Dec.9 8
Preliminary
M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM DQ0 - 15
BLOCK DIAGRAM
I/O Buffer
Memory Array Bank #0
Memory Array Bank #1
Memory Array Bank #2
Memory Array Bank #3
Mode Register Control Circuitry
Address Buffer Clock Buffer A0-12 BA0,1 CLK CKE
Control Signal Buffer
/CS /RAS /CAS /WE DQMU/L
Type Designation Code M 2 V 56 S 4 0
This rule is applied to only Synchronous DRAM family.
TP - 8
Speed Grade 7: CL2@100MHz, 8: CL3@100MHz Package Type TP: TSOP(II) Process Generation Function Reserved for Future Use Organization 2n 2: x4, 3: x8, 4: x16 Synchronous DRAM Density 56: 256M bits Interface V:LVTTL, S:SSTL_3 Memory Style (DRAM) Mitsubishi Main Designation
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Preliminary
M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
PIN FUNCTION
CLK Input Master Clock: All other inputs are referenced to the rising edge of CLK. Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low. Chip Select: When /CS is high, any command means No Operation. Combination of /RAS, /CAS, /WE defines basic commands. A0-11 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-12. The Column Address is specified by A0-9,11. A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. Data In and Data out are referenced to the rising edge of CLK. Din Mask / Output Disable: When DQMU/L is high in burst write, Din for the current cycle is masked. When DQMU/L is high in burst read, Dout is disabled at the next but one cycle. Power Supply for the memory array and peripheral circuitry. VddQ and VssQ are supplied to the Output Buffers only.
CKE
Input
/CS /RAS, /CAS, /WE
Input Input
A0-12
Input
BA0,1 DQ0-15 DQM DQMU/L Vdd, Vss VddQ, VssQ
Input Input / Output Input Power Supply Power Supply
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Preliminary
M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
BASIC FUNCTIONS
The M2V56S20/30/40TP provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively. To know the detailed definition of commands, please see the command truth table.
CLK /CS /RAS /CAS /WE CKE A10
Chip Select : L=select, H=deselect Command Command Command Refresh Option @refresh command Precharge Option @precharge or read/write command define basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H] ACT command activates a row in an idle bank indicated by BA. Read (READ) [/RAS =H, /CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (autoprecharge,READA) Write (WRITE) [/RAS =H, /CAS =/WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (autoprecharge, WRITEA). Precharge (PRE) [/RAS =L, /CAS =H, /WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read /write operation. When A10 =H at this command, both banks are deactivated (precharge all, PREA). Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H] REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically.
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Preliminary
M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
COMMAND TRUTH TABLE
COMMAND Deselect No Operation Row Address Entry & Bank Activate Single Bank Precharge Precharge All Banks Column Address Entry & Write Column Address Entry & Write with Auto-Precharge Column Address Entry & Read Column Address Entry & Read with Auto-Precharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register Set MNEMONIC DESEL NOP ACT PRE PREA WRITE CKE n-1 H H H H H H CKE n X X X X X X /CS H L L L L L /RAS X H L L L H /CAS X H H H H L /WE BA0,1 X H H L L L X X V V X V A10 /AP X X V L H L A0-9, note 11-12 X X V X X V
WRITEA
H
X
L
H
L
L
V
H
V
READ
H
X
L
H
L
H
V
L
V
READA REFA REFS REFSX TERM MRS
H H H L L H H
X H L H H X X L
L L L H L L L
H L L X H H L
L
H H
V X X X X X L
H X X X X X L
V X X X X X V 1
L X H H L
H X H L L
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: 1. A7-9,11-12=L, A0-A6 =Mode Address
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Preliminary
M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
FUNCTION TRUTH TABLE
Current State IDLE /CS H L L L L L L L ROW ACTIVE H L L L L L L L L READ H L L L /RAS X H H H L L L L X H H H H L L L L X H H H /CAS X H H L H H L L X H H L L H H L L X H H L /WE X H L X H L H L X H L H L H L H L X H L H X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 Address Command DESEL NOP TBST NOP NOP ILLEGAL*2 Action
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS DESEL NOP TBST READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST Bank Active, Latch RA NOP*4 Auto-Refresh*5 Mode Register Set*5 NOP NOP NOP Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge Bank Active / ILLEGAL*2 Precharge / Precharge All ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst
Terminate Burst, Latch CA, READ / READA Begin New Read, Determine Auto-Precharge*3 WRITE / WRITEA ACT PRE / PREA REFA MRS Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge*3 Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL
L L L L L
H L L L L
L H H L L
L H L H L
BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add
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M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State WRITE /CS H L L L /RAS X H H H /CAS X H H L /WE X H L H X X BA BA, CA, A10 Address Command DESEL NOP TBST Action NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst
Terminate Burst, Latch CA, READ / READA Begin Read, Determine AutoPrecharge*3 WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge*3 Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL
L L L L L READ with AUTO PRECHARGE H L L L L L L L L WRITE with AUTO PRECHARGE H L L L L L L L L
H L L L L X H H H H L L L L X H H H H L L L L
L H H L L X H H L L H H L L X H H L L H H L L
L H L H L X H L H L H L H L X H L H L H L H L
BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add
READ / READA ILLEGAL WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST WRITE / WRITEA ACT PRE / PREA REFA MRS ILLEGAL Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL
READ / READA ILLEGAL ILLEGAL Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
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M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State PRE CHARGING /CS H L L L L L L L ROW ACTIVATING H L L L L L L L WRITE RECOVERING H L L L L L L L /RAS X H H H L L L L X H H H L L L L X H H H L L L L /CAS X H H L H H L L X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X H L X H L H L X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Address Command DESEL NOP TBST Action NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL*2
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS DESEL NOP TBST ILLEGAL*2 NOP*4 (Idle after tRP) ILLEGAL ILLEGAL NOP (Row Active after tRCD) NOP (Row Active after tRCD) ILLEGAL*2
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS DESEL NOP TBST ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP NOP ILLEGAL*2
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
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M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
FUNCTION TRUTH TABLE (continued)
Current State REFRESHING /CS H L L L L L L L MODE REGISTER SETTING H L L L L L L L /RAS X H H H L L L L X H H H L L L L /CAS X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Address Command DESEL NOP TBST Action NOP (Idle after tRC) NOP (Idle after tRC) ILLEGAL
READ / WRITE ILLEGAL ACT PRE / PREA REFA MRS DESEL NOP TBST ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Idle after tRSC) NOP (Idle after tRSC) ILLEGAL
READ / WRITE ILLEGAL ACT PRE / PREA REFA MRS ILLEGAL ILLEGAL ILLEGAL ILLEGAL
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and/or data-integrity are not guaranteed.
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M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
FUNCTION TRUTH TABLE for CKE
Current State SELFREFRESH*1 CKE n-1 H L L L L L L POWER DOWN H L L ALL BANKS IDLE*2 H H H H H H H L ANY STATE other than listed above H H L L CKE n X H H H H H L X H L H L L L L L L X H L H L /CS X H L L L L X X X X X L H L L L L X X X X X /RAS /CAS X X H H H L X X X X X L X H H H L X X X X X X X H H L X X X X X X L X H H L X X X X X X /WE X X H L X X X X X X X H X H L X X X X X X X Add X X X X X X X X X X X X X X X X X X X X X X INVALID Exit Self-Refresh (Idle after tRC) Exit Self-Refresh (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP (Maintain Self-Refresh) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State =Power Down Refer to Function Truth Table Begin CLK Suspend at Next Cycle*3 Exit CLK Suspend at Next Cycle*3 Maintain CLK Suspend Action
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command.
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M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
SIMPLIFIED STATE DIAGRAM
SELF REFRESH
REFS REFSX
MODE REGISTER SET
MRS
IDLE
REFA
AUTO REFRESH
CKEL
CLK SUSPEND
ACT CKEL CKEH
CKEH
POWER DOWN
ROW ACTIVE
WRITE WRITEA WRITE READA READ READ
CKEL
CKEL
WRITE WRITE SUSPEND CKEH
READ
CKEH
READ SUSPEND
WRITEA WRITEA CKEL READA
READA
CKEL PRE PRE PRE
WRITEA WRITEA SUSPEND CKEH
READA
CKEH
READA SUSPEND
POWER APPLIED
POWER ON
PRE
PRE CHARGE Automatic Sequence Command Sequence
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M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs. 2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200s. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.
CLK /CS /RAS /CAS /WE
V
BA0,1 A12-A0 BA0 BA1 A12 A11 A10 A9 0 0 0 0 0 0 A8 0 A7 0 A6 A5 A4 A3 BT A2 A1 BL A0
LTMODE
LATENCY MODE
CL 000 001 010 011 100 101 110 111
/CAS LATENCY R R 2 3 R R R R
BURST LENGTH
BL 000 001 010 011 100 101 110 111 0 1
BT=0 1 2 4 8 R R R Full Page
BT=1 1 2 4 8 R R R R
BURST TYPE
SEQUENTIAL INTERLEAVED
R: Reserved for Future Use
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M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
CLK Command Address DQ CL= 3 BL= 4 /CAS Latency
Read Y Q0 Q1 Q2 Q3 Write Y D0 D1 D2 D3
Burst Length Burst Type
Burst Length
Initial Address BL A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 8 0 1 0 1 0 1 4 0 1 0 1 2 2 3 0 1 3 0 1 0 0 1 1 2 4 5 6 7 0 1 5 6 7 0 1 2 6 7 0 1 2 3 7 0 1 2 3 0 0 1 2 3 1 2 3 4 0 1 2 3 1 2 3 4 2 3 4 5 Sequential 3 4 5 6 4 5 6 7 5 6 7 0
Column Addressing Interleaved 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 0 1 2 3 0 1 1 0 3 2 5 4 7 6 1 0 3 2 1 0 2 3 0 1 6 7 4 5 2 3 0 1 3 2 1 0 7 6 5 4 3 2 1 0 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
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256M Synchronous DRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Vdd VddQ VI VO IO Pd Topr Tstg Parameter Supply Voltage Supply Voltage for Output Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Ta = 25 C Conditions with respect to Vss with respect to VssQ with respect to Vss with respect to VssQ Ratings -0.5 ~ 4.6 -0.5 ~ 4.6 -0.5 ~ Vdd+0.5 -0.5 ~ VddQ+0.5 50 1000 0 ~ 70 -65 ~ 150 Unit V V V V mA mW C C
RECOMMENDED OPERATING CONDITIONS
(Ta=0 ~ 70C, unless otherwise noted)
Limits Symbol Vdd Vss VddQ VssQ VIH VIL Parameter Supply Voltage Supply Voltage Supply Voltage for Output Supply Voltage for Output High-Level Input Voltage all inputs Low-Level Input Voltage all inputs Min. 3.0 0 3.0 0 2.0 -0.3 Typ. 3.3 0 3.3 0 Max. 3.6 0 3.6 0 Vdd+0.3 0.8 Unit V V V V V V
CAPACITANCE
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Symbol CI(A) CI(C) CI(K) CI/O Parameter Input Capacitance, address pin Input Capacitance, control pin Input Capacitance, CLK pin Input Capacitance, I/O pin VI=1.4v f=1MHz VI=25mVrms Test Condition Limits Min. 2.5 2.5 2.5 4.0 Max. 5.0 5.0 4.0 6.5 Unit pF pF pF pF
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256M Synchronous DRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
Limits(max) Symbol Icc1 Icc2P Icc2PS Icc2N Icc2NS Icc3P Icc3PS Icc3N Icc3NS Icc4 Icc5 Icc6 Parameter Test Conditions 135 MHz TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 125 MHz 130 2 1 25 6 5 3 30 20 150 190 2 100 MHz 120 2 1 20 6 4 3 25 15 120 180 2 Unit Note mA mA mA mA mA mA mA mA mA mA mA mA 1 2 2,3 2,4 5 3,5 4,5 5
Operating Current (1bank) tCLK=min, tRC=min, BL=1 Idle Standby Current in Power Down Mode Idle Standby Current in Normal Mode Active Standby Current in Power Down Mode Active Standby Current in Normal Mode Burst Operating Current Auto-Refresh Current Self-Refresh Current tCLK=min, CKEVILmax tCLK=, CKEVILmax tCLK=min, CKEVIHmin tCLK=, CKEVIHmin tCLK=min, CKEVILmax tCLK=, CKEVILmax tCLK=min, CKEVIHmin tCLK=, CKEVIHmin tCLK=min, BL=4, gapless data tCLK=min, tRFC=min CKEVILmax
Notes 1. addresses are changed 3 times during tRC, only 1 bank is active & all other banks are idle 2. all banks are idle 3. input signals are changed one time during 3xtCLK 4. input signals are stable 5. all banks are active
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Limits Min. VOH(DC) VOL(DC) IOZ II High-Level Output Voltage (DC) Low-Level Output Voltage (DC) Off-state Output Current Input Current IOH=-2mA IOL= 2mA Q floating Vo=0 ~ VddQ VIH=0 ~ VddQ+0.3V -10 -10 2.4 0.4 10 10 Max. Unit V V A A
Symbol
Parameter
Test Conditions
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256M Synchronous DRAM
AC TIMING REQUIREMENTS
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3V, Vss = VssQ = 0V, unless otherwise noted) Input Pulse Levels: 0.8V to 2.0V Input Timing Measurement Level: 1.4V
Limits Symbol Parameter Min. tCLK tCH tCL tT tIS tIH tRC tRFC tRCD tRAS tRP tWR tRRD tCCD tRSC tSRX tREF CLK cycle time CLK High pulse width CLK Low pulse width Transition time of CLK Input Setup time (all inputs) Input Hold time (all inputs) Row Cycle time Refresh Cycle time Row to Column Delay Row Active time Row Precharge time Write Recovery time ACT to ACT Delay time Colum to Column Delay time Mode Register Set Cycle time Self Refresh Exit time Refresh period CL=2 CL=3 Max. Min. 10 10 3 3 1 2 1 70 80 20 50 20 20 20 10 20 10 64 120000 10 -7 Max. Min. 13 10 3 3 1 2 1 80 80 20 50 20 20 20 10 20 10 64 120000 10 -8 Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms Unit Note
CLK
1.4V Any AC timing is referenced to the input signal crossing through 1.4V.
Signal
1.4V
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256M Synchronous DRAM
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Limits Symbol Parameter Min. CL=2 tAC Access Time from CLK CL=3 CL=2 tOH Output Hold Time from CLK CL=3 tOLZ tOHZ Delay Time, Output Low impedance from CLK Delay Time, Output High impedannce from CLK 3 0 3 6 3 0 3 6 ns ns ns 3 6 3 6 ns ns Max Min. -7 Max 6 Min. -8 Max 6 ns Unit
Output Load Condition
VTT=1.4V 50 Vout 50pF VREF=1.4V
CLK
1.4V
DQ tOLZ tAC tOH tOHZ
1.4V
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SDRAM (Rev.0.2)
MITSUBISHI LSIs
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Preliminary
M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
OPERATIONAL DESCRIPTION
BANK ACTIVATE One of four banks is activated by an ACT command. An bank is selected by BA0-1. A row is selected by A0-12. Multiple banks can be active state concurrently by issuing multiple ACT commands. Minimum activation interval between one bank and the other bank is tRRD. PRECHARGE An open bank is deactivated by a PRE command. A bank to be deactivated is designated by BA0-1. When multiple banks are active, a precharge all command (PREA, PRE + A10=H) deactivates them at the same time. BA0-1 are "Don't Care" in this case. Minimum delay time of an ACT command after a PRE command to the same bank is tRP. Bank Activation and Precharge All (BL=4, CL=3)
CLK Command A0-9,11-12 A10 BA0-1 DQ ACT
tRRD
ACT
tRCD
READ Yb 0 01 Qb0 Qb1
PRE
tRP
ACT Xa
Xa Xa 00
Xb Xb 01
1
Xa 00
Qb2
Qb3
Precharge All
READ A READ command can be issued to any open bank. The start address is specified by A0-9,11(x4). 1st output data is available after the /CAS Latency from the READ. The consecutive data length is defined by the Burst Length. The address sequence of the burst data is defined by the Burst Type. Minimum delay time of a READ command after an ACT command to the same bank is tRCD. When A10 is high at a READ command, auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT,TERM) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at the BL after READA. The next ACT command can be issued after (BL + tRP) from the previous READA. In any case, tRCD+BL tRASmin must be met. MITSUBISHI ELECTRIC
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SDRAM (Rev.0.2)
MITSUBISHI LSIs
Dec.9 8
Preliminary
M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
Multi Bank Interleaving Read (CL=2, BL=4)
CLK Command A0-9,11-12 A10 BA0-1 DQ ACT
tRCD
READ Ya 0 00
ACT
tRCD
READ PRE
tRP
ACT Xa
Xa Xa 00
Xb Xb 01 Qa0 Qa1
Yb 0 01 Qa2 Qa3 Qb0 0
Xa 00 Qb1 Qb2 Qb3
Read with Auto-Precharge (CL=2, BL=4)
CLK Command A0-9,11-12 A10 BA0-1 DQ ACT
tRCD
READ
BL tRP
ACT Xa Xa 00 Qa0 Qa1 Qa2 Qa3
Xa Xa 00
Ya 1 00
internal precharge starts
Auto-Precharge Timing (READ, BL=4)
CLK Command DQ DQ ACT
tRCD
READ
BL
ACT Qa0 Qa1 Qa0 Qa2 Qa1 Qa3 Qa2 Qa3
CL=2 CL=3
internal precharge starts
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SDRAM (Rev.0.2)
MITSUBISHI LSIs
Dec.9 8
Preliminary
M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
WRITE A WRITE command can be issued to any open bank.The start address is specified by A0-9,11(x4). 1st input data is set at the same cycle as the WRITE. The consecutive data length to be written is defined by the Burst Length. The address sequence of burst data is defined by the Burst Type. Minimum delay time of a WRITE command after an ACT command to the same bank is tRCD. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, auto-precharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT, TERM) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at tWR after the last input data cycle. The next ACT command can be issued after (BL + tWR -1 +tRP) from the previous WRITEA. In any case, tRCD + BL + tWR -1 tRASmin must be met. Write (BL=4)
CLK Command A0-9,11-12 A10 BA0-1 DQ ACT
tRCD
Write
BL
PRE
tRP
ACT Xa
Xa Xa 00
Ya 0 00
tWR
0
Xa 00
Da0
Da1
Da2
Da3
Write with Auto-Precharge (BL=4)
CLK Command A0-9,11-12 A10 BA0-1 DQ ACT
tRCD
Write
BL tRP
ACT Xa Xa 00
tWR
Xa Xa 00
Ya 1 00 Da0 Da1 Da2 Da3
internal precharge starts
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SDRAM (Rev.0.2)
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Dec.9 8
Preliminary
M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
BURST INTERRUPTION [ Read Interrupted by Read ] Burst read operation can be interrupted by new read of any bank. Random column access is allowed. READ to READ interval is minimum 1 CLK. Read interrupted by Read (CL=2, BL=4)
CLK Command A0-9,11-12 A10 BA0-1 DQ READ Ya 0 00 Qa0 READ READ Ya 0 00 Qa1 Yb 0 10 Qa2 Qa0 Qb0 Qb1 Qb2 Qb3
[ Read Interrupted by Write ] Burst read operation can be interrupted by write of any bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled automatically 1 cycle after WRITE assertion. Read interrupted by Write (CL=2, BL=4)
CLK Command A0-9,11-12 A10 BA0-1 ACT Xa Xa 00 READ Ya 0 00 Write Ya 0 00
DQM DQ Qa0 Da0 Da1 Da2 Da3
Output disable by DQM
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SDRAM (Rev.0.2)
MITSUBISHI LSIs
Dec.9 8
Preliminary
M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
[ Read Interrupted by Precharge ] Burst read operation can be interrupted by precharge of the same bank . READ to PRE interval is minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. Read interrupted by Precharge (BL=4)
CLK Command READ PRE
DQ Command READ
Q0 PRE
Q1
Q2
CL=2
DQ Command READ PRE Q0 Q1
DQ
Q0
Command
READ
PRE
DQ Command READ PRE
Q0
Q1
Q2
CL=3
DQ Command READ PRE Q0 Q1
DQ
Q0
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SDRAM (Rev.0.2)
MITSUBISHI LSIs
Dec.9 8
Preliminary
M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
[ Read Interrupted by Burst Terminate ] Similarly to the precharge, a burst terminate command can interrupt burst read operation and disable the data output. The terminated bank remains active. READ to TERM interval is minimum 1 CLK. A TERM command to output disable latency is equivalent to the /CAS Latency. Read interrupted by Terminate (BL=4)
CLK Command READ TERM
DQ Command READ
Q0 TERM
Q1
Q2
CL=2
DQ Command READ TERM Q0 Q1
DQ
Q0
Command
READ
TERM
DQ Command READ TERM
Q0
Q1
Q2
CL=3
DQ Command READ TERM Q0 Q1
DQ
Q0
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SDRAM (Rev.0.2)
MITSUBISHI LSIs
Dec.9 8
Preliminary
M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
[ Write Interrupted by Write ] Burst write operation can be interrupted by new write of any bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK. Write interrupted by Write (CL=2, BL=4)
CLK Command A0-9,11-12 A10 BA0-1 DQ Write Ya 0 00 Da0 Da1 Da2 Write Ya 0 00 Da0 Write Yb 0 10 Db0 Db1 Db2 Db3
[ Write Interrupted by Read ] Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is "Don't Care". Write interrupted by Read (CL=2, BL=4)
CLK Command A0-9,11-12 A10 BA0-1 DQ ACT Xa Xa 00 Write Ya 0 00 Da0 Da1 READ Ya 0 00 Qa0 Qa1 Qa2 Qa3
don't care
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SDRAM (Rev.0.2)
MITSUBISHI LSIs
Dec.9 8
Preliminary
M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
[ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank. Write recovery time (tWR) is required from the last data to PRE command. During write recovery, data inputs must be masked by DQM. Write interrupted by Precharge (BL=4)
CLK Command A0-9,11-12 A10 BA0-1 DQM
tWR
ACT Xa 0 00
Write Ya 0 00
PRE
tRP
ACT Xa
0 00
0 00
DQ
Da0
Da1
[ Write Interrupted by Burst Terminate ] Burst terminate command can terminate burst write operation. In this case, the write recovery time is not required and the bank remains active. WRITE to TERM interval is minimum 1 CLK. Write interrupted by Terminate (BL=4)
CLK Command A0-9,11-12 A10 BA0-1 DQ ACT Xa 0 00 Write Ya 0 00 Da0 Da1 TERM Write Ya 0 00 Da0 Da1 Da2 Da3
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SDRAM (Rev.0.2)
MITSUBISHI LSIs
Dec.9 8
Preliminary
M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
[ Write with Auto-Precharge Interrupted by Write / Read to another Bank ] Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT comand can be issued after (BL+tWR-1+tRP) from the WRITEA. Auto-precharge interruption by a command to the same bank is inhibited. WRITEA interrupted by WRITE to another bank (CL=2, BL=4)
CLK Command A0-9,11-12 A10 BA0-1 DQ Write Ya 1 00 Da0 Da1 Write
BL tRP
ACT Xa
tWR
Yb 0 10 Db0 Db1 Db2 Db3
Xa 00
auto-precharge
interrupted
activate
WRITEA interrupted by READ to another bank (CL=2, BL=4)
CLK Command A0-9,11-12 A10 BA0-1 DQ Write Ya 1 00 Da0 Da1 interrupted Read
BL tRP
ACT Xa
tWR
Yb 0 10 Qb0 Qb1 Qb2
Xa 00
Qb3 activate
auto-precharge
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SDRAM (Rev.0.2)
MITSUBISHI LSIs
Dec.9 8
Preliminary
M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
[ Read with Auto-Precharge Interrupted by Read to another Bank ] Burst read with auto-precharge can be interrupted by read to another bank. Next ACT comand can be issued after (BL+tRP) from the READA. Auto-precharge interruption by a command to the same bank is inhibited. READA interrupted by READ to another bank (CL=2, BL=4)
CLK Command A0-9,11-12 A10 BA0-1 DQ auto-precharge Read Ya 1 00 Read
BL tRP
ACT Xa Xa 00 Qa1 Qb0 Qb1 Qb2 activate Qb3
Yb 0 10 Qa0
interrupted
Full Page Burst Full page burst length is available for only the sequential burst type. Full page burst read / write is repeated untill a Precharge or a Burst Terminate command is issued. In case of the full page burst, a read / write with auto-precharge command is illegal.
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SDRAM (Rev.0.2)
MITSUBISHI LSIs
Dec.9 8
Preliminary
M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
AUTO REFRESH Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H) command. The refresh address is generated internally. 8192 REFA cycles within 64ms refresh 256Mbit memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an autorefresh, all banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any command must not be issued before tRFC from the REFA command.
Auto-Refresh
CLK /CS /RAS /CAS /WE CKE A0-12 BA0-1 minimum tRFC
NOP or DESELECT
Auto Refresh on All Banks
Auto Refresh on All Banks
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SDRAM (Rev.0.2)
MITSUBISHI LSIs
Dec.9 8
Preliminary
M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enabled input. All other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE (REFSX) for longer than tSRX. After (tRFC + 1CLK) from REFSX all banks are in the idle state and a new command can be issued, but DESEL or NOP commands must be asserted till then.
Self-Refresh
CLK
Stable CLK
/CS /RAS /CAS /WE CKE
NOP
tSRX
A0-12 BA0-1
new command X 00
Self Refresh Entry
Self Refresh Exit
minimum tRFC +1 CLOCK for recovery
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SDRAM (Rev.0.2)
MITSUBISHI LSIs
Dec.9 8
Preliminary
M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
CLK SUSPEND CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle. A command at the suspended cycle is ignored.
ext.CLK
CKE
int.CLK
Power Down by CKE
CLK CKE Command
PRE NOP NOP Standby Power Down
NOP NOP NOP
NOP NOP
CKE Command
ACT NOP NOP
Active Power Down
NOP NOP NOP
NOP NOP
DQ Suspend by CKE
CLK CKE Command
Write READ
DQ
D0
D1
D2
D3
Q0
Q1
Q2
Q3
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SDRAM (Rev.0.2)
MITSUBISHI LSIs
Dec.9 8
Preliminary
M2V56S20/ 30/ 40/ TP-7, -8
256M Synchronous DRAM
DQM CONTROL DQMU/L is a dual functional signal defined as the data mask for writes and the output disable for reads. During writes, DQMU/L masks input data word by word. DQMU/L to write mask latency is 0.During reads, DQMU/L forces output to Hi-Z word by word. DQMU/L to output Hi-Z latency is 2.
DQM Function
CLK Command DQMU/L
Write READ
DQ
D0
D2
D3
Q0
Q1
Q3
masked by DQMU/L=H
disabled by DQMU/L=H
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