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Bookly Micro
8 Megabit (1M x 8) Flash Memory AC39VF088
DEVICE FEATURES
3/4 Single Power Supply - Full voltage range: 2.7 to 3.6 volt for both read and write operations 3/4 Sector-Erase Capability Uniform 4Kbyte sectors 3/4 Block-Erase Capability - Uniform 64Kbyte blocks 3/4 Read Access Time - Access time: 70 and 90 ns 3/4 Power Consumption 3/4 Automatic Write Timing
- Internal VPP Generation 3/4 End-of-Program or End-of-Erase Detection
Data# Polling Toggle Bit 3/4 CMOS I/O Compatibility 3/4 JEDEC Standard - Pin-out and software command sets compatible with single-power supply Flash memory 3/4 High Reliability:
-
-
-
Active current: 15 mA (Typical) Standby current: 4 A (Typical)
3/4 Erase Features - Sector-Erase Time: 18 ms (Typical) - Block-Erase Time: 18 ms (Typical) - Chip-Erase Time: 45 ms (Typical) - Byte-Program Time: 14s (Typical) - Chip Rewrite Time: 15 seconds (Typical)
-
Endurance cycles: 100K (Typical) Data retention: 10 years
3/4 Package Option - 48-pin TSOP
This preliminary data sheet contains product specifications which are subject to change without notice.
AC39VF088
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AC39VF088
PRODUCT DESCRIPTION
The AC39VF088 is a 1M x 8 CMOS Flash manufactured with Actrans' proprietary Split-Gate Flash memory technology. The AC39VF088 uses 2.7-3.6V power supply for Program and Erase. The AC39VF088 conforms to JEDEC standard pin outs for x8 memories. Featuring high performance Byte-Program, the AC39VF088 devices provide a typical ByteProgram time of 14 sec. The devices use Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation. To protect against inadvertent write, they have on -chip hardware and software data protection schemes. Designed, manufactured and tested for a wide spectrum of applications, these devices are offered with a typically guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 10 years. The AC39VF088 devices are suited for applications that require memories with convenient and economical updating of program, data or configuration. For all system applications, they improve significantly the performance and reliability while lowering power consumption. They consume less energy during Erase and Program operations as compared to alternative flash technologies. When programming or erasing a flash device, the total energy consumption is a function of the applied voltage, current, and time of operation. Since for any given voltage range, Actrans' technology uses less current to program and has a shorter erase time, the total energy consumption during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for applications of program, data and configuration storage. The technology provides fixed Erase and Program times, which is independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies whose Erase and Program times increase with accumulated Erase and Program cycles. To meet surface mount requirements, the AC39VF088 is offered in package types of 48-pin TSOP, and known good die (KGD). For KGD, please contact Actrans System Inc. or its representatives for detailed information.
Table 1. PIN DESCRIPTION
Name of the Pin A0-A19 DQ7-DQ0 CE# OE# WE# VDD VSS NC Function 20 addresses Data inputs/outputs Chip enable Output enable Write enable 2.7-3.6 volt single power supply Device ground Pin not connected internally
This preliminary data sheet contains product specifications which are subject to change without notice.
AC39VF088
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AC39VF088
ORDERING INFORMATION Standard Products
The order number is defined by a combination of the following elements. AC39VF088
-70 E C
Temperature Range
C = Commercial (0C to +70C) I = Industrial (-40C to +85C)
Package Type
E = TSOP (type 1, die up, 12mm x 20mm) KGD = Known Good Die
Speed Option
70 90 ** **R = 70ns = 90ns = 2 digits: Indicates speed in ns; device is full voltage range, VCC = 2.7-3.6V = 2 digits: Indicates speed in ns; "R" indicates regulated voltages range, VCC=3.0 -3.6V
Device Number/Description
AC39VF088 8 Megabit (1M x 8-Bit) Flash Memory 2.7-3.6 Volt only Read, Program and Erase
Valid Combinations for TSOP 48Pin Package AC39VF088-70 EC, EI AC39VF088-70R EC, EI AC39VF088-90 EC, EI AC39VF088-90R EC, EI Valid Combinations for FBGA 48 Ball Package Order Number Package Marking AC39VF088-70 WAC, WAI V088-70 C, I AC39VF088-70R WAC, WAI V088-70R C, I AC39VF088-90 WAC, WAI V088-90 C, I AC39VF088-90R WAC, WAI V088-90R C, I Valid Combinations: Valid Combinations list the configurations that are supported in volume for this device.
This preliminary data sheet contains product specifications which are subject to change without notice.
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AC39VF088
Functional Block Diagram
Flash Memory Array X-Decoder
Memory Address
Address Buffer & Latches Y-Decoder
CE# OE# WE# Control Logic I/O Buffers and Data Latches
DQ7-DQ0
Pin Assignments
A16 A15 A14 A13 A12 A11 A10 A9 NC NC WE# NC NC NC NC A19 A18 A8 A7 A6 A5 A4 A3 A2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Standard TSOP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A17 NC V SS A0 DQ7 NC DQ6 NC DQ5 NC DQ4 VDD NC DQ3 NC DQ2 NC DQ1 NC DQ0 OE# V SS CE# A1
This preliminary data sheet contains product specifications which are subject to change without notice .
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AC39VF088
DEVICE OPERATION
The AC39VF088 devices use Commands to initiate the memory operation functions. The Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 20 s. See Figures 2 and 3 for WE# and CE# controlled Program operation timing diagrams and Figure 14 for flowchart. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored.
Byte Program
The AC39VF088 devices are programmed on a byte-by-byte basis. Before programming, the sector where the byte locates must be fully erased. The Program operation is accomplished in three steps. The first step is a three-byte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last; and the data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth
Read
The Read operation of the AC39VF088 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram in Figure 1 for further details.
Table 2: AC39VF088 Device Operation
Operation
Read Program Erase Standby Write Inhibit Write Inhibit Software Mode Product Identification
CE# OE# WE# VIL VIL VIL VIH X X VIL VIL VIH VIH X VIL X VIL VIH VIL VIL X X VIH VIH
DQ DOUT DIN X
1
Address AIN AIN Sector or Block address, XXH for Chip-Erase X X X See Table 3
High Z High Z/DOUT High Z/DOUT
1. X can be VIL or V IH, but no other value.
This preliminary data sheet contains product specifications which are subject to change without notice.
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AC39VF088
Write Command/Command Sequence
The AC39VF088 provides two software means to detect the completion of a write (Program or Erase) cycle in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the write operation is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit method. See Figures 7 and 8 for timing waveforms. Any commands issued during the Sector or Block Erase operation are ignored.
Data# Polling (DQ7)
When the AC39VF088 is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce the true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Program operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 4 for Data# Polling timing diagram and Figure 15 for a flowchart.
Chip Erase
The AC39VF088 provides Chip-Erase feature, which allows the user to erase the entire memory array to the "1" state. This is useful and convenient when the entire device must be quickly erased. The Chip -Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address AAAH in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid reads are Toggle Bit and Data# Polling. See Table 3 for the command sequence, Figure 6 for timing diagram, and Figure 17 for the flowchart. Any commands issued during the Chip-Erase operation are ignored.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 5 for Toggle Bit timing diagram and Figure 15 for a flowchart.
Sector/Block Erase
The AC39VF088 offers both Sector-Erase and Block-Erase modes. The Sector- (or Block-) Erase operation allows the system to erase the devices on a sector-by-sector (or block-by-block) basis. The sector architec ture is based on uniform sector size of 4 KByte. The Block-Erase mode is based on uniform block size of 64 KByte. The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing
Data Protection
The AC39VF088 provides both hardware and software features to protect the nonvolatile data
This preliminary data sheet contains product specifications which are subject to change without notice.
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AC39VF088
from inadvertent writes. command sequence.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
Product Identification
The product identification mode identifies the device as the AC39VF088. This mode may be assessed by software operations. Users may use the Software Product Identifiaction operation to identify the part(i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 3 for software operation, Figure 9 for the Software Entry and Read timing diagram and Figure 14 for the Software ID Entry command sequence flowchart.
Software Data Protection (SDP)
The AC39VF088 provides the JEDEC approved Software Data Protection scheme for all data iteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three -byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of sixbyte sequence. This group of devices is shipped with the Software Data Protection permanently enabled. See Table 3 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within T . The contents of DQ15-DQ8 can RC be VIL or VIH , but n other value, during any SDP o
Product Identification Mode Exit
In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read operation. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., command is ignored during an internal Program or Erase operation. See Table 3 for software command and Figure 14 for a flowchart.
This preliminary data sheet contains product specifications which are subject to change without notice.
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AC39VF088
Table 3: Software Command Sequence
Command Sequence 1st Bus Write Cycle Addr 1 Data2 AAAH AAH AAAH AAH AAAH AAH AAAH AAH AAAH AAH 2nd Bus Write Cycle Addr1 Data2 555H 55H 555H 55H 555H 55H 555H 55H 555H 55H 3rd Bus Write Cycle Addr1 Data 2 AAAH A0H AAAH 80H AAAH 80H AAAH 80H AAAH 90H 4th Bus Write Cycle Addr1 Data2 2 WA Data AAAH AAH AAAH AAH AAAH AAH 5th Bus 6th Bus Write Cycle Write Cycle Addr1 Data2 Addr 1 Data2
Byte Program Sector Erase 555H 55H SAX4 30H Block Erase 555H 55H BAX4 50H Chip Eras e 555H 55H AAAH 10H Software ID Entry 5,6 Manufacture ID AAAH AAH 555H 55H AAAH 90H 000H 07FH Manufacture ID AAAH AAH 555H 55H AAAH 90H 007H 07FH Manufacture ID AAAH AAH 555H 55H AAAH 90H 080H 01FH Device ID AAAH AAH 555H 55H AAAH 90H 001H 21H 7 Software ID Exit XXH F0H 1. Address format A14-A0 (Hex), Addresses A19-A15 can be VIL or VIH , but no other value, for the Command sequence. 2. DQ7-DQ0 can be VIL or VIH, but no other value, for the Command sequence. 3. WA = Program Byte address. 4. SAX for Sector -Erase; uses A19-A12 address lines. BAX for Block-Erase; uses A19-A16 address lines. 5. The device does not remain in Software Product ID mode if powered down. 6. Both Software ID Exit operations are equivalent. 7. Please refer to figure 9 for more information.
This preliminary data sheet contains product specifications which are subject to change without notice.
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AC39VF088
ABSOLUTE MAXIMUM RATINGS (Applied conditions greater than those listed under "Absolute
Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ..................................................................................... -55C to 125C Storage Temperature ............................................................................................ -65C to 150C D.C. Voltage on Any Pin to Ground Potential ...................................................... -0.5 V to V DD+0.5V Transient Voltage (<20ns) on Any Pin to Ground Potential..................................... -2.0V to VDD +2.0V Voltage on A9 Pin to Ground Potential..................................................................... -0.5 V to 13.2V Package Power Dissipation Capability (Ta=25C).................................................................... 1.0W Surface Mount Lead Soldering Temperature (3 Seconds)......................................................... 240C Output Short Circuit Current (Note 1).....................................................................................50mA Note 1: Output shorted for no more than one second. No more than one output shorted at a time.
Table 4: Operating Range
Model Name AC39VF088 Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD 2.7~3.6V 2.7~3.6V
AC CONDITIONS OF TEST
Input Rise/Fall Time..................................................................................5ns Output Load............................................................................................CL=30pF for 55Rns Output Load............................................................................................CL=100pF for 70ns/90ns See Figures 14 and 15
Table 5: DC CHARACTERISTICS
CMOS Compatible
Parameter Description IDD Power Supply Current Read Program and Erase Standby VDD Current Input Leakage Current Output Leakage Current Input Low Voltage Input Low Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Output Low Voltage Output High Voltage Test Conditions Address Input =VIL/VIH , at f=1/TRC Min, VDD=VDD Max CE#=OE#=VIL, WE#=VIH, all I/Os open CE#=WE#=V IL, OE#=VIH, CE#=VIHC , VDD=VDD Max VIN=GND to VDD, VDD =VDD Max VOUT=GND to VDD, VDD =VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Max VDD=VDD Max IOL=100A, VDD=VDD Min IOH=-100A, VDD =VDD Min Min Max Unit
ISB ILI ILO VIL VILC VIH VIHC VOL VOH
30 30 30 1 10 0.8 0.3 0.7 VDD VDD -0.3 0.2 VDD -0.2
mA mA A A A V V V V V V
This preliminary data sheet contains product specifications which are subject to change without notice.
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AC39VF088
Table 6: Recommended System Power-up Timing
Description Min Unit TPU-READ Power-up to Read Operation 100 s 1 TPU-WRITE Power-up to Program/Erase Operation 100 s 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
1
Parameter
Table 7: Capacitance (Ta=25 C, f=1Mhz, other pins open)
Parameter Description Test Conditions Max 1 CI/O I/O Pin Capacitance VI/O=0V 12pF 1 CIN Input Capacitance VIN=0V 6pF 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Table 8: Reliability Characteristics
Symbol Parameter Min Specification Unit Test Method 1 NEND Endurance 10,000 Cycles JEDEC Standard A117 1 TDR Data Retention 10 Years JEDEC Standard A103 1 ILTH Latch Up 100+IDD mA JEDEC Standard 78 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
AC CCHARACTERISTICS Table 9: Read Cycle Timing Parameters
Symbol TRC TCE TAA TOE 1 TCLZ 1 TOLZ 1 TCHZ 1 TOHZ 1 TOH Symbol Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change Parameter 70REC Min Max 70 70 70 35 0 0 20 20 0 70EC Max 90REC Min Max 90 90 90 45 0 0 30 30 0 90EC Min 90 Max Unit ns ns ns ns ns ns ns ns ns Unit
TRC Read Cycle Time ns TCE Chip Enable Access Time 70 90 ns TAA Address Access Time 70 90 ns TOE Output Enable Access Time 35 45 ns 1 TCLZ CE# Low to Active Output 0 0 ns 1 TOLZ OE# Low to Active Output 0 0 ns 1 TCHZ CE# High to High-Z Output 20 30 ns 1 TOHZ OE# High to High-Z Output 20 30 ns 1 TOH Output Hold from Address Change 0 0 ns 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Min 70
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AC39VF088
Table 10: Program/Erase Cycle Timing Parameter
Symbol TBP TAS TAH TCS TCH TOES TOEH TCP TWP TWPH1 1 TCPH TDS 1 TDH TIDA1 TSE TBE TSCE Parameter Byte-Program Time Address Setup Time Address Hold Time WE# and CE# Setup Time WE# and CE# Hold Time OE# High Setup Time OE# High Hold Time CE# Pulse Width WE# Pulse Width WE# Pulse Width High CE# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time Sector Erase Block Erase Chip Erase Min 0 30 0 0 0 10 45 45 30 30 45 0 150 30 30 60 Max 24 Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
This preliminary data sheet contains product specifications which are subject to change without notice.
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AC39VF088
T RC A19~A0 T CE CE# T AA
T OE OE# TOHZ
T OLZ
V IH WE#
T CLZ
T OH Data Valid
TCHZ HIGH-Z Data Valid
HIGH-Z DQ7-0
Figure 1. Read Cycle Timing Diagram
Internal Program Operation Starts TB P A19~A0 AAA T AH TW WE# T WPH TAS OE# TDS
P
555
AAA
ADDR TDH
TCH CE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA Byte (ADDR/DATA) X c a n b e V IL or V I H , b u t n o o t h e r v a l u e .
Figure 2. WE# Controlled Program Cycle Timing Diagr am
This preliminary data sheet contains product specifications which are subject to change without notice.
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AC39VF088
Internal Program Operation Starts TBP A19~A0 AAA T AH T CP CE# T CPH T AS OE# T DS 555 AAA ADDR T DH
TCH WE#
TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA Byte (ADDR/DATA)
X c a n b e V IL o r V I H , b u t n o o t h e r v a l u e .
Figure 3. CE# Controlled Program Cycle Timing Diagram
A19~A0 TCE CE# TOEH OE# TOE WE# TOES
DQ7
DATA
DATA#
DATA#
DATA#
Figure 4. Data# Polling Timing Diagram
This preliminary data sheet contains product specifications which are subject to change without notice.
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AC39VF088
A19~A0 T CE CE# TOEH OE# T OE TOES
WE#
DQ6 Two Read Cycles With Same Outputs
Figure 5. Toggle Bit Timing Diagram
Six-Byte Code For Chip-Erase
TSCE AAA
A19~A0
AAA
555
AAA
AAA
555
CE#
OE# TW P WE#
DQ7-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
10 SW5
Note: This device also supports CE# controlled Chip-Erase operation. The WE#and CE# signals are interchageable as long as minimum timings are met. (See Table 14) X c a n b e V IL o r V I H , b u t n o o t h e r v a l u e .
Figure 6. WE# Controlled Chip-Erase Timing Diagram
This preliminary data sheet contains product specifications which are subject to change without notice.
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AC39VF088
Six-Byte Code For Block-Erase
T BE BAX
A19~A0
AAA
555
AAA
AAA
555
CE#
OE# TWP WE#
DQ7-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
50 SW5
Note: This device also supports CE# controlled Block-Erase operation. The WE#and CE# signals are interchageable as long as minimum timings are met. (See Table 14) B A X=Block Address X c a n b e V IL o r V I H , b u t n o o t h e r v a l u e .
Figure 7. WE# Controlled Block-Erase Timing Diagram
Six-Byte Code For Sector-Erase
TSE SAX
A19~A0
AAA
555
AAA
AAA
555
CE#
OE# TWP WE#
DQ7-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
30 SW5
Note: This device also supports CE# controlled Sector-Erase operation. The WE#and CE# signals are interchageable as long as minimum timings are met. (See Table 14) S A X= S e c t o r A d d r e s s X c a n b e V IL o r V I H , b u t n o o t h e r v a l u e .
Figure 8. WE# Controlled Sector-Erase Timing Diagram
This preliminary data sheet contains product specifications which are subject to change without notice.
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AC39VF088
Three-Byte Sequence For Software ID Entry
Address A14-0
AAA
555
AAA
0000H 0003H 0040H 0001H
CE#
OE# TWP WE# T WPH DQ7-0 AA SW0 Device ID=21H X c a n b e V IL o r V I H , b u t n o o t h e r v a l u e . 1=7FH, 2=7FH, 3=1FH 55 SW1 90 SW2 TAA 1 2 3
21H
T IDA
Figure 9. Software ID Entry and Read
VIHT Input VILT AC test inputs are driven at V IHT (0.9 VDD) for a logic "1" and VILT(0.1 V DD) for a logic "0". Measurement reference points for inputs and outpputs are V IT(0.5 V DD) and VOT(0.5 V DD). Input rise and fall times(10% - 90% ) are <5ns VIT Reference Points VOT Output
Note: V IT = Vinput Test VOT = Voutput Test VIHT = Vinput HIGH Test VILT = Vinput LOW Test
Figure 10. AC Input/Output Reference Waveforms
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AC39VF088
TO TESTER
TO DUT CL
Figure 11. A Test Load Example
This preliminary data sheet contains product specifications which are subject to change without notice.
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AC39VF088
Start
Load Data: AAH Address: AAAH
Load Data: 55H Address: 555H
Load Data: A0H Address: AAAH
Load Word Address/Word Data
Wait for end of Program (T B P , D a t a # P o l l i n g b i t , o r Toggle bit operation)
Program Completed
Figure 12. Byte-Program Algorithm
This preliminary data sheet contains product specifications which are subject to change without notice.
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AC39VF088
Internal Timer Progrm/Erase Initiated Toggle Bit Progrm/Erase Initiated Data# Polling Progrm/Erase Initiated
Wait TBP , TSCE , TSE or TBE
Read Word
Read DQ7
Progrm/Erase Completed
Read Same Word
Is DQ7=true data? Yes
No
Does DQ6 match? Yes Progrm/Erase Completed
No
Progrm/Erase Completed
Figure 13. Wait Options
This preliminary data sheet contains product specifications which are subject to change without notice.
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AC39VF088
Software ID Entry Command Sequence Load Data: AAH Address: AAAH Software ID Exit Command Sequence Load Data: F0H Address: XXH
Load Data: 55H Address: 555H
Wait T I D A
Load Data: 90H Address: AAAH
Return to Normal Operation
Wait TI D A
Read Software ID
Figure 14. Software ID Command Flowcharts
This preliminary data sheet contains product specifications which are subject to change without notice.
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AC39VF088
Chip-Erase Command Sequence Sector-Erase Command Sequence Block-Erase Command Sequence
Load Data: AAH Address: AAAH
Load Data: AAH Address: AAAH
Load Data: AAH Address: AAAH
Load Data: 55H Address: 555H
Load Data:55H Address: 555H
Load Data: 55H Address: 555H
Load Data: 80H Address: AAAH
Load Data:80H Address: AAAH
Load Data: 80H Address: AAAH
Load Data: AAH Address: AAAH
Load Data: AAH Address: AAAH
Load Data: AAH Address: AAAH
Load Data: 55H Address: 555H
Load Data: 55H Address: 555H
Load Data: 55H Address: 555H
Load Data: 10H Address: AAAH
Load Data: 50H Address: SA
X
Load Data: 30H Address: BA
X
Wait T
SCE
Wait T
SE
Wait T
BE
Chip Erased to FFH
Sector Erased to FFH
Block Erased to FFH
Figure 15. Erase Command Sequence
This preliminary data sheet contains product specifications which are subject to change without notice.
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