View AD5379_973723.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY TECHNICAL DATA
a
40-Channel, 14-Bit, Parallel and Serial Input, Voltage-Output DAC Preliminary Technical Data AD5379
FEATURES 40-Channel DAC in 13 x 13 mm 2 108-lead CSPBGA System Calibration Function allowing User Programmable Offset and Gain Buffered Voltage Outputs Output Voltage Span of 3.5VREF(+) Maximum Output Voltage Span of 17.5V Clear Function to User-defined REFGND (CLR Pin) CLR LDAC Simultaneous Update of DAC Outputs (LDAC Pin) DAC Increment/Decrement Mode Parallel Interface DSP-/Microcontroller-compatible 3-wire Serial Interface SDO Daisy-Chaining Option Power-On-Reset Digital Reset (RESET pin and Soft-Reset function) RESET APPLICATIONS Automatic Test Equipment Optical Networks Industrial Control Systems
VCC VDD VSS AGND
GENERAL DESCRIPTION
The AD5379 contains forty 14-bit DACs in one package. It has a maximum output voltage span of 17.5V which corresponds to an output range of -8.75 V to +8.75 V derived from reference voltages of -3.5 V and +5 V. The AD5379 has a parallel interface in which 14 data-bits are loaded into one of the input registers under the control of the WR, CS and DAC channel address pins, A0-A7. It also has a 3wire serial interface which is compatible with SPITM, QSPITM, MICROWIRETM and DSP interface standards. The DAC outputs are updated on reception of new data into the DAC registers. All the outputs can be updated simultaneously by taking the LDAC input low. Each channel has a programmable gain and offset adjust register. Each DAC output is gained and buffered on-chip with respect to an external REFGND input. The DAC outputs can also be switched to REFGND via the CLR pin.
FUNCTIONAL BLOCK DIAGRAM
DGND LDAC VBIAS VREF1(+) VREF1(-) REFGND A1 CLR
POWER-ON RESET
RESET DCEN/WR SYNC/CS REG0 REG1 DB13 SCLK/DB12 DIN/DB11 DB0 A7 A0 SER/PAR DIN SCLK SDO FIFOEN REFGND B1 REFGND B2 REFGND C1 REFGND C2 REFGND D1 REFGND D2 BUSY
AD5379
14
INPUT REG 0..1
VBIAS
14
X
+
14
I 14 NF TI EF RO 14 INPUT REG F 2 A . C M .14 ESA . TC . 14 AH . TI 14 INPUT REG EN 7 E
14
DAC 14 REG 0..1
+
DAC 0..1
+
VOUT 0 VOUT 1
m REG0..1 c REG0..1
14
14
X
+
DAC 14 REG 2
DAC 2 . . . DAC 7
+
VOUT 2 VOUT 3 VOUT 4 VOUT 5 VOUT 6 VOUT 7
m REG2 c REG2
. . 14 . .X .
m REG7 c REG7
. . . . + .
14
. . . . .
DAC 14 REG 7
. . . . .
+
14
INPUT REG 8..9
14
14
X
+
m REG8..9
14
c REG8..9
X4
DAC 14 DAC 8..9 REG 8..9
+ +
VOUT 8 VOUT 9 VOUT 10
VOUT 39 VREF2(+) VREF2(-) REFGND A2
*Protected by U.S. Patent Nos. 5,969,657; other patents pending. SPI and QSPI are Trademarks of Motorola, Inc. MICROWIRE is a Trademark of National Semiconductor Corporation. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REV. PrQ 08/02
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
(V V; V V ; (+) V; -3.5 AD5379-SPECIFICATIONS AGND==2.7 V to=5.5REFGND==120 V;V 5%;=V5 V;=C-12=V2005% toVGND; R==5 11 Vk(-) = V; V; DGND pF to 3
CC DD SS REF REF BIAS L L
Gain = 1; Offset = 0 V; All specifications TMIN to TMAX unless otherwise noted.)
Parameter
ACCURACY Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Error Gain Error Gain Temperature Coefficient2 DC Crosstalk2 REFERENCE INPUTS VREF(+) DC Input Impedance VREF(-) DC Input Impedance VREF(+) Input Current VREF(+) Range VREF(-) Range REFGND INPUTS2 DC Input Impedance Input Range OUTPUT CHARACTERISTICS2 Output Voltage Range Short Circuit Current Load Current Capacitive Load DC Output Impedance DIGITAL INPUTS2 Input High Voltage Input Low Voltage Input Current Input Capacitance DIGITAL OUTPUTS (BUSY, SDO)2 Output Low Voltage Output High Voltage (SDO) Output High Voltage (BUSY) High Impedance Leakage Current High Impedance Output Capacitance POWER REQUIREMENTS VCC VDD VSS Power Supply Sensitivity2 Full Scale/VDD Full Scale/VSS ICC IDD ISS Power Dissipation(outputs unloaded)3 Power Dissipation(outputs loaded)3,4,5
2
A Version1
Units
Test Conditions/Comments
14 4 -1/+2 10 10 TBD 20 0.5 1 8 10 1.5/5 -3.5/0 80 0.5 VSS + 2.5 VDD - 2.5 15 1.5 200 TBD 2.0 0.8 30 10 0.5 VCC - 0.5 VCC + 0.3 10 10 2.7/5.5 8.5/16.5 -3/-16.5 -65 -65 5 40 40 1.03 TBD
Bits LSB max LSB max mV max mV max mV max ppm FSR/C typ mV max M min k min A max V min/max V min/max k min V min/max V min V max mA max mA max pF max max V min V max A max pF max V max V min V max A max pF typ V min/max V min/max V min/max dB typ dB typ mA max mA max mA max W max W max
Guaranteed Monotonic Over Temperature. Typically 5 mV Typically TBD mV Typically 100 M Typically 12 k Per Input. Typically 30 nA
Typically 120 k
ILOAD = 1.5 mA ILOAD = 1.5 mA
VCC = 2.7 V to 5.5 V Total for All Pins. Input Current per pin < 5A max.
Sinking 200 A Sourcing 200 A Open-drain output. BUSY has an internal clamp diode to Vcc SDO Only
VCC = 5.5V. VIH = VCC, VIL = GND. VDD = 12.6V. Outputs Unloaded. Typically 14.5 mA VSS = -12.6V. Outputs Unloaded. Typically 10.5 mA P = (VDD x IDD) + (VSS x ISS) + (VCC x ICC ) PTOTAL = P + [(VDD - VO) x ISOURCE] + [(VO - VSS) x ISINK]
NOTES 1 Temperature range for A Version: -40C to +85C 2 Guaranteed by characterization. Not production tested. 3 VDD = 12.6 V, VSS = -12.6 V, VCC = 5.5 V. 4 This includes the power dissipation due to the additional current in the 40 output buffers when driving external loads. It does not include the power dissipated in the external loads. 5 Ensure you do not exceed T J (max) Specifications subject to change without notice.
-2-
REV. PrQ
PRELIMINARY TECHNICAL DATA AD5379
5.5 V; V V = 5 (+) = (-) V; AC CHARACTERISTICS1 (V ==2.7 V to= REFGND==12 V; 5%;=V5 V; C-12 V50 pF;%; V= 11 k 5 V;3 VV; Gain==-3.5Offset = 0 V;) AGND DGND 0V = R 1; to
CC DD SS REF REF BIAS L L
Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time
A
Units s typ s max V/s typ nV-s typ mV max dB typ nV-s typ nV-s typ nV-s typ nV/(Hz)1/2 typ
Test Conditions/Comments Full-Scale Change to 1/2 LSB. DAC Latch Contents Alternately Loaded with All 0s and All 1s
TBD TBD Slew Rate 1 Digital-to-Analog Glitch Energy 50 Glitch Impulse Peak Amplitude 15 Channel-to-Channel Isolation 100 DAC-to-DAC Crosstalk 40 Digital Crosstalk 2 Digital Feedthrough 1 Output Noise Spectral Density @ 1 kHz 200
See Terminology See Terminology Effect of Input Bus Activity on DAC Output Under Test All 1s Loaded to DAC. VREF(+) = VREF(-) = 0 V
1 Guaranteed by design and characterization, not production tested. Specifications subject to change without notice.
TIMING CHARACTERISTICS
SERIAL INTERFACE
(VCC = 2.7 V to 5.5 V; VDD = 12 V 5%; VSS = -12 V 5 %; VREF(+) = 5 V; VREF(-) = -3.5 V; AGND = DGND = REFGND = 0 V; VBIAS = 5 V; All specifications TMIN to TMAX unless otherwise noted.) Units ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns typ ns min ns min ns max ns min
ns min
Parameter1,2,3 t1 t2 t3 t4 t 54 t 64 t7 t8 t9 t104,5 t11 t124 t13 t14 t15
t16
Limit at TMIN, TMAX 33 13 13 13 13 33 10 5 4.5 30 900 20 20 100 0
100
Description SCLK Cycle Time SCLK High Time SCLK Low Time SYNC Falling Edge to SCLK Falling Edge Setup Time 24th SCLK Falling Edge to SYNC Falling Edge Minimum SYNC Low Time Minimum SYNC High Time Data Setup Time Data Hold Time 24th SCLK Falling Edge to BUSY Falling Edge BUSY Pulse Width Low (Single Channel Update) 24th SCLK Falling Edge to LDAC Falling Edge LDAC Pulse Width Low BUSY Rising Edge to DAC Output Response Time BUSY Rising Edge to LDAC Falling Edge LDAC Falling Edge to DAC Output Response Time DAC Output Settling Time CLR Pulse Width Low CLR Pulse Activation Time SCLK Rising Edge to SDO Valid SCLK Falling Edge to SYNC Rising Edge SYNC Rising Edge to SCLK Rising Edge SYNC Rising Edge to LDAC Falling Edge
t17 t18 t19 t206,7 t217 t227 t237
30 20 300 20 5 8 20
s typ ns min ns max ns max ns min ns min ns min
NOTES 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V. 3 See Figures 3 and 4 4 Stand-Alone Mode only. 5 This is measured with the load circuit of Figure 1a. 6 This is measured with the load circuit of Figure 1b. 7 Daisy-Chain Mode only. Specifications subject to change without notice.
VCC
RL 2.2k
200A TO OUTPUT PIN
IOL
TO OUTPUT PIN
CL 50pF
VOL
CL 50pF 200A IOH
VOH(min) + VOL(max) 2
Figure 1a Load Circuit for BUSY Timing Diagram
Figure 1b Load Circuit for SDO Timing Diagram (Serial Interface, Daisy-Chain mode)
REV. PrQ
-3-
PRELIMINARY TECHNICAL DATA AD5379 TIMING CHARACTERISTICS
PARALLEL INTERFACE
(VCC = 2.7 V to 3.6 V; VDD = 12 V 5 %; VSS = -12 V 5%; AGND = DGND = DUTGND = 0 V; VREF(+) = 5 V; VREF(-) = -3.5 V; All specifications TMIN to TMAX unless otherwise noted.)
Units ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns max ns min ns min ns max ns min ns min ns min
s typ
Parameter1,2,3 t0 t1 t2 t3 t4 t5 t6 t7 t8 t 94 t104 t114,5 t124 t13 t144 t15 t16 t174 t18 t19 t20
Limit at TMIN, TMAX 4.5 4.5 20 20 0 0 4.5 4.5 20 430 30 400 30 20 100 20 0 100 30 20 300
Description REG0, REG1, Address to WR Rising Edge Setup Time REG0, REG1, Address to WR Rising Edge Hold Time CS Pulse Width Low WR Pulse Width Low CS to WR Falling Edge Setup Time WR to CS Rising Edge Hold Time Data to WR Rising Edge Setup Time Data to WR Rising Edge Hold Time WR Pulse Width High Minimum WR Cycle Time (Single Channel Write) WR Rising Edge to BUSY Falling Edge BUSY Pulse Width Low (Single Channel Update) WR Rising Edge to LDAC Falling Edge LDAC Pulse Width Low BUSY Rising Edge to DAC Output Response Time LDAC Rising Edge to WR Rising Edge BUSY Rising Edge to LDAC Falling Edge LDAC Falling Edge to DAC Output Response Time DAC Output Settling Time CLR Pulse Width Low CLR Pulse Activation Time
ns min ns max
NOTES 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with t r = tf = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V. 3 See Timing Diagram in Figure 2. 4 See Table III. 5 This is measured with the load circuit of Figure 1a. Specifications subject to change without notice. t0 t1
REG0, REG1, A7..A0 t4 CS WR t2 t3 t6 DB12..DB0 t10 BUSY t12 LDAC1 VOUT1 LDAC2 VOUT2 t19 CLR t20 VOUT
1 LDAC ACTIVE DURING BUSY 2 LDAC ACTIVE AFTER BUSY
t5 t9 t8 t7 t15
t11 t13 t14 t18 t16 t13
t17 t18
Figure 2. Parallel Interface Timing Diagram -4-
REV. PrQ
PRELIMINARY TECHNICAL DATA AD5379
t1 SCLK 1 t4 SYNC t7 t8 DIN D23 t6 t9 D0 t10 BUSY t12 LDAC1 VOUT 1 t14 t17 t15 LDAC2 VOUT2 t18 CLR t19 V OUT
1 LDAC ACTIVE DURING BUSY 2 LDAC ACTIVE AFTER BUSY
2 t3 t2
24 t5
24
t11 t13
t13
t16 t17
Figure 3. Serial Interface Timing Diagram (Stand-Alone mode)
t1 t1 SCLK t7 t4 SYNC t8 t9 DIN D23 Input Word for DAC N SDO UNDEFINED LDAC
Figure 4. Serial Interface Timing Diagram (Daisy-Chain mode)
24 t3 t2 t21
48 t22
D0
D23' Input Word for DAC N+1 t20 D23 Input Word for DAC N
D0'
D0 t23 t13
-5- REV. PrQ
PRELIMINARY TECHNICAL DATA AD5379
ABSOLUTE MAXIMUM RATINGS1,2
(TA = +25C unless otherwise noted)
VDD to AGND................................................-0.3 V to +17 V VSS to AGND.................................................+0.3 V to -17 V VCC to DGND.................................................-0.3 V to +7 V Digital Inputs to DGND.........................-0.3 V to VCC + 0.3 V Digital Outputs to DGND......................-0.3 V to VCC + 0.3 V VREF1(+), VREF2(+) to AGND..........................-0.3 V to +7 V VREF1(+), VREF2(+) to AGND..........................-0.3 V to +7 V VREF1(+) to VREF1(-)........................................-0.3 V to +7 V VREF2(+) to VREF2(-)........................................-0.3 V to +7 V VBIAS to AGND.............................................-0.3 V to +5.5 V VOUT0-39 to AGND......................VSS - 0.3 V to VDD + 0.3 V REFGND to AGND......................VSS - 0.3 V to VDD + 0.3 V AGND to DGND......................................... -0.3 V to +0.3 V
Operating Temperature Range (TA) Commercial (A Version)..................................0C to +70C Storage Temperature Range...........................-65C to +150C Junction Temperature (TJ max)...................................+150C 108-lead CSPBGA Package, JA Thermal Impedance............................................47C/W JA Thermal Impedance..............................................7C/W Max Power Dissipation3.......................(150C - TA)/JA mW Reflow Soldering Peak Temperature......................................................230C Time at Peak Temperature........................... 10 sec to 40 sec NOTES:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100mA will not cause SCR latch-up 3This limit includes additional power due to external loads
1
ORDERING GUIDE
Model AD5379ABC
Temperature Range -40C to +85C
Linearity Error (LSBs)
4
Package Description 108-lead CSPBGA
Package Option BC-108
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5379 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
-6-
REV. PrQ
PRELIMINARY TECHNICAL DATA AD5379
PIN CONFIGURATION
1 2 3 4 5 6 7 8 9 10 11 12
A B C D E F G H J K L M
1 2 3 4 5
TOP VIEW
A B C D E F G H J K L M
8 9 10 11 12
6
7
108-Lead CSPBGA Ball Configuration
CSPBGA Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12
1 2
Ball Name REG0 VCC3 DB10 AGND4 VBIAS VOUT5 AGND3 REFGNDA1 VDD5 VSS5 VSS4 VDD4 REG1 DGND4 DB9 CLR VOUT7 VOUT6 VOUT0 VOUT1 VOUT2 VOUT31 REFGNDD1 VOUT30 DB13 DB12/SCLK DB11/DIN SER/PAR LDAC VOUT8 VOUT3 VOUT4 VOUT9 VOUT34 VOUT32 VOUT33
CSPBGA Number D1 D2 D3 D10 D11 D12 E1 E2 E3 E10 E11 E12 F1 F2 F3 F10 F11 F12 G1 G2 G3 G10 G11 G12 H1 H2 H3 H10 H11 H12 J1 J2 J3 J10 J11 J12
Ball Name DB7 DB8 DGND1 VREF1(-) VOUT35 VOUT36 DB5 DB6 VCC1 REFGNDB2 VOUT37 VOUT38 DB4 DB32 DB22 VDD3 REFGNDD2 VOUT39 DB12 DB02 BUSY VSS3 VOUT29 REFGNDC2 WR/DCEN2 SDO CS/SYNC VOUT28 VOUT26 VOUT27 A0 A1 A2 VOUT19 VOUT24 VOUT25
CSPBGA Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12
Ball Name A4 A5 A3 DGND2 REFGNDA2 VREF2(-) VOUT12 VOUT13 VOUT16 VOUT18 VOUT22 VOUT23 A7 A6 N/C1, 3 RESET4 VOUT17 AGND2 VOUT14 VOUT10 VDD1 VREF2(+) VOUT20 VOUT21 DGND3 VCC2 FIFOEN 2 AGND1 VOUT15 VOUT11 REFGNDB1 VREF1(+) VSS1 VSS2 VDD2 REFGNDC1
N/C should be left unconnected Internal 1M pull-down device on these logic inputs. Therefore they can be left floating and will default to a logic low condition. 3 Internal active pull-up device on these logic inputs. Therefore they can be left floating and will default to a logic high condition. 4 Internal 1M pull-up device on these logic inputs. Therefore they can be left floating and will default to a logic high condition.
-7- REV. PrQ
PRELIMINARY TECHNICAL DATA AD5379
PIN FUNCTION DESCRIPTION
Pin VCC(1-3) VSS(1-5) VDD(1-5) AGND(1-4) DGND(1-4) VREF1(+), VREF1(-) VREF2(+), VREF2(-) VBIAS
Function
Logic Power Supply; 2.7 V to 5.5 V. Negative Analog Power Supply; -12 V 5%. Positive Analog Power Supply; +12 V 5%. Ground for all analog circuitry. Ground for all digital circuitry. Reference Inputs for DACs 0 to 7, 10 to 17, 20 to 27 and 30 to 37. These voltages are referred to AGND. Reference Inputs for DACs 8, 9, 18, 19, 28, 29, 38 and 39. These reference voltages are referred to AGND. DAC Bias Voltage Input/Output. If VREF(+) > 4.25 V, VBIAS must be pulled high externally to an equal or higher potential (e.g. 5 V). If VREF(+) < 4.25 V, the on-chip bias generator can be used. In this case the VBIAS pin should be decoupled with a 10 nF capacitor to AGND. VOUT0 ...VOUT39 DAC Outputs. SER/PAR Interface Select Input. This pin allows the user to select whether the serial or parallel interface will be used. If it is tied high the serial interface will be used. SYNC1 Active Low Input. This is the Frame Synchronisation signal for the serial interface. SCLK1 Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds up to 30 MHz. Serial Data Input. Data must be valid on the falling edge of SCLK. DIN1 SDO1 Serial Data Output. CMOS output. SDO can be used for daisy-chaining a number of devices together. Data is clocked out on SDO on the rising edge of SCLK and is valid on the falling edge of SCLK. 1 DCEN Daisy-Chain Select Input (level sensitive, active high). When high this signal is used in conjunction with SER/ PAR high to enable serial interface daisy-chain mode. CS Parallel Interface Chip Select Input (level sensitive, active low). If it is low the device is selected. WR Parallel Interface Write Input (edge sensitive). The rising edge of WR is used in conjunction with CS low and the address bus inputs to write to the selected AD5379 registers. DB13...DB0 Parallel Data Inputs. The AD5379 can accept a straight 14-bit parallel word on DB0 to DB13 where DB13 is the MSB and DB0 is the LSB. A0...A7 Parallel Address Inputs. A7 to A4 are decoded to select one group or multiple groups of registers for a data transfer. A3 to A0 are decoded to select one of ten input registers, gain registers (m) or offset registers (c). See Page 13 for details of the address decoding. REG0 Parallel Interface Register Select Input. This pin is used together with REG1 to select data registers, gain registers, offset registers, Increment/Decrement mode or Soft-Reset. See Table II. REG1 Parallel Interface Register Select Input. This pin is used together with REG0 to select data registers, gain registers, offset registers, Increment/Decrement mode or Soft-Reset. See Table II. CLR Asynchronous Clear Input (level sensitive, active low). When CLR is low, the input to each of the DAC output buffer stages, VOUT0 to VOUT39, is switched to the externally set potential on the relevant REFGND pin. While CLR is low all LDAC pulses are ignored. When CLR is taken high again, the DAC outputs remain cleared until LDAC is taken low. The contents of input registers and DAC registers 0 to 39 are not affected by taking CLR low. BUSY Digital Input/Open-Drain Output. BUSY goes low during internal calculations of x2. During this time the user can continue writing new data to further x1, c and m registers (these are stored in a FIFO) but no further updates to the DAC registers and DAC outputs can take place. If LDAC is taken low while BUSY is low this event is stored. Since BUSY is bidirectional, it can be pulled low externally in order to delay LDAC action. BUSY also goes low during power-on-reset or when the RESET pin is low. During this time the parallel interface is disabled and any events on LDAC are ignored. LDAC Load DAC Logic Input (active low). If LDAC is taken low while BUSY is inactive (high) the contents of the input registers are transferred to the DAC registers and the DAC outputs are updated. If LDAC is taken low while BUSY is active and internal calculations are taking place, the LDAC event is stored and the DAC registers are updated when BUSY goes inactive. However any events on LDAC during power-on-reset or RESET are ignored. RESET Asynchronous Digital Reset Input (level sensitive, active low). The function of this pin is equivalent to that of the Power-On-Reset generator. When this pin is taken low, the AD5379 state-machine initiates a reset sequence to digitally reset x1, m, c, and x2 registers to their default power-on values. This sequence takes 10 ms (typ). Furthermore the input to each of the DAC output buffer stages, VOUT0 to VOUT39, is switched to the externally set potential on the relevant REFGND pin. While RESET is low BUSY goes low and the parallel interface is disabled. All LDAC pulses are ignored until BUSY goes high. When RESET is taken high again, the DAC outputs remain at REFGND until LDAC is taken low.
1
These serial interface signals do not require separate pins but share parallel interface pins.
-8-
REV. PrQ
PRELIMINARY TECHNICAL DATA AD5379
PIN FUNCTION DESCRIPTION (CONTINUED)
Pin VCC(1-3) REFGNDA1 REFGNDA2 REFGNDB1 REFGNDB2 REFGNDC1 REFGNDC2 REFGNDD1 REFGNDD2
Function Logic Power Supply; 2.7 V to 3.6 V. Device Sense Ground for DACs 0 to 7. VOUT0 to VOUT7 are referenced to this voltage. Device Sense Ground for DACs 8 and 9. VOUT8 and VOUT9 are referenced to this voltage. Device Sense Ground for DACs 10 to 17. VOUT10 to VOUT17 are referenced to this voltage. Device Sense Ground for DACs 18 and 19. VOUT18 and VOUT19 are referenced to this voltage. Device Sense Ground for DACs 20 to 27. VOUT20 to VOUT27 are referenced to this voltage. Device Sense Ground for DACs 28 and 29. VOUT28 and VOUT29 are referenced to this voltage. Device Sense Ground for DACs 30 to 37. VOUT30 to VOUT37 are referenced to this voltage. Device Sense Ground for DACs 38 and 39. VOUT38 and VOUT39 are referenced to this voltage.
TERMINOLOGY Relative Accuracy
Relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error and is expressed in Least Significant Bits.
Differential Nonlinearity
The forty DAC outputs are buffered by op amps that share common VDD and VSS power supplies. If the dc load current changes in one channel (due to an update), this can result in a further dc change in one or other channel outputs. This effect is most obvious at high load currents and reduces as the load currents are reduced. With high impedance loads the effect is virtually unmeasurable.
Output Voltage Settling Time
Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity.
Zero-Scale Error
This is the amount of time it takes for the output of a DAC to settle to a specified level for a full-scale input change.
Digital-to-Analog Glitch Energy
Zero-scale error is the error in the DAC output voltage when all 0s are loaded into the DAC register. Ideally, with all 0s loaded to the DAC and m = all 1s, c = 0: VOUT(Zero-Scale) = 2.5 x (VREF(-) - AGND) + REFGND Zero-scale error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV. It is mainly due to offsets in the output amplifier.
Full-Scale Error
This is the amount of energy injected into the analog output at the major code transition. It is specified as the area of the glitch in nV-s. It is measured by toggling the DAC register data between 1FFFHex and 2000Hex.
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input signal from one DACs reference input that appears at the output of another DAC. It is expressed in dBs.
DAC-to-DAC Crosstalk
Full-scale error is the error in DAC output voltage when all 1s are loaded into the DAC register. Ideally, with all 1s loaded to the DAC and m = all 1s, c = 0: VOUT(Full-Scale) = 3.5 x (VREF(+) - AGND) + 2.5 x (VREF(-) - AGND) + REFGND Full-scale error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV. It does not include zero-scale error.
Gain Error
DAC-to-DAC crosstalk is defined as the glitch impulse that appears at the output of one converter due to both the digital change and subsequent analog O/P change at another converter. It is specified in nV-s.
Digital Crosstalk
The glitch impulse transferred to the output of one converter due to a change in the DAC register code of another converter is defined as the digital crosstalk and is specified in nV-s.
Digital Feedthrough
Gain Error is defined as the difference between Full-Scale Error and Zero-Scale Error. It is expressed in mV. Gain Error = Full-Scale Error - Zero-Scale Error
DC Output Impedance
This is the effective output source resistance. It is dominated by package lead resistance.
DC Crosstalk
When the device is not selected, high frequency logic activity on the device's digital inputs can be capacitively coupled both across and through the device to show up as noise on the VOUT pins. It can also be coupled along the supply and ground lines. This noise is digital feedthrough.
Output Noise Spectral Density
Although the common input reference voltage signals are internally buffered, small IR drops in the individual DAC reference inputs across the die can mean that an update to one channel can produce a dc output change in one or other of the channel outputs. REV. PrQ
This is a measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per root Hertz). It is measured by loading all DACs to midscale and measuring noise at the output. It is measured in nV/(Hz)1/2.
-9-
PRELIMINARY TECHNICAL DATA AD5379 Typical Performance Characteristics
TBD
TPC 1. Typical INL Plot
TBD
TPC 2. Typical DNL Plot
TBD
TPC 3. Typical INL Error vs. Temperature
TBD
TPC 4. Typical DNL Error vs. Temperature
TBD
TPC 5. Zero-Scale and Full-Scale Error vs. Temperature
TBD
TPC 6. ICC vs. Temperature
TBD
TPC 7. Major Code-Transition Digital-to-Analog Glitch Energy
TBD
TPC 8. Full-Scale Settling Time
TBD
TPC 9. IDD, ISS vs. Temperature
-10-
REV. PrQ
PRELIMINARY TECHNICAL DATA AD5379
FUNCTIONAL DESCRIPTION DAC Architecture -- General
The AD5379 contains 40 DAC channels and 40 output amplifiers in a single package. The architecture of a single DAC channel consists of a 14-bit resistor-string DAC followed by an output buffer amplifier. The resistor-string section is simply a string of resistors, each of value R, from VREF(+) to AGND. This type of architecture guarantees DAC monotonicity. The 14-bit binary digital code loaded to the DAC register determines at what node on the string the voltage is tapped off before being fed into the output amplifier. The output amplifier translates the output of the DAC to a wider range. The DAC output is gained up by a factor of 3.5 and offset by the voltage on the VREF(-) pin. See the section on Transfer Function.
Channel Groups
Figure 5 shows a single DAC channel and it's associated registers. The power-on values for the m and c registers are fullscale and zero respectively. The user can individually adjust the voltage range on each DAC channel by over-writing the poweron values of m and c. The AD5379 has digital overflow and underflow detection circuitry to clamp the DAC output at fullscale or zero-scale when the values chosen for x1, m and c result in x2 being out of range. The complete transfer function for the AD5379 can be represented as: VOUT = 3.5 x ((VREF(+) - AGND) x x2/214) + 2.5 x (VREF(-) - AGND) + REFGND x2 is the Dataword loaded to the resistor string DAC VREF(+) is the voltage at the positive reference pin VREF(-) is the voltage at the negative reference pin Figure 6 shows the output amplifier stage of a single channel. VDAC is the voltage output from the resistor-string DAC. The nominal range of VDAC is 1 LSB to full-scale.
VDAC
The 40 DAC channels on the AD5379 are arranged in 4 groups (A, B, C, D) of 10 channels. In each group there are 8 channels connected to VREF1(+) and VREF1(-) and the remaining 2 channels are connected to VREF2(+) and VREF2(-). Each group has 2 individual REFGND pins e.g. in Group A there are 8 channels connected to REFGNDA1 and the remaining 2 channels are connected to REFGNDA2. In addition to an input register (x1) and a DAC register (x2), each channel has a gain register (m) and an offset register (c). See Tables IX, X and XI. Table I shows the reference inputs and REFGND inputs, m and c registers for Group A. Groups B, C and D are similar.
Table I. Group A
+ VREF(-)
VOUT
R
R
2.5R
REFGND
2.5R
+
R
AGND
Channel Reference 0..7 8..9 VREF1(+), VREF1(-)
REFGND
m, c Registers
Figure 6. Output Amplifier Stage
VBIAS Function
REFGNDA1 m REG0..7 c REG0..7 m REG8..9 c REG8..9
VREF2(+), VREF2(-) REFGNDA2
The AD5379 has an on-chip voltage-generator which provides a bias voltage of 4.25 V (min). The VBIAS pin provides access to this voltage: For VREF(+) < 4.25 V the on-chip bias generator should be used and the VBIAS pin must be decoupled externally with a 10 nF capacitor. For VREF(+) > 4.25 V, VBIAS must be over-driven externally by an equal or higher voltage. The external voltage source should be capable of driving a 50 uA (typ) current sink load.
Reference Selection
Transfer Function
The digital input transfer function for each DAC can be represented as: x2 = [(m + 1 )/2 x x1] + c x2 is the Dataword loaded to the resistor string DAC (default is 10 0000 0000 0000) x1 is the 14-bit Dataword written to the DAC input register (default is 10 0000 0000 0000) m is the 13-bit Gain Coefficient (default is 1 1111 1111 1111) c is the 14-bit Offset Coefficient (default is 10 0000 0000 0000)
LDAC VREF(+)
13
DAC
x1 INPUT REG INPUT DATA m REG c REG x2
The voltages applied to VREF(+) and VREF(-) determine the output voltage range and span on VOUT0-VOUT39. If the offset and gain features are not used (m and c are left at their power-on values), the reference levels required can be calculated as follows: VREF(+)min = (VOUTmax - VOUTmin) / 3.5 VREF(-)max = (AGND + VOUTmin ) / 2.5 If the offset and gain features of the AD5379 are used, then the output range required is slightly different. The reference levels required can be calculated as follows: - Identify the nominal output range on VOUT. - Identify the maximum offset span and the maximum gain required on the full output signal range. - Calculate the new maximum output range on VOUT. - Choose the new "VOUTmax" and "VOUTmin" required, keeping the new VOUT limits centred on the nominal values and assuming REFGND is zero (or equal to AGND). Note that VDD and Vss must provide sufficient headroom. -11-
x2 REG
DAC REG
DAC
VDAC
Figure 5. Single DAC Channel
AGND
REV. PrQ
PRELIMINARY TECHNICAL DATA AD5379
- Calculate the values of VREF(+) and VREF(-) as follows: VREF(+)min = (VOUTmax - VOUTmin) / 3.5 VREF(-)max = (AGND + VOUTmin ) / 2.5
Reference Selection Example INTERFACES
The AD5379 contains both a parallel and a serial interface. The active interface is selected via the SER/PAR pin. The AD5379 uses an internal FIFO memory to allow high speed successive writes. The user can continue writing new data to the AD5379 while write instructions are being executed. The BUSY signal goes low while instructions in the FIFO are being executed. Up to 120 successive intructions can be written to the FIFO at maximum speed in parallel mode. When the FIFO is full any further writes to the AD5379 are ignored. To minimize both the power consumption of the device and on-chip digital noise, the active interface only powers up fully when the device is being written to, i.e. on the falling edge of WR or on the falling edge of SYNC.
Parallel Interface
Nominal output range = 10 V; (-2 V to 8 V) Offset Error = 100 mV; Gain Error = 3%; REFGND = AGND = 0 V; 1) Gain Error = 3%; => Maximum Positive Gain Error = + 3% => Output Range incl. gain error = 10 + 0.03 (10) = 10.3 V 2) Offset Error = 100 mV; => Maximum Offset Error Span = 2(100) mV = 0.2 V => Output Range incl. gain error and offset error = 10.3 + 0.2 = 10.5 V 3) VREF(+) and VREF(-) Calculation: Actual Output range = 10.5 V i.e. -2.25 V to 8.25 V (centred); => VREF(+) = (8.25 + 2.25) / 3.5 = 3 V VREF(-) = -2.25 / 2.5 = -0.9 V If the solution yields inconvenient reference levels, the user can adopt one of three approaches: (1) Use a resistor divider to divide down a convenient, higher reference level to the required level. (2) Select convenient reference levels above VREF(+)min or below VREF(-)max. Modify the gain and offset registers to downsize the references digitally. In this way, the user can use almost any convenient reference level, but may reduce performance by over-compaction of the transfer function. (3) Use a combination of these two approaches.
AD5379 Calibration
The SER/PAR pin must be tied low to enable the parallel interface and disable the serial interface. Figure 2 shows the timing diagram for a parallel write to the AD5379. The parallel interface is controlled by the following pins:
CS Pin Active low device select pin. WR Pin On the rising edge of WR , with CS low, the address values at pins A7-A0 are latched and data values at pins DB13-DB0 are loaded into the selected AD5379 input registers.
REG1, REG0 Pins
The REG1 and REG0 pins determine the destination register of the data being written to the AD5379. See Table II.
Table II. Register Selection
The user can perform a system-calibration by overwriting the default values in the m and c registers for any individual DAC channel as follows: - Calculate the nominal offset and gain coefficients for the new output range (see previous example) - Calculate the new m and c values for each channel based on the specified offset and gain errors.
Calibration Example
REG1 REG0 1 1 0 0
DB13-DB0 Pins
Register Selected Input Data Register (x1) Offset Register (c) Gain Register (m) Special Function Register
1 0 1 0
Nominal Offset Coefficient = 0 Nominal Gain Coefficient = 10/10.5 x 8191 = 0.95238 x 8191 = 7801 Example 1: Channel 0, Gain Error = +3%, Offset Error = +100 mV 1) Gain Error (+3%) Calibration: 7801 x 1.03 = 8035 => Load Code "1 1111 0110 0011" to m Register 0 2) Offset Error (+100 mV) Calibration: LSB size = 10.5 / 16384 = 641 V; Offset Coefficient for +100 mV offset = 100 / 0.64 = 156 LSBs => Load "10 0000 1001 1100" to c Register 0 Example 2: Channel 1, Gain Error = -3%, Offset Error = -100 mV 1) Gain Error (-3%) Calibration: 7801 x 0.97 = 7567 => Load Code "1 1110 1000 1111" to m Register 1 2) Offset Error (-100 mV) Calibration: LSB size = 10.5 / 16384 = 641 V; Offset Coefficient for -100 mV offset = -100 / 0.64 = -156 LSBs => Load "01 1111 0110 0100" to c Register 1
The AD5379 accepts a straight 14-bit parallel word on DB0DB13 where DB13 is the MSB and DB0 is the LSB. See Tables IV, V, VI, VII and VIII.
A7-A0 Pins
Each of the 40 DAC channels can be addressed individually. There are also several channel groupings which enable the user to simultaneously write the same data to multiple DAC channels. Address bits A7-A4 are decoded to select one group or multiple groups of registers. Address bits A3-A0 select one of ten input data registers (x1), offset registers (c) or gain registers (m). See Tables IX, X and XI.
MSB LSB
A7-A0
REG1
REG0
D13-D0
Group/Channel Select Bits
Register Select Bits
Register Data Bits
Figure 7. Serial Data Format
-12-
REV. PrQ
PRELIMINARY TECHNICAL DATA AD5379
Serial Interface ADDITIONAL FUNCTIONS Clear Function
The SER/PAR pin must be tied high to enable the serial interface and disable the parallel interface. The serial interface is controlled by five pins as follows: SYNC, SYNC DIN, SCLK - Standard 3-wire interface pins. DCEN - Selects Stand-Alone Mode or Daisy-Chain Mode. SDO - Data Out pin for Daisy-Chain Mode. Figures 3 and 4 show the timing diagram for a serial write to the AD5379 in both Stand-Alone and Daisy-Chain Mode. The 24-bit data word format for the serial interface in shown in Figure 7.
Stand-Alone Mode
The clear function on the AD5379 can be implemented by using analog or digital control. 1) Bringing the CLR line low switches the outputs, VOUT0VOUT39 to the externally set potential on the REFGND pin. This is achieved by switching in REFGND and re-configuring the output amplifier stages. The contents of the input registers and DAC registers are not affected by taking CLR low. When CLR is brought high, the DAC outputs remain cleared until LDAC is taken low. While CLR is low the value of LDAC is ignored. 2) Loading a clear code to the x1 registers also enables the user to set VOUT0 to VOUT39 to the REFGND level. The Default Clear Code corresponds to m at full-scale and c at mid-scale (i.e. x2 = x1). Default Clear Code = 214 x(-Output Offset) / (Output range) = 214 x 2.5 x (AGND - VREF(-)) / (3.5 x (VREF(+) - AGND)) The more general expression for the Clear Code is as follows: Clear code = (214)/(m+1) x (Default Clear Code - c )
BUSY and LDAC Functions
By connecting DCEN (Daisy-Chain Enable) pin low, StandAlone Mode is enabled. The serial interface works with both a continuous and a noncontinuous serial clock. The first falling edge of SYNC starts the write cycle and resets a counter that counts the number of serial clocks to ensure that the correct number of bits are shifted into the serial shift register. Any further edges on SYNC are ignored until 24 bits are shifted in. Once 24 bits have been shifted in, the SCLK is ignored. In order for another serial transfer to take place the counter must be reset by the falling edge of SYNC.
Daisy-Chain Mode
For systems which contain several DACs the SDO pin may be used to daisy-chain several devices together. This daisy-chain mode can be useful in system diagnostics and reducing the number of serial interface lines. By connecting DCEN (Daisy-Chain Enable) pin high, the Daisy-Chain Mode is enabled. The first falling edge of SYNC starts the write cycle. The SCLK is continuously applied to the input shift register when SYNC is low. If more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting this line to the DIN input on the next device in the chain, a multi-device interface is constructed. 24 clock pulses are required for each AD5379 in the system. Therefore, the total number of clock cycles must equal 24N where N is the total number of AD5379 devices in the chain. When the serial transfer to all devices is complete, SYNC should be taken high. This latches the input data in each device in the daisy-chain and prevents any further data being clocked into the input shift register. A continuous SCLK source may be used if it can be arranged that SYNC is held low for the correct number of clock cycles. Alternatively, a burst clock containing the exact number of clock cycles may be used and SYNC taken high some time later. When the transfer to all input registers is complete, a common LDAC signal updates all DAC registers and all analog outputs are updated simultaneously.
The value of x2 is calculated each time the user writes new data to the corresponding x1, c or m registers. During the calculation of x2 the BUSY output goes low. While BUSY is low the user can continue writing new data to the x1, m or c registers but no DAC output updates can take place. The DAC outputs are updated by taking the LDAC input low. If LDAC goes low while BUSY is active, the LDAC event is stored and the DAC outputs update immediately after BUSY goes high. A user may also hold the LDAC input permanently low. In this case the DAC outputs update immediately after BUSY goes high. The value of x2 for a single channel or group of channels is recalculated each time there is a write to any x1 register(s), c register(s) or m register(s). During the calculation of x2 BUSY goes low. The duration of this BUSY pulse depends on the no. of channels being updated e.g. if x1, c or m data is written to one DAC channel, BUSY goes low for 900 ns (max). However if data is written to two DAC channels, BUSY goes low for 1250 ns (max). Note there is 500 ns overhead due to FIFO access. See Table III. The AD5379 contains an extra feature whereby a DAC register is not updated unless it's x2 register has been written to since the last time LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the x2 registers. However the AD5379 will only update the DAC register if the x2 data has changed, thereby removing unnecessary digital crosstalk.
Table III. BUSY Pulsewidth
Action Loading x1 or c or m to 1 Channel Loading x1 or c or m to 2 Channels Loading x1 or c or m to 3 Channels Loading x1 or c or m to 4 Channels Loading x1 or c or m to all 40 Channels
BUSY Pulsewidth 900 1250 1600 1950 14550 ns (max) ns (max) ns (max) ns (max) ns (max)
-13- REV. PrQ
PRELIMINARY TECHNICAL DATA AD5379
BUSY Input Function DATA DECODING
Since the BUSY pin is bi-directional and open-drain, a second AD5379 or any other device (e.g. system controller), can pull BUSY low and therefore delay DAC update(s), if required. This is a means of holding off any LDAC action. This feature allows synchronous updates of multiple AD5379 devices in a system at maximum speed. As soon as the last device connected to the BUSY pin is ready, all DACs will update automatically. Tying the BUSY pin of multiple devices together enables synchronous updating of all DACs without the addition of extra hardware.
Power-On-Reset
The AD5379 contains a 14-bit data bus, DB13-DB0. Depending on the value of REG1 and REG0, this data is loaded into the addressed DAC input register(s), Offset (c) register(s), Gain (m) register(s) or the Special Function register.
Table IV. DAC Data format (REG1 = 1, REG0 = 1)
DB13 to DB0 11 1111 11 1111 10 0000 10 0000 01 1111 00 0000 00 0000 1111 1111 0000 0000 1111 0000 0000 1111 1110 0001 0000 1111 0001 0000
DAC Output (16383/16384)VREF(+) (16382/16384)VREF(+) (8193/16384)VREF(+) (8192/16384)VREF(+) (8191/16384)VREF(+) (1/16384)VREF(+) 0 V V V V V V V
The AD5379 contains a power-on-reset generator and statemachine. During power-on CLR becomes active (internally), the power-on state-machine resets all internal registers to their default values and BUSY goes low. This sequence takes 10 ms (typ). The outputs, VOUT0-VOUT39 are switched to the externally set potential on the REFGND pin. During power-on the parallel interface is disabled so it is not possible to write to the part. Any transitions on LDAC during the power-on period will be ignored in order to reject initial LDAC pin glitching. A rising edge on BUSY indicates that power-on is complete and that the parallel interface is enabled. All DACs remain in their power-on state until LDAC is used to update the DAC outputs as described above.
RESET Input Function
Table V. Offset Data format (REG1 = 1, REG0 = 0)
DB13 to DB0 11 11 10 10 01 00 00 1111 1111 0000 0000 1111 0000 0000 1111 1111 0000 0000 1111 0000 0000 1111 1110 0001 0000 1111 0001 0000
Offset +8191 +8190 +1 +0 -1 -8191 -8192 LSB LSB LSB LSB LSB LSB LSB
The AD5379 can be placed in it's power-on-reset state at any time by activating the RESET pin. The AD5379 state-machine initiates a reset sequence to digitally reset x1, m, c and x2 registers to their default power-on values. This sequence takes 10 ms (typ) and during this sequence BUSY goes low. While RESET is low any transitions on LDAC will be ignored. As with the CLR input, while RESET is low the DAC outputs are switched to REFGND. This reset function can also be implemented via the parallel interface by setting REG0 and REG1 pins low and writing all 1s to DB13-DB0 (see Table VIII for Soft-Reset).
Increment/Decrement Function
Table VI. Gain Data format (REG1 = 0, REG0 = 1)
DB13 to DB1 1 1 1 1 0 0 0 1111 1111 0000 0000 1111 0000 0000 1111 1111 0000 0000 1111 0000 0000 1111 1110 0001 0000 1111 0001 0000
Gain 8192/8192 8191/8192 4098/8192 4097/8192 4096/8192 2/8192 1/8192
The AD5379 has a Special Function Register which enables the user to increment or decrement the internal 13-Bit Input Register data (x1) in steps of 0 to 127 LSBs. The increment/ decrement mode is selected by setting both REG1 and REG0 pins (or bits) low. The address pins (or bits) A7-A0 are used to select a DAC channel or a group of channels. The amount by which the x1 is incremented/decremented is determined by bits/pins DB6-DB0 e.g. for a 1 LSB increment/ decrement DB6..DB0 = 0000001 while for a 7 LSB increment/ decrement, DB6...DB0 = 0000111. DB8 determines whether the Input Register data is incremented (DB8 = 1) or decremented (DB8 = 0). The maximum amount by which the user is allowed to increment or decrement the data is 127 LSBs i.e DB6...DB0 = 1111111. The 0 LSB step is included to facilitate software loops in the user's application. See Table VII.
Table VII. Special Function Data format (REG1 = 0, REG0 = 0)
DB13 to DB0 00000 00000 00000 00000 00000 00000 00000 10 10 10 X0 00 00 00 1111111 0000111 0000001 0000000 0000001 0000111 1111111
Increment/Dccrement step +127 +7 +1 0 -1 -7 -128 LSB LSB LSB LSB LSB LSB LSB
Table VIII. Soft-Reset (REG1 = 0, REG0 = 0)
DB12 to DB0 11 1111 1111 1111 -14-
DAC Output REFGND
REV. PrQ
PRELIMINARY TECHNICAL DATA AD5379
ADDRESS DECODING
The AD5379 contains an 8-bit address bus, A7-A0. This address bus allows each DAC input register (x1), each Offset A7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Group All 40 DACs Group 1 Group 2 Group 1, 2 Group 3 Group 1, 3 Group 2, 3 Group 1, 2, 3 Group 4 Group 1, 4 Group 2, 4 Group 1, 2, 4 Group 3, 4 Group 1, 3, 4 Group 2, 3, 4 Group 1, 2, 3, 4 Group All 40 DACs Group 1 Group 2 Group 1, 2 Group 3 Group 1, 3 Group 2, 3 Group 1, 2, 3 Group 4 Group 1, 4 Group 2, 4 Group 1, 2, 4 Group 3, 4 Group 1, 3, 4 Group 2, 3, 4 Group 1, 2, 3, 4 A3 0 0 0 0 0 0 0 0 1 1
(c) register and each Gain (m) register to be individually updated. Note when all 40 DAC channels are selected address bits A[3:0] are ignored. A2 0 0 0 0 1 1 1 1 0 0 A1 0 0 1 1 0 0 1 1 0 0 A0 0 1 0 1 0 1 0 1 0 1 DATA REGISTER Input Register 0 (with m, c, Registers 0) Input Register 1 (with m, c, Registers 1) Input Register 2 (with m, c, Registers 2) Input Register 3 (with m, c, Registers 3) Input Register 4 (with m, c, Registers 4) Input Register 5 (with m, c, Registers 5) Input Register 6 (with m, c, Registers 6) Input Register 7 (with m, c, Registers 7) Input Register 8 (with m, c, Registers 8) Input Register 9 (with m, c, Registers 9)
Table IX. DAC Input Register (x1) Selection (REG1 = REG0 = 1)
Table X. DAC Offset Register (c) Selection (REG1 = 1, REG0 = 0)
A3 0 0 0 0 0 0 0 0 1 1
A2 0 0 0 0 1 1 1 1 0 0
A1 0 0 1 1 0 0 1 1 0 0
A0 0 1 0 1 0 1 0 1 0 1
OFFSET REGISTER Offset Register 0 Offset Register 1 Offset Register 2 Offset Register 3 Offset Register 4 Offset Register 5 Offset Register 6 Offset Register 7 Offset Register 8 Offset Register 9
Table XI. DAC Gain Register (m) Selection (REG1 = 0, REG0 = 1)
A7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Group All 40 DACs Group 1 Group 2 Group 1, 2 Group 3 Group 1, 3 Group 2, 3 Group 1, 2, 3 Group 4 Group 1, 4 Group 2, 4 Group 1, 2, 4 Group 3, 4 Group 1, 3, 4 Group 2, 3, 4 Group 1, 2, 3, 4
A3 0 0 0 0 0 0 0 0 1 1
A2 0 0 0 0 1 1 1 1 0 0
A1 0 0 1 1 0 0 1 1 0 0
A0 0 1 0 1 0 1 0 1 0 1
GAIN REGISTER Gain Register 0 Gain Register 1 Gain Register 2 Gain Register 3 Gain Register 4 Gain Register 5 Gain Register 6 Gain Register 7 Gain Register 8 Gain Register 9
-15- REV. PrQ
PRELIMINARY TECHNICAL DATA AD5379
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5379 is mounted should be designed so that the analog and digital sections are separated, and confined to certain areas of the board. If the AD5379 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. For supplies with multiple pins (VSS, VDD, VCC) it is recommended to tie these pins together and to decouple each supply once. The AD5379 should have ample supply decoupling of 10 F in parallel with 0.1 F on each supply located as close to the package as possible, ideally right up against the device. The 10 F capacitors are the tantalum bead type. The 0.1 F capacitor should have low Effective Series Resistance (ESR) and Effective Series Inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Digital lines running under the device should be avoided as these will couple noise onto the device. The analog ground plane should be allowed to run under the AD5379 to avoid noise coupling. The power supply lines of the AD5379 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching digital signals should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. It is essential to minimize noise on all VREF(+) and VREF(-) lines. The VBIAS pin should be decoupled with a 10 nF capacitor to AGND. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. As is the case for all thin packages, care must be taken to avoid flexing the CSPBGA package and to avoid a point load on the surface of this package during the assembly process.
-16-
REV. PrQ
PRELIMINARY TECHNICAL DATA AD5379
OUTLINE DIMENSIONS
Dimensions shown in mm and (inches).
108-Lead CSPBGA (BC-108)
13.00 (0.512) BSC 11.00 (0.433) BSC
12 11 10 9 8 7 6 5 4 3 2 1
A1
TOP VIEW
13.00 (0.512) BSC
1.00 (0.039) BSC
BOT TOM VIEW
A B C D E F G H J K L M
11.00 (0.433) BSC
1.64 (0.065) MAX
DETAIL A
1.00 (0.039) BSC
SEATING PLANE CONTROLLING DIMENSIONS ARE IN MILLIMETERS 0.50 (0.020) TYP
DETAIL A
0.6 (0.024) TYP BALL DIAMETER
SEATING PLANE
-17- REV. PrQ

▲Up To Search▲

Price & Availability of AD5379

	To Download AD5379 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .