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ADS1216
ADS 121 6
SBAS171B - JUNE 2001
8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER
FEATURES
q 24 BITS NO MISSING CODES q 0.0015% INL q 22 BITS EFFECTIVE RESOLUTION (PGA = 1), 19 BITS (PGA = 128) q PGA FROM 1 TO 128 q SINGLE CYCLE SETTLING MODE q PROGRAMMABLE DATA OUTPUT RATES UP TO 1kHz q ON-CHIP 1.25V/2.5V REFERENCE q EXTERNAL DIFFERENTIAL REFERENCE OF 0.1V TO 2.5V q ON-CHIP CALIBRATION q SPITM COMPATIBLE q 2.7V TO 5.25V q < 1mW POWER CONSUMPTION
DESCRIPTION
The ADS1216 is a precision, wide dynamic range, delta-sigma, Analogto-Digital (A/D) converter with 24-bit resolution operating from 2.7V to 5.25V supplies. The delta-sigma, A/D converter provides up to 24 bits of no missing code performance and effective resolution of 22 bits. The eight input channels are multiplexed. Internal buffering can be selected to provide a very high input impedance for direct connection to transducers or low-level voltage signals. Burn out current sources are provided that allow for the detection of an open or shorted sensor. An 8bit Digital-to-Analog (D/A) converter provides an offset correction with a range of 50% of the FSR (Full-Scale Range). The PGA (Programmable Gain Amplifier) provides selectable gains of 1 to 128 with an effective resolution of 19 bits at a gain of 128. The A/D conversion is accomplished with a second-order deltasigma modulator and programmable sinc filter. The reference input is differential and can be used for ratiometric cancellation. The onboard current DACs (Digital-to-Analog Converters) operate independently with the maximum current set by an external resistor. The serial interface is SPI compatible. Eight bits of digital I/O are also provided that can be used for input or output. The ADS1216 is designed for high-resolution measurement applications in smart transmitters, industrial process control, weight scales, chromatography, and portable instrumentation.
AGND AVDD RDAC VREFOUT VRCAP VREF+ VREF- XIN XOUT
APPLICATIONS
q q q q q q q INDUSTRIAL PROCESS CONTROL LIQUID/GAS CHROMATOGRAPHY BLOOD ANALYSIS SMART TRANSMITTERS PORTABLE INSTRUMENTATION WEIGHT SCALES PRESSURE TRANSDUCERS
SPI is a registered trademark of Motorola.
IDAC2
8-Bit IDAC 1.25V or 2.5V Reference Clock Generator
IDAC1 AVDD
8-Bit IDAC
2A
Offset DAC
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM POL Serial Interface SCLK DIN DOUT CS D0 ... D7 PDWN DSYNC RESET DRDY MUX IN+ IN- BUF + PGA 2nd-Order Modulator A = 1:128 Programmable Digital Filter Registers Controller RAM
2A AGND DVDD DGND BUFEN
Digital I/O Interface
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2000, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
AVDD to AGND ...................................................................... -0.3V to +6V DVDD to DGND ...................................................................... -0.3V to +6V Input Current ............................................................... 100mA, Momentary Input Current ................................................................. 10mA, Continuous AIN ................................................................... GND -0.5V to AVDD + 0.5V AVDD to DVDD ........................................................................... -6V to +6V AGND to DGND ................................................................. -0.3V to +0.3V Digital Input Voltage to GND .................................... -0.3V to DVDD + 0.3V Digital Output Voltage to GND ................................. -0.3V to DVDD + 0.3V Maximum Junction Temperature ................................................... +150C Operating Temperature Range ......................................... -40C to +85C Storage Temperature Range .......................................... -60C to +100C Lead Temperature (soldering, 10s) .............................................. +300C NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE DRAWING NUMBER PFB SPECIFIED TEMPERATURE RANGE -40 to +85 PACKAGE MARKING ADS1216Y ORDERING NUMBER(1) ADS1216Y/250 ADS1216Y/2K TRANSPORT MEDIA Tape and Reel Tape and Reel
PRODUCT ADS1216Y
PACKAGE TQFP-48
"
"
"
"
"
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., / 2K indicates 2000 devices per reel). Ordering 2000 pieces of "ADS1216Y/2K" will get a single 2000-piece Tape and Reel.
ELECTRICAL CHARACTERISTICS: AVDD = 5V
All specifications TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 150k, fDATA = 10Hz, VREF (REF IN+) - (REF IN-) = +2.5V, unless otherwise specified. ADS1216 PARAMETER ANALOG INPUT (AIN0 - AIN7, AINCOM) Analog Input Range Full-Scale Input Voltage Range Differential Input Impedance Input Current Bandwidth Fast Settling Filter Sinc2 Filter Sinc3 Filter Programmable Gain Amplifier Input Capacitance Input Leakage Current Burnout Current Sources OFFSET DAC Offset DAC Range Offset DAC Monotonicity Offset DAC Gain Error Offset DAC Gain Error Drift SYSTEM PERFORMANCE Resolution No Missing Codes Integral Non-Linearity Offset Error(1) Offset Drift(1) Gain Error(1) Gain Error Drift(1) Common-Mode Rejection fCM = fCM = fCM = fSIG = fSIG = CONDITIONS MIN TYP MAX UNITS
Buffer OFF Buffer ON (In+) - (In-), See Block Diagram Buffer OFF Buffer ON -3dB -3dB -3dB User Selectable Gain Ranges Modulator OFF, T = 25C
AGND - 0.1 AGND + 0.05 5/PGA 0.5 0.469 * fDATA 0.318 * fDATA 0.262 * fDATA 1 9 5 2 VREF /(2 * PGA) 8 10 1 24
AVDD + 0.1 AVDD - 1.5 VREF /PGA
V V V M nA Hz Hz Hz
128 pF pA A V Bits % ppm/C Bits Bits % of FS ppm of FS ppm of FS/C % ppm/C dB dB dB dB dB dB dB
sinc3 Filter End Point Fit 7.5 0.02 0.005 0.5 at DC 60Hz, fDATA = 10Hz 50Hz, fDATA = 50Hz 60Hz, fDATA = 60Hz 50Hz, fDATA = 50Hz 60Hz, fDATA = 60Hz 100 130 120 120 100 100 See Typical Characteristics 95
24 0.0015
Normal-Mode Rejection Output Noise Power-Supply Rejection
at DC, dB = -20 log(VOUT /VDD)(2)
80
2
ADS1216
SBAS171B
ELECTRICAL CHARACTERISTICS: AVDD = 5V (Cont.)
All specifications TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 150k, fDATA = 10Hz, VREF (REF IN+) - (REF IN-) = +2.5V, unless otherwise specified. ADS1216 PARAMETER VOLTAGE REFERENCE INPUT Reference Input Range VREF Common-Mode Rejection Common-Mode Rejection Bias Current(3) ON-CHIP VOLTAGE REFERENCE Output Voltage Short-Circuit Current Source Short-Circuit Current Sink Short-Circuit Duration Drift Noise Output Impedance Startup Time IDAC Full-Scale Output Current CONDITIONS MIN TYP MAX UNITS
REF IN+, REF IN- VREF (REF IN+) - (REF IN-) at DC fVREFCM = 60Hz, fDATA = 60Hz VREF = 2.5V REF HI = 1 REF HI = 0
AGND 0.1
2.5 120 120 1.3 2.50 1.25 8 50 Indefinite 15 10 3 50 0.5 1 2 20 Indefinite
AVDD 2.6
V V dB dB A V V mA A ppm/C Vp-p s mA mA mA mA
2.4
2.6
Sink or Source VRCAP = 0.1F, BW = 0.1Hz to 100Hz Sourcing 100A
Maximum Short-Circuit Current Duration Monotonicity Compliance Voltage Output Impedance PSRR Absolute Error Absolute Drift Mismatch Error Mismatch Drift POWER-SUPPLY REQUIREMENTS Power-Supply Voltage Analog Current (IADC + IVREF + IDAC) ADC Current (IADC)
RDAC = 150k, Range = 1 RDAC = 150k, Range = 2 RDAC = 150k, Range = 3 RDAC = 15k, Range = 3 RDAC = 10k RDAC = 0 RDAC = 150k 8 0
10 AVDD - 1 See Typical Characteristics 400 5 75 0.25 15 4.75 1 140 430 180 800 250 480 180 150 230 1 1.6 5.25 225 650 275 1250 375 675 275
Minute Bits V ppm/V % ppm/C % ppm/C V nA A A A A A A A A A nA mW
VOUT = AVDD /2 Individual IDAC Individual IDAC Between IDACs, Same Range and Code Between IDACs, Same Range and Code AVDD PDWN = 0, or SLEEP PGA = 1, Buffer OFF PGA = 128, Buffer OFF PGA = 1, Buffer ON PGA = 128, Buffer ON Excludes Load Current Normal Mode, DVDD = 5V SLEEP Mode, DVDD = 5V Read Data Continuous Mode, DVDD = 5V PDWN PGA = 1, Buffer OFF, REFEN = 0, IDACS OFF, DVDD = 5V -40 -60
VREF Current (IVREF) IDAC Current (IDAC) Digital Current
Power Dissipation TEMPERATURE RANGE Operating Storage
2.5
+85 +100
C C
NOTES: (1) Calibration can minimize these errors. (2) VOUT is change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency.
ADS1216
SBAS171B
3
ELECTRICAL CHARACTERISTICS: AVDD = 3V
All specifications TMIN to TMAX, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 75k, fDATA = 10Hz, VREF (REF IN+) - (REF IN-) = +1.25V unless otherwise specified. ADS1216 PARAMETER ANALOG INPUT (AIN0 - AIN7, AINCOM) Analog Input Range Full-Scale Input Voltage Range Input Impedance Input Current Bandwidth Fast Settling Filter Sinc2 Filter Sinc3 Filter Programmable Gain Amplifier Input Capacitance Input Leakage Current Burnout Current Sources OFFSET DAC Offset DAC Range Offset DAC Monotonicity Offset DAC Gain Error Offset DAC Gain Error Drift SYSTEM PERFORMANCE Resolution No Missing Codes Integral Non-Linearity Offset Error(1) Offset Drift(1) Gain Error(1) Gain Error Drift(1) Common-Mode Rejection fCM = fCM = fCM = fSIG = fSIG = CONDITIONS MIN TYP MAX UNITS
Buffer OFF Buffer ON (In+) - (In-) See Block Diagram Buffer OFF Buffer ON -3dB -3dB -3dB User Selectable Gain Ranges Modulator OFF, T = 25C
AGND - 0.1 AGND + 0.05 5/ PGA 0.5 0.469 * fDATA 0.318 * fDATA 0.262 * fDATA 1 9 5 2 VREF /(2 * PGA) 8 10 2 24
AVDD + 0.1 AVDD - 1.5 VREF /PGA
V V V M nA Hz Hz Hz
128 pF pA A V Bits % ppm/C Bits Bits % of FS ppm of FS ppm of FS/C % ppm/C dB dB dB dB dB dB dB AVDD 1.3 V V dB dB A V mA A ppm/C Vp-p s mA mA mA mA 10 Minute Bits V ppm/V % ppm/C % ppm/C
sinc3 Filter End Point Fit 15 0.04 0.010 1.0 at DC 60Hz, fDATA = 50Hz, fDATA = 60Hz, fDATA = 50Hz, fDATA = 60Hz, fDATA = 100 10Hz 50Hz 60Hz 50Hz 60Hz 75 0 0.1 130 120 120 100 100 See Typical Characteristics 90
24 0.0015
Normal-Mode Rejection Output Noise Power-Supply Rejection VOLTAGE REFERENCE INPUT Reference Input Range VREF Common-Mode Rejection Common-Mode Rejection Bias Current(3) ON-CHIP VOLTAGE REFERENCE Output Voltage Short-Circuit Current Source Short-Circuit Current Sink Short-Circuit Duration Drift Noise Output Impedance Startup Time IDAC Full-Scale Output Current
at DC, dB = -20 log(VOUT /VDD)(2) REF IN+, REF IN- VREF (REF IN+) - (REF IN-) at DC fVREFCM = 60Hz, fDATA = 60Hz VREF = 1.25V REF HI = 0
1.25 120 120 0.65 1.25 3 50 Indefinite 15 10 3 50 0.5 1 2 20 Indefinite
1.2
1.3
Sink or Source VRCAP = 0.1F, BW = 0.1Hz to 100Hz Sourcing 100A
RDAC RDAC RDAC RDAC
Maximum Short-Circuit Current Duration Monotonicity Compliance Voltage Output Impedance PSRR Absolute Error Absolute Drift Mismatch Error Mismatch Drift
= 75k, Range = 75k, Range = 75k, Range = 15k, Range RDAC = 10k RDAC = 0 RDAC = 75k
= = = =
1 2 3 3
8 0 See Typical Characteristics 600 5 75 0.25 15
AVDD - 1
VOUT = AVDD /2 Individual IDAC Individual IDAC Between IDACs, Same Range and Code Between IDACs, Same Range and Code
4
ADS1216
SBAS171B
ELECTRICAL CHARACTERISTICS: AVDD = 3V (Cont.)
All specifications TMIN to TMAX, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 75k, fDATA = 10Hz, VREF (REF IN+) - (REF IN-) = +1.25V unless otherwise specified. ADS1216 PARAMETER POWER-SUPPLY REQUIREMENTS Power-Supply Voltage Analog Current (IADC + IVREF + IDAC) ADC Current (IADC) CONDITIONS AVDD PDWN = 0, or SLEEP PGA = 1, Buffer OFF PGA = 128, Buffer OFF PGA = 1, Buffer ON PGA = 128, Buffer ON Excludes Load Current Normal Mode, DVDD = 3V SLEEP Mode, DVDD = 3V Read Data Continuous Mode, DVDD = 3V PDWN = 0 PGA = 1, Buffer OFF, REFEN = 0, IDACS OFF, DVDD = 3V -40 -60 MIN 2.7 1 120 370 170 750 250 480 90 75 113 1 0.6 TYP MAX 3.3 200 600 250 1200 375 675 200 UNITS V nA A A A A A A A A A nA mW
VREF Current (IVREF) IDAC Current (IDAC) Digital Current
Power Dissipation TEMPERATURE RANGE Operating Storage
1.2
+85 +100
C C
NOTES: (1) Calibration can minimize these errors. (2) VOUT is change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency.
DIGITAL SPECIFICATIONS: TMIN to TMAX, DVDD 2.7V to 5.25V
PARAMETER Digital Input/Output Logic Family Logic Level: VIH VIL VOH VOL Input Leakage: IIH IIL Master Clock Rate: fOSC Master Clock Period: tOSC CONDITIONS MIN TYP MAX UNITS
CMOS 0.8 * DVDD DGND DVDD - 0.4 DGND -10 1 200 DVDD 0.2 * DVDD DGND + 0.4 10 5 1000 V V V V A A MHz ns
IOH = 1mA IOL = 1mA VI = DVDD VI = 0 1/fOSC
ADS1216
SBAS171B
5
PIN CONFIGURATION
Top View DSYNC PDWN DGND DRDY SCLK TQFP
DVDD
DOUT
XOUT 26
POL
DIN
CS
36 D0 37 D1 38 D2 39 D3 40 D4 41 D5 42 D6 43 D7 44 AGND 45 VREFOUT 46 VREF+ 47 VREF- 48 1 AVDD
35
34
33
32
31
30
29
28
27
25 24 RESET 23 BUFEN 22 DGND 21 DGND 20 DGND
XIN 19 DGND 18 DGND 17 RDAC 16 IDAC2 15 IDAC1 14 VRCAP 13 AVDD 12 AGND DESCRIPTION Clock Input Clock Output, used with crystal or resonator. Active LOW. Power Down. The power down function shuts down the analog and digital circuits. Serial Clock Polarity Active LOW, Synchronization Control Digital Ground Digital Power Supply Active LOW, Data Ready Active LOW, Chip Select Serial Clock, Schmitt Trigger Serial Data Input, Schmitt Trigger Serial Data Output Digital I/O 0-7 Analog Ground Voltage Reference Output Positive Differential Reference Input Negative Differential Reference Input
ADS1216
2 AGND
3 AIN0
4 AIN1
5 AIN2
6 AIN3
7 AIN4
8 AIN5
9 AIN6
10 AIN7 XIN
11 AINCOM
PIN DESCRIPTIONS
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18-22 23 24 NAME AVDD AGND AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM AGND AVDD VRCAP IDAC1 IDAC2 RDAC DGND BUFEN RESET DESCRIPTION Analog Power Supply Analog Ground Analog Input 0 Analog Input 1 Analog Input 2 Analog Input 3 Analog Input 4 Analog Input 5 Analog Input 6 Analog Input 7 Analog Input Common Analog Ground Analog Power Supply VREF Bypass CAP Current DAC1 Output Current DAC2 Output Current DAC Resistor Digital Ground Buffer Enable Active LOW, resets the entire chip. 28 29 30 31 32 33 34 35 36 37-44 45 46 47 48 POL DSYNC DGND DVDD DRDY CS SCLK DIN DOUT D0-D7 AGND VREFOUT VREF+ VREF- PIN NUMBER 25 26 27 NAME
XOUT PDWN
6
ADS1216
SBAS171B
TIMING DIAGRAMS
CS t3 SCLK (POL = 0) SCLK (POL = 1) t4 DIN MSB t5 LSB t7 MSB(1) t8 LSB(1) t9 t6 t2 t11 t1 t2 t10
(Command or Command and Data) DOUT NOTE: (1) Bit Order = 0.
SCLK Reset Waveform t13 SCLK t12 t14 t15 t13
ADS1216 Resets On Falling Edge
t16 t17 DRDY RESET, DSYNC, PDWN
TIMING CHARACTERISTICS
SPEC t1 t2 t3 t4 t5 t6 DESCRIPTION SCLK Period SCLK Pulse Width, HIGH and LOW CS LOW to first SCLK Edge; Setup Time(2) DIN Valid to SCLK Edge; Setup Time Valid DIN to SCLK Edge; Hold Time Delay between last SCLK edge for DIN and first SCLK edge for DOUT: RDATA, RDATAC, RREG, WREG, RRAM, WRAM CSREG, CSRAMX, CSRAM CHKARAM, CHKARAMX SCLK Edge to Valid New DOUT SCLK Edge to DOUT, Hold Time Last SCLK Edge to DOUT Tri-State NOTE: DOUT goes tri-state immediately when CS goes HIGH. CS LOW time after final SCLK edge Final SCLK edge of one op code until first edge SCLK of next command: RREG, WREG, RRAM, WRAM, CSRAMX, CSARAMX, CSRAM, CSARAM, CSREG, DSYNC, SLEEP, RDATA, RDATAC, STOPC CREG, CRAM CREGA SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL SELFCAL RESET (Command, SCLK or Pin) MIN 4 3 200 0 50 50 MAX UNITS tOSC Periods DRDY Periods ns ns ns ns
50 200 1100 50 0 6 0 10
t7(1) t8(1) t9 t10 t11
tOSC Periods tOSC Periods tOSC Periods ns ns tOSC Periods ns
tOSC Periods 4 220 1600 7 14 16 300 5 550 1050 4 4 tOSC Periods tOSC Periods tOSC Periods DRDY Periods DRDY Periods tOSC Periods tOSC Periods tOSC Periods tOSC Periods tOSC Periods tOSC Periods tOSC Periods
t12 t13 t14 t15 t16 t17
500 750 1250
Pulse Width DOR Data Not Valid
NOTE: (1) Load = 20pF 10k to DGND. (2) CS may be tied LOW.
ADS1216
SBAS171B
7
TYPICAL CHARACTERISTICS
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150k, fDATA = 10Hz, VREF (REF IN+) - (REF IN-) = +2.5V, unless otherwise specified.
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22
PGA1 PGA2 PGA4 PGA8
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22
PGA2 PGA4 PGA8
21 20 19
21 20 19
PGA1
ENOB (rms)
18 17 16 15 14 13 12 0 500
PGA16
ENOB (rms)
PGA32
18 17 16 15
PGA32 PGA16 PGA64 PGA128
PGA64
PGA128
Sinc3 Filter
14 13 12
Sinc3 Filter, Buffer ON
1000 Decimation Ratio =
1500 fMOD fDATA
2000
0
500
1000 Decimation Ratio =
1500 fMOD fDATA
2000
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22 21 20 19
PGA1 PGA2 PGA4 PGA8
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22
PGA2 PGA4 PGA8
21 20 19
ENOB (rms)
PGA1
ENOB (rms)
18 17 16 15 14 13 12 0 500 1000 Decimation Ratio = 1500 fMOD fDATA 2000 Sinc3 Filter, VREF = 1.25V, BUFFER OFF
PGA16 PGA32 PGA64 PGA128
18 17 16 15 14 13 12 0 500 1000 Decimation Ratio 1500 2000 Sinc3 Filter, VREF = 1.25, BUFFER ON
PGA16 PGA32 PGA64 PGA128
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22
PGA2 PGA4 PGA8
FAST SETTLING FILTER EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22 21 20 19
21 20 19
PGA1
ENOB (rms)
18 17 16 15 14 13 12 0 500 1000 Decimation Ratio = 1500 fMOD fDATA 2000 Sinc2 Filter
PGA32 PGA16 PGA64 PGA128
ENOB (rms)
18 17 16 15 14 13 12 0 500 1000 Decimation Ratio = 1500 fMOD fDATA 2000 Fast Settling Filter
8
ADS1216
SBAS171B
TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150k, fDATA = 10Hz, VREF (REF IN+) - (REF IN-) = +2.5V, unless otherwise specified.
NOISE vs INPUT SIGNAL 0.8 0.7
CMRR vs FREQUENCY 130 120 110 100 90 80 70 60 50 40 30 20 10 0 1 10 100 1k 10k 100k Frequency of CM Signal (Hz)
Noise (rms, ppm of FS)
0.6
0.4 0.3 0.2 0.1 0 -2.5
-1.5
-0.5 VIN (V)
0.5
1.5
2.5
CMRR (dB)
0.5
PSRR vs FREQUENCY 120 110 100 90 80 70 60 50 40 30 20 10 0 1 10 100 1k 10k 100k Frequency of Power Supply (Hz) 50
OFFSET vs TEMPERATURE PGA1 0 PGA16
Offset (ppm of FS)
PSRR (dB)
-50 PGA64 PGA128 -150
-100
-200 -50 -30 -10 10 30 50 70 90 Temperature (C)
GAIN vs TEMPERATURE 1.00010 1.00006
Gain (Normalized)
INTEGRAL NON-LINEARITY vs INPUT SIGNAL 10 8 6
INL (ppm of FS)
-40C
1.00002 0.99998 0.99994 0.99990 0.99986 -50 -30 -10 10 30 50 70 90 Temperature (C)
4 2 0 -2 -4 -6 -8 -10 -2.5
+85C
+25C
-2
-1.5
-1
-0.5
0 VIN (V)
0.5
1
1.5
2
2.5
ADS1216
SBAS171B
9
TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150k, fDATA = 10Hz, VREF (REF IN+) - (REF IN-) = +2.5V, unless otherwise specified.
CURRENT vs TEMPERATURE 250 IDIGITAL
ADC CURRENT vs PGA 900 800 AVDD = 5V, Buffer = ON Buffer = OFF
200
700 600
IADC (A)
Current (A)
150 IANALOG
500 400 300
AVDD = 3V, Buffer = ON Buffer = OFF
100
50
200 100
0 -50 -30 -10 10 30 50 70 90 Temperature (C)
0 0 1 2 4 8 16 32 64 128 PGA Setting
DIGITAL CURRENT 400 350 300 SLEEP 4.91MHz Normal 4.91MHz 4500 4000
HISTOGRAM OF OUTPUT DATA
Number of Occurrences
SLEEP 2.45MHz 4.0 VDD (V) 5.0
3500 3000 2500 2000 1500 1000 500 0 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2
Current (A)
250 200 150 100 50 0 3.0
Normal 2.45MHz
Power Down
ppm of FS
VREFOUT vs LOAD CURRENT 2.55
200 170 140
OFFSET DAC - OFFSET vs TEMPERATURE
Offset (ppm of FSR)
110 80 50 20 -10 -40 -70
VREFOUT (V)
2.50
2.45 -0.5
-100
0
0.5
1.0
1.5
2.0
2.5
-50
-30
-10
10
30
50
70
90
VREFOUT Current Load (mA)
Temperature (C)
10
ADS1216
SBAS171B
TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150k, fDATA = 10Hz, VREF (REF IN+) - (REF IN-) = +2.5V, unless otherwise specified.
OFFSET DAC - GAIN vs TEMPERATURE 1.00020 1.00016 1.00012 IOUT (Normalized)
1.000
IDAC ROUT vs VOUT
+85C 1.000 +25C 0.999
Normalized Gain
1.00008 1.00004 1.00000 0.99996 0.99992 0.99988 0.99984 0.99980 0.99976 -50 -30 -10 10 30 50 70 90 Temperature (C)
0.999 -40C 0.998 0 1 2 3 4 5 VDD - VOUT (V)
IDAC NORMALIZED vs TEMPERATURE 1.01 3000 2000 1.005 1000
IDAC MATCHING vs TEMPERATURE
IDAC Match (ppm)
IOUT (Normalized)
0 -1000 -2000 -3000 -4000 -5000
1
0.995
0.99
0.985 -50 -30 -10 10 30 50 70 90 Temperature (C)
-6000 -50 -30 -10 10 30 50 70 90 Temperature (C)
IDAC DIFFERENTIAL NON-LINEARITY (Range = 1, RDAC = 150k, VREF = 2.5V) 0.5 0.4 0.3 0.2
DNL (LSB) INL (LSB)
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
IDAC INTEGRAL NON-LINEARITY (Range = 1, RDAC = 150k, VREF = 2.5V)
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 32 64 96 128 160 192 224 255 IDAC Code
0
32
64
96
128
160
192
224
255
IDAC Code
ADS1216
SBAS171B
11
OVERVIEW
INPUT MULTIPLEXER The input multiplexer provides for any combination of differential inputs to be selected on any of the input channels, as shown in Figure 1. If channel 1 is selected as the positive differential input channel, any other channel can be selected as the negative differential input channel. With this method, it is possible to have up to eight fully differential input channels. In addition, current sources are supplied that will source or sink current to detect open or short circuits on the pins.
BURNOUT CURRENT SOURCES When the Burnout bit is set in the ACR configuration register, two current sources are enabled. The current source on the positive input channel sources approximately 2A of current. The current source on the negative input channel sinks approximately 2A. This allows for the detection of an open circuit (full-scale reading) or short circuit (0V differential reading) on the selected input differential pair. INPUT BUFFER The input impedance of the ADS1216 without the buffer is 5M/PGA. With the buffer enabled, the input voltage range is reduced and the analog power-supply current is higher. The buffer is controlled by ANDing the state of the buffer pin with the state of the BUFFER bit in the ACR register. IDAC1 AND IDAC2 The ADS1216 has two 8-bit current output DACs that can be controlled independently. The output current is set with RDAC, the range select bits in the ACR register, and the 8-bit digital value in the IDAC register. The output current = VREF /(8 * RDAC)(2RANGE-1)(DAC CODE). With VREFOUT = 2.5V and RDAC = 150k, the full-scale output can be selected to be 0.5, 1, or 2mA. The compliance voltage range is 0 to within 1V of AVDD. When the internal voltage reference of the ADS1216 is used, it is the reference for the IDAC. An external reference may be used for the IDACs by disabling the internal reference and tying the external reference input to the VREFOUT pin. PGA
Burnout Current Source On
AIN0
AIN1
AVDD
AIN2
Burnout Current Source On
AIN3
AIN4
AIN5
AIN6 AGND IDAC1 AIN7
AINCOM
The Programmable Gain Amplifier (PGA) can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can actually improve the effective resolution of the A/D converter. For instance, with a PGA of 1 on a 5V full-scale range, the A/D converter can resolve to 1V. With a PGA of 128 on a 40mV full-scale range, the A/D converter can resolve to 75nV. With a PGA of 1 on a 5V full-scale range, it would require a 26-bit A/D converter to resolve 76nV. PGA OFFSET DAC The input to the PGA can be shifted by half the full-scale input range of the PGA by using the ODAC register. The ODAC (Offset DAC) register is an 8-bit value; the MSB is the sign and the seven LSBs provide the magnitude of the offset. Using the ODAC does not reduce the performance of the A/D. MODULATOR The modulator is a single-loop second-order system. The modulator runs at a clock speed (fMOD) that is derived from the external clock (fOSC). The frequency division is determined by the SPEED bit in the setup register.
FIGURE 1. Input Multiplexer Configuration. TEMPERATURE SENSOR An on-chip diode provides temperature sensing capability. When the configuration register for the input MUX is set to all 1s, the diode is connected to the input of the A/D converter. All other channels are open. The anode of the diode is connected to the positive input of the A/D converter, and the cathode of the diode is connected to negative input of the A/D converter. The output of IDAC1 is connected to the anode to bias the diode and the cathode of the diode is also connected to ground to complete the circuit. In this mode, the output of IDAC1 is also connected to the output pin, so some current may flow into an external load from IDAC1, rather than the diode.
SPEED BIT 0 1
fMOD fOSC /128 fOSC / 256
12
ADS1216
SBAS171B
CALIBRATION The offset and gain errors in the ADS1216, or the complete system, can be reduced with calibration. Internal calibration of the ADS1216 is called self calibration. This is handled with three commands. One command does both offset and gain calibration. There is also a gain calibration command and an offset calibration command. Each calibration process takes seven tDATA periods to complete. Therefore, it takes 14 tDATA periods to complete both an offset and gain calibration. For system calibration, the appropriate signal must be applied to the inputs. The system offset command requires a "zero" differential input signal. It then computes an offset that will nullify offset in the system. The system gain command requires a positive "full-scale" differential input signal. It then computes a value to nullify gain errors in the system. Each of these calibrations will take seven tDATA periods to complete. Calibration should be performed after power on, a change in temperature, or a change of the PGA. The RANGE bit (ACR bit 2) must be zero during calibration. For operation with a reference voltage greater than (AVDD - 1.5) Volts, the buffer must also be turned off during calibration. Calibration will remove the effects of the ODAC, therefore, changes to the ODAC register must be done after calibration, otherwise the calibration will remove the effects of the offset. At the completion of calibration the DRDY signal goes low which indicates the calibration is finished and valid data is available.
settling filter, for the next two conversions the first of which should be discarded. It will then use the sinc2 followed by the sinc3 filter to improve noise performance. This combines the low-noise advantage of the sinc3 filter with the quick response of the fast settling time filter. The frequency response of each filter is shown in Figure 3.
SINC3 FILTER RESPONSE (-3dB = 0.262 * fDATA = 15.76Hz) 0 -20 -40
Gain (dB)
-60 -80 -100 -120 0 30 60 90 120 150 180 210 240 270 300 Frequency (Hz) SINC2 FILTER RESPONSE (-3dB = 0.318 * fDATA = 19.11Hz) 0 -20 -40
Gain (dB)
DIGITAL FILTER The Digital Filter can use either the fast settling, sinc2, or sinc3 filter, as shown in Figure 2. In addition, the Auto mode changes the sinc filter after the input channel or PGA is changed. When switching to a new channel, it will use the fast
Adjustable Digital Filter Sinc3 Modulator Output
-60 -80 -100 -120 0 30 60 90 120 150 180 210 240 270 300 Frequency (Hz)
FAST SETTLING FILTER RESPONSE (-3dB = 0.469 * fDATA = 28.125Hz)
Sinc2
Data Out
0 -20
Fast Settling
-40
FILTER SETTLING TIME FILTER Sinc3 Sinc2 Fast SETTLING TIME (Conversion Cycles) 3(1) 2(1) 1(1)
Gain (dB)
-60 -80 -100 -120 0 30 60 90 120 150 180 210 240 270 300 Frequency (Hz)
NOTE: (1) With Synchronized Channel Changes. AUTO MODE FILTER SELECTION CONVERSION CYCLE 1 Discard 2 Fast 3 Sinc2 4+ Sinc3
NOTE: fDATA = 60Hz.
FIGURE 3. Filter Frequency Responses. FIGURE 2. Filter Step Responses.
ADS1216
SBAS171B
13
VOLTAGE REFERENCE The voltage reference used for the ADS1216 can either be internal or external. The power-up configuration for the voltage reference is 2.5V internal. The selection for the voltage reference is made through the status configuration register. The internal voltage reference is selectable as either 1.25V or 2.5V (AVDD = 5V only). The VREFOUT pin should have a 0.1F capacitor to AGND. The external voltage reference is differential and is represented by the voltage difference between the pins: +VREF and -VREF. The absolute voltage on either pin (+VREF and -VREF) can range from AGND to AVDD, however, the differential voltage must not exceed 2.5V. The differential voltage reference provides easy means of performing ratiometric measurement. VRCAP PIN This pin provides a bypass cap for noise filtering on internal VREF circuitry only. The recommended capacitor is a 0.001F ceramic cap. If an external VREF is used, this pin can be left unconnected. CLOCK GENERATOR The clock source for the ADS1216 can be provided from a crystal, ceramic resonator, oscillator, or external clock. When the clock source is a crystal or ceramic resonator, external capacitors must be provided to ensure start-up and a stable clock frequency. This is shown in Figure 4 and Table I. DIGITAL I/O INTERFACE The ADS1216 has eight pins dedicated for digital I/O. The default power-up condition for the digital I/O pins are as inputs. All of the digital I/O pins are individually configurable
as inputs or outputs. They are configured through the DIR control register. The DIR register defines whether the pin is an input or output, and the DIO register defines the state of the digital output. When the digital I/O are configured as inputs, DIO is used to read the state of the pin. SERIAL INTERFACE The serial interface is standard four-wire SPI compatible (DIN, DOUT, SCLK, and CS). The ADS1216 also offers the flexibility to select the polarity of the serial clock through the POL pin. The serial interface can be clocked up to fOSC/4. Serial communication can occur independent of DRDY, DRDY only indicates the validity of data in the data output register. DSYNC OPERATION DSYNC is used to provide for precise synchronization of the A/D conversion with an external event. Synchronization can be achieved either through the DSYNC pin or the DSYNC command. When the DSYNC pin is used, the filter counter is reset on the falling edge of DSYNC. The filter values are useless, they should be treated as if the input channel was changed. The modulator is held in reset until DSYNC is taken HIGH. Synchronization occurs on the next rising edge of the system clock after DSYNC is taken HIGH. When the DSYNC command is sent, the filter counter is reset on the edge of the last SCLK on the DSYNC command. The modulator is held in RESET until the next edge of SCLK is detected. Synchronization occurs on the next rising edge of the system clock after the first SCLK after the DSYNC command. POWER-UP--SUPPLY VOLTAGE RAMP RATE The power-on reset circuitry was designed to accommodate digital supply ramp rates as slow as 1V/10ms. To ensure proper operation, the power supply should ramp monotonically. RESET
Crystal or Ceramic Resonator
C1
XIN
C2
XOUT
There are three methods of reset. The RESET pin, SCLK pattern, and the RESET command. They all perform the same function. The Power ON state also issues the RESET command. MEMORY
FIGURE 4. Crystal or Ceramic Resonator Connection.
CLOCK SOURCE Crystal Crystal Crystal Crystal PART NUMBER ECS, ECSD 2.45 - 32 ECS, ECSL 4.91 ECS, ECSD 4.91 CTS, MP 042 4M9182
FREQUENCY 2.4576 4.9152 4.9152 4.9152
C1 0-20pF 0-20pF 0-20pF 0-20pF
C2 0-20pF 0-20pF 0-20pF 0-20pF
TABLE I. Typical Clock Sources.
Two types of memory are used on the ADS1216: registers and RAM. 16 registers directly control the various functions (PGA, DAC value, Decimation Ratio, etc.) and can be directly read or written to. Collectively, the registers contain all the information needed to configure the part, such as data format, mux settings, calibration settings, decimation ratio, etc. Additional registers, such as output data, are accessed through dedicated instructions.
14
ADS1216
SBAS171B
ADS1216 REGISTER BANK TOPOLOGY The operation of the device is set up through individual registers. The set of the 16 registers required to configure the device is referred to as a Register Bank, as shown in Figure 5. Reads and Writes to Registers and RAM occur on a byte basis. However, copies between registers and RAM occurs on a bank basis. The RAM is independent of the Registers, i.e.: the RAM can be used as general-purpose RAM. The ADS1216 supports any combination of eight analog inputs. With this flexibility, the device could easily support eight unique configurations--one per input channel. In order to facilitate this type of usage, eight separate register banks are available. Therefore, each configuration could be written once and recalled as needed without having to serially retransmit all the configuration data. Checksum commands are also included, which can be used to verify the integrity of RAM. The RAM provides eight "banks", with a bank consisting of 16 bytes. The total size of the RAM is 128 bytes. Copies between the registers and RAM are performed on a bank basis. Also, the RAM can be directly read or written through the serial interface on power-up. The banks allow separate storage of settings for each input. The RAM address space is linear, therefore accessing RAM is done using an auto-incrementing pointer. Access to RAM in the entire memory map can be done consecutively without having to address each bank individually. For example, if you were currently accessing bank 0 at offset 0xF (the last location of bank 0), the next access would be bank 1 and offset 0x0. Any access after bank 7 and offset 0xF will wrap around to bank 0 and Offset 0x0. Although the Register Bank memory is linear, the concept of addressing the device can also be thought of in terms of bank and offset addressing. Looking at linear and bank addressing syntax, we have the following comparison: in the linear
memory map, the address 0x14 is equivalent to bank 1 and offset 0x4. Simply stated, the most significant four bits represent the bank, and the least significant four bits represent the offset. The offset is equivalent to the register address for that bank of memory.
Configuration Registers 16 bytes
SETUP MUX ACR IDAC1 IDAC2 ODAC DIO DIR DEC0 M/DEC1 OCR0 OCR1 OCR2 FSR0 FSR1 FSR2
RAM 128 Bytes
Bank 0 16 bytes
Bank 2 16 bytes
Bank 7 16 bytes
FIGURE 5. Memory Organization.
ADDRESS 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH
REGISTER SETUP MUX ACR IDAC1 IDAC2 ODAC DIO DIR DEC0 M/DEC1 OCR0 OCR1 OCR2 FSR0 FSR1 FSR2
BIT 7 ID PSEL3 BOCS IDAC1_7 IDAC2_7 SIGN DIO_7 DIR_7 DEC07 DRDY OCR07 OCR15 OCR23 FSR07 FSR15 FSR23
BIT 6 ID PSEL2 IDAC2R1 IDAC1_6 IDAC2_6 OSET_6 DIO_6 DIR_6 DEC06 U/B OCR06 OCR14 OCR22 FSR06 FSR14 FSR22
BIT 5 ID PSEL1 IDAC2R0 IDAC1_5 IDAC2_5 OSET_5 DIO_5 DIR_5 DEC05 SMODE1 OCR05 OCR13 OCR21 FSR05 FSR13 FSR21
BIT 4 SPEED PSEL0 IDAC1R1 IDAC1_4 IDAC2_4 OSET_4 DIO_4 DIR_4 DEC04 SMODE0 OCR04 OCR12 OCR20 FSR04 FSR12 FSR20
BIT 3 REF EN NSEL3 IDAC1R0 IDAC1_3 IDAC2_3 OSET_3 DIO_3 DIR_3 DEC03 Reserved OCR03 OCR11 OCR19 FSR03 FSR11 FSR19
BIT 2 REF HI NSEL2 PGA2 IDAC1_2 IDAC2_2 OSET_2 DIO_2 DIR_2 DEC02 DEC10 OCR02 OCR10 OCR18 FSR02 FSR10 FSR18
BIT 1 BUF EN NSEL1 PGA1 IDAC1_1 IDAC2_1 OSET_1 DIO_1 DIR_1 DEC01 DEC09 OCR01 OCR09 OCR17 FSR01 FSR09 FSR17
BIT 0 BIT ORDER NSEL0 PGA0 IDAC1_0 IDAC2_0 OSET_0 DIO_0 DIR_0 DEC00 DEC08 OCR00 OCR08 OCR16 FSR00 FSR08 FSR16
TABLE II. Registers.
ADS1216
SBAS171B
15
DETAILED REGISTER DEFINITIONS SETUP (Address 00H) Setup Register Reset Value = iii01110
bit 7 ID bit 6 ID bit 5 ID bit 4 SPEED bit 3 REF EN bit 2 REF HI bit 1 bit 0 BUF EN BIT ORDER
ACR (Address 02H) Analog Control Register Reset Value = 00H
bit 7 BOCS bit 6 bit 5 bit 4 bit 3 IDAC1R0 bit 2 PGA2 bit 1 PGA1 bit 0 PGA0 IDAC2R1 IDAC2R0 IDAC1R1
bit 7
bit 7-5 Factory Programmed Bits bit 4 SPEED: Modulator Clock Speed 0 : fMOD = fOSC /128 (default) 1 : fMOD = fOSC /256 bit 3 REF EN: Internal Voltage Reference Enable 0 = Internal Voltage Reference Disabled 1 = Internal Voltage Reference Enabled (default) bit 2 REF HI: Internal Reference Voltage Select 0 = Internal Reference Voltage = 1.25V 1 = Internal Reference Voltage = 2.5V (default) bit 1 BUF EN: Buffer Enable 0 = Buffer Disabled 1 = Buffer Enabled (default) bit 0 BIT ORDER: Set Order Bits are Transmitted 0 = Most Significant Bit Transmitted First (default) 1 = Least Significant Bit Transmitted First Data is always shifted into the part most significant bit first. Data is always shifted out of the part most significant byte first. This configuration bit only controls the bit order within the byte of data that is shifted out. MUX (Address 01H) Multiplexer Control Register Reset Value = 01H
bit 7 PSEL3 bit 6 PSEL2 bit 5 PSEL1 bit 4 PSEL0 bit 3 NSEL3 bit 2 NSEL2 bit 1 NSEL1 bit 0 NSEL0
BOCS: Burnout Current Source 0 = Disabled (default) 1 = Enabled
VREF RANGE -1 IDAC Current = (DAC Code) 2 8 * R DAC
(
)
bit 7-4 PSEL3: PSEL2: PSEL1: PSEL0: Positive Channel Select 0000 = AIN0 (default) 0001 = AIN1 0010 = AIN2 0011 = AIN3 0100 = AIN4 0101 = AIN5 0110 = AIN6 0111 = AIN7 1xxx = AINCOM (except when all bits are 1's) 1111 = Temperature Sensor Diode Anode bit 3-0 NSEL3: NSEL2: NSEL1: NSEL0: Negative Channel Select 0000 = AIN0 0001 = AIN1 (default) 0010 = AIN2 0011 = AIN3 0100 = AIN4 0101 = AIN5 0110 = AIN6 0111 = AIN7 1xxx = AINCOM (except when all bits are 1's) 1111 = Temperature Sensor Diode Cathode Analog GND
bit 6-5 IDAC2R1: IDAC2R0: Full-Scale Range Select for IDAC2 00 = Off (default) 01 = Range 1 10 = Range 2 11 = Range 3 bit 4-3 IDAC1R1: IDAC1R0: Full-Scale Range Select for IDAC1 00 = Off (default) 01 = Range 1 10 = Range 2 11 = Range 3 bit 2-0 PGA2: PGA1: PGA0: Programmable Gain Amplifier Gain Selection 000 = 1 (default) 001 = 2 010 = 4 011 = 8 100 = 16 101 = 32 110 = 64 111 = 128 IDAC1 (Address 03H) Current DAC 1 Reset Value = 00H
bit 7 IDAC1_7 bit 6 IDAC1_6 bit 5 bit 4 bit 3 bit 2 bit 1 IDAC1_1 bit 0 IDAC1_0 IDAC1_5 IDAC1_4 IDAC1_3 IDAC1_2
The DAC code bits set the output of DAC1 from 0 to fullscale. The value of the full-scale current is set by this Byte, VREF, RDAC, and the DAC1 range bits in the ACR register. IDAC2 (Address 04H) Current DAC 2 Reset Value = 00H
bit 7 IDAC2_7 bit 6 IDAC2_6 bit 5 bit 4 bit 3 bit 2 bit 1 IDAC1_1 bit 0 IDAC1_0 IDAC2_5 IDAC2_4 IDAC1_3 IDAC1_2
The DAC code bits set the output of DAC2 from 0 to fullscale. The value of the full-scale current is set by this Byte, VREF, RDAC, and the DAC2 range bits in the ACR register.
16
ADS1216
SBAS171B
ODAC (Address 05H) Offset DAC Setting Reset Value = 00H
bit 7 SIGN bit 6 OSET6 bit 5 OSET5 bit 4 OSET4 bit 3 OSET3 bit 2 OSET2 bit 1 OSET1 bit 0 OSET0
U/B 0
ANALOG INPUT +FS Zero -FS +FS Zero -FS
DIGITAL OUTPUT 0x7FFFFF 0x000000 0x800000 0xFFFFFF 0x000000 0x000000
1
bit 7
Offset Sign 0 = Positive 1 = Negative
bit 6-0 Offset =
VREF Code * 127 2 * PGA
NOTE: The offset must be used after calibration or the calibration will notify the effects. DIO (Address 06H) Digital I/O
bit 7 DIO7 bit 6 DIO6 bit 5 DIO5 bit 4 DIO4 bit 3 DIO3
bit 5-4 SMODE1: SMODE0: Settling Mode 00 = Auto (default) 01 = Fast Settling filter 10 = Sinc2 filter 11 = Sinc3 filter bit 2-0 DEC10: DEC09: DEC08: Most Significant Bits of the Decimation Value OCR0 (Address 0AH) Offset Calibration Coefficient (Least Significant Byte) Reset Value = 00H
bit 7 OCR07 bit 6 OCR06 bit 5 OCR05 bit 4 OCR04 bit 3 OCR03 bit 2 OCR02 bit 1 OCR01 bit 0 OCR00
Reset Value = 00H
bit 2 DIO2 bit 1 DIO1 bit 0 DIO0
A value written to this register will appear on the digital I/O pins if the pin is configured as an output in the DIR register. Reading this register will return the value of the digital I/O pins. DIR (Address 07H) Direction control for digital I/O Reset Value = FFH
bit 7 DIR7 bit 6 DIR6 bit 5 DIR5 bit 4 DIR4 bit 3 DIR3 bit 2 DIR2 bit 1 DIR1 bit 0 DIR0
OCR1 (Address 0BH) Offset Calibration Coefficient (Middle Byte) Reset Value = 00H
bit 7 OCR15 bit 6 OCR14 bit 5 OCR13 bit 4 OCR12 bit 3 OCR11 bit 2 OCR10 bit 1 OCR09 bit 0 OCR08
Each bit controls whether the Digital I/O pin is an output (= 0) or input (= 1). The default power-up state is as inputs. DEC0 (Address 08H) Decimation Register (Least Significant 8 bits) Reset Value = 80H
bit 7 DEC07 bit 6 DEC06 bit 5 DEC05 bit 4 DEC04 bit 3 DEC03 bit 2 DEC02 bit 1 DEC01 bit 0 DEC00
OCR2 (Address 0CH) Offset Calibration Coefficient (Most Significant Byte) Reset Value = 00H
bit 7 OCR23 bit 6 OCR22 bit 5 OCR21 bit 4 OCR20 bit 3 OCR19 bit 2 OCR18 bit 1 OCR17 bit 0 OCR16
The decimation value is defined with 11 bits for a range of 20 to 2047. This register is the least significant 8 bits. The 3 most significant bits are contained in the M/DEC1 register. The default data rate is 10Hz with a 2.4576MHz crystal. M/DEC1 (Address 09H) Mode and Decimation Register Reset Value = 07H
bit 7 DRDY bit 6 U/B bit 5 bit 4 bit 3 Reserved bit 2 DEC10 bit 1 DEC09 bit 0 DEC08 SMODE1 SMODE0
FSR0 (Address 0DH) Full-Scale Register (Least Significant Byte) Reset Value = 24H
bit 7 FSR07 bit 6 FSR06 bit 5 FSR05 bit 4 FSR04 bit 3 FSR03 bit 2 FSR02 bit 1 FSR01 bit 0 FSR00
FSR1 (Address 0EH) Full-Scale Register (Middle Byte) Reset Value = 90H
bit 7 FSR15 bit 6 FSR14 bit 5 FSR13 bit 4 FSR12 bit 3 FSR011 bit 2 FSR10 bit 1 FSR09 bit 0 FSR08
bit 7
DRDY: Data Ready (Read Only) This bit duplicates the state of the DRDY pin. U/B: Data Format 0 = Bipolar (default) 1 = Unipolar
bit 6
FSR2 (Address 0FH) Full-Scale Register (Most Significant Byte) Reset Value = 67H
bit 7 FSR23 bit 6 FSR22 bit 5 FSR21 bit 4 FSR20 bit 3 FSR019 bit 2 FSR18 bit 1 FSR17 bit 0 FSR16
ADS1216
SBAS171B
17
ADS1216 CONTROL
COMMAND DEFINITIONS The commands listed below control the operation of the ADS1216. Some of the commands are stand-alone commands (e.g., RESET) while others require additional bytes (e.g., WREG requires command, count, and the data bytes). Op codes that output data require a minimum of four fOSC cycles before the data is ready (e.g., RDATA). Operands: n = count (0 to 127) r = register (0 to 15) x = don't care a = RAM bank address (0 to 7)
COMMAND BYTE 0000 0000 0000 0001 0010 0100 0100 0101 0110 1100 1101 1101 1101 1110 1110 1111 1111 1111 1111 1111 1111 1111 1111 0001 (01H) 0011 (03H) 1111 (0FH) r r r r (1xH) 0aaa (2xH) 0aaa (4xH) 1000 (48H) r r r r (5xH) 0aaa (6xH) 0aaa (CxH) 0aaa (DxH) 1000 (D8H) 1111 (DFH) 0aaa (ExH) 1000 (E8H) 0000 (F0H) 0001 (F1H) 0010 (F2H) 0011 (F3H) 0100 (F4H) 1100 (FCH) 1101 (FDH) 1110 (FEH) 2ND COMMAND BYTE -- -- -- xxxx_nnnn (# of reg-1) xnnn_nnnn (# of bytes-1) -- -- xxxx_nnnn (# of reg-1) xnnn_nnnn (# of bytes-1) -- -- -- -- -- -- -- -- -- -- -- -- -- --
COMMANDS RDATA RDATAC STOPC RREG RRAM CREG CREGA WREG WRAM CRAM CSRAMX CSARAMX CSREG CSRAM CSARAM SELFCAL SELFOCAL SELFGCAL SYSOCAL SYSGCAL DSYNC SLEEP RESET
DESCRIPTION Read Data Read Data Continuously Stop Read Data Continuously Read from REG Bank "rrrr" Read from RAM Bank "aaa" Copy REGs to RAM Bank "aaa" Copy REGS to all RAM Banks Write to REG "rrrr" Write to RAM Bank "aaa" Copy RAM Bank "aaa" to REG Calc RAM Bank "aaa" Checksum Calc all RAM Bank Checksum Calc REG Checksum Calc RAM Bank "aaa" Checksum Calc all RAM Banks Checksum Self Cal Offset and Gain Self Cal Offset Self Cal Gain Sys Cal Offset Sys Cal Gain Sync DRDY Put in SLEEP Mode Reset to Power-Up Values
NOTE: (1) The data received by the A/D is always MSB First, the data out format is set by the BIT ORDER bit in ACR reg.
TABLE III. Command Summary.
RDATA
Read Data
RDATAC
Read Data Continuous
Description: Read a single data value from the Data Output Register (DOR) which is the most recent conversion result. This is a 24-bit value. Operands: None Bytes: 1 Encoding: 0000 0001 Data Transfer Sequence:
DIN 0000 0001 * * *(1) xxxx xxxx xxxx xxxx xxxx xxxx
Description: Read Data Continuous mode enables the continuous output of new data on each DRDY. This command eliminates the need to send the Read Data Command on each DRDY. This mode may be terminated by either the STOP Read Continuous command or the RESET command. Operands: None Bytes: 1 Encoding: 0000 0011 Data Transfer Sequence: Command terminated when "uuuu uuuu" equals STOPC or RESET.
DIN 0000 0011 * * *(1) uuuu uuuu uuuu uuuu uuuu uuuu *** DOUT DRDY xxxx xxxx * * *(1) MSB Mid-Byte LSB
DOUT
xxxx xxxx
* * *(1)
MSB
Mid-Byte
LSB
NOTE: (1) For wait time, refer to timing specification.
*** xxxx *** xxxx xxxx
DIN
DOUT
MSB
Mid-Byte
LSB
NOTE: (1) For wait time, refer to timing specification.
18
ADS1216
SBAS171B
STOPC
Stop Continuous
CREG
Copy Registers to RAM Bank
Description: Ends the continuous data output mode. Operands: None Bytes: 1 Encoding: 0000 1111 Data Transfer Sequence:
DIN 0000 1111
Description: Copy the 16 control registers to the RAM bank specified in the op code. Refer to timing specifications for command execution time. Operands: a Bytes: 1 Encoding: 0100 0aaa Data Transfer Sequence: Copy Register Values to RAM Bank 3
DIN 0100 0011
DOUT
xxxx xxxx
RREG
Read from Registers CREGA
DOUT
xxxx xxxx
Description: Output the data from up to 16 registers starting with the register address specified as part of the instruction. The number of registers read will be one plus the second byte. If the count exceeds the remaining registers, the addresses will wrap back to the beginning. Operands: r, n Bytes: 2 Encoding: 0001 rrrr xxxx nnnn Data Transfer Sequence: Read Two Registers Starting from Register 01H (MUX)
DIN 0001 0001 0000 0001 * * *(1) xxxx xxxx xxxx xxxx
Copy Registers to All RAM Banks
Description: Duplicate the 16 control registers to all the RAM banks. Refer to timing specifications for command execution time. Operands: None Bytes: 1 Encoding: 0100 1000 Data Transfer Sequence:
DIN 0100 1000
DOUT
xxxx xxxx
xxxx xxxx
* * *(1)
MUX
ACR
DOUT
xxxx xxxx
NOTE: (1) For wait time, refer to timing specification.
WREG RRAM Read from RAM
Description: Up to 128 bytes can be read from RAM starting at the bank specified in the op code. All reads start at the address for the beginning of the RAM bank. The number of bytes to read will be one plus the value of the second byte. Operands: a, n Bytes: 2 Encoding: 0010 0aaa xnnn nnnn Data Transfer Sequence: Read Two RAM Locations Starting from 20H
DIN 0010 0010 x000 0001 * * *(1) xxxx xxxx xxxx xxxx
Write to Register
Description: Write to the registers starting with the register specified as part of the instruction. The number of registers that will be written is one plus the value of the second byte. Operands: r, n Bytes: 2 Encoding: 0101 rrrr xxxx nnnn Data Transfer Sequence: Write Two Registers Starting from 06H (DIO)
DIN 0101 0110 xxxx 0001 Data for DIO Data for DIR
DOUT
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
DOUT
xxxx xxxx
xxxx xxxx
* * *(1)
RAM Data 20H
RAM Data 21H
NOTE: (1) For wait time, refer to timing specification.
ADS1216
SBAS171B
19
WRAM
Write to RAM
Description: Write up to 128 RAM locations starting at the beginning of the RAM bank specified as part of the instruction. The number of bytes written is RAM is one plus the value of the second byte. Operands: a, n Bytes: 2 Encoding: 0110 0aaa xnnn nnnn Data Transfer Sequence: Write to Two RAM Locations starting from 10H
DIN 0110 0001 x000 0001 Data for 10H xxxx xxxx Data for 11H xxxx xxxx
CSARAMX Calculate the Checksum for all RAM Banks
Description: Calculate the checksum of all RAM Banks. The checksum is calculated as a sum of all the bytes with the carry ignored. The ID, DRDY and DIO bits are masked so they are not included in the checksum. Operands: None Bytes: 1 Encoding: 1101 1000 Data Transfer Sequence:
DIN 1101 1000
DOUT
xxxx xxxx
xxxx xxxx
DOUT
xxxx xxxx
CRAM
Copy RAM Bank to Registers
CSREG
Description: Copy the selected RAM Bank to the Configuration Registers. This will overwrite all of the registers with the data from the RAM bank. Operands: a Bytes: 1 Encoding: 1100 0aaa Data Transfer Sequence: Copy RAM Bank 0 to the Registers
DIN 1100 0000
Calculate the Checksum of Registers
Description: Calculate the checksum of all the registers. The checksum is calculated as a sum of all the bytes with the carry ignored. The ID, DRDY and DIO bits are masked so they are not included in the checksum. Operands: None Bytes: 1 Encoding: 1101 1111 Data Transfer Sequence:
DIN 1101 1111
DOUT
xxxx xxxx DOUT xxxx xxxx
CSRAMX
Calculate RAM Bank Checksum CSRAM Calculate RAM Bank Checksum
Description: Calculate the checksum of the selected RAM Bank. The checksum is calculated as a sum of all the bytes with the carry ignored. All bits are included in the checksum calculation, there is no masking of bits. Operands: a Bytes: 1 Encoding: 1110 0aaa Data Transfer Sequence: Calculate Checksum for RAM Bank 2
DIN DOUT xxxx xxxx DOUT xxxx xxxx 1110 0010
Description: Calculate the checksum of the selected RAM Bank. The checksum is calculated as a sum of all the bytes with the carry ignored. The ID, DRDY and DIO bits are masked so they are not included in the checksum. Operands: a Bytes: 1 Encoding: 1101 0aaa Data Transfer Sequence: Calculate Checksum for RAM Bank 3
DIN 1101 0011
20
ADS1216
SBAS171B
CSARAM
Calculate Checksum for all RAM Banks
SELFGCAL Gain Self Calibration
Description: Starts the process of self-calibration for gain. The Full-Scale Register (FSR) is updated with new values after this operation. Operands: None Bytes: 1 Encoding: 1111 0010 Data Transfer Sequence:
DIN 1111 0010
Description: Calculate the checksum of all RAM Banks. The checksum is calculated as a sum of all the bytes with the carry ignored. All bits are included in the checksum calculation, there is no masking of bits. Operands: None Bytes: 1 Encoding: 1110 1000 Data Transfer Sequence:
DIN 1110 1000
DOUT
xxxx xxxx
DOUT
xxxx xxxx
SYSOCAL SELFCAL Offset and Gain Self Calibration
System Offset Calibration
Description: Starts the process of self calibration. The Offset Control Register (OCR) and the Full-Scale Register (FSR) are updated with new values after this operation. Operands: None Bytes: 1 Encoding: 1111 0000 Data Transfer Sequence:
DIN 1111 0000
Description: Starts the system offset calibration process. For a system offset calibration the input should be set to 0V differential, and the ADS1216 computes the OCR register value that will compensate for offset errors. The Offset Control Register (OCR) is updated after this operation. Operands: None Bytes: 1 Encoding: 1111 0011 Data Transfer Sequence:
DIN 1111 0011
DOUT
xxxx xxxx
DOUT
xxxx xxxx
SELFOCAL Offset Self Calibration
Description: Starts the process of self-calibration for offset. The Offset Control Register (OCR) is updated after this operation. Operands: None Bytes: 1 Encoding: 1111 0001 Data Transfer Sequence:
DIN 1111 0001
SYSGCAL
System Gain Calibration
Description: Starts the system gain calibration process. For a system gain calibration, the differential input should be set to the reference voltage and the ADS1216 computes the FSR register value that will compensate for gain errors. The FSR is updated after this operation. Operands: None Bytes: 1 Encoding: 1111 0100 Data Transfer Sequence:
DIN 1111 0100
DOUT
xxxx xxxx
DOUT
xxxx xxxx
ADS1216
SBAS171B
21
DSYNC
Sync DRDY
RESET
Reset to Powerup Values
Description: Synchronizes the ADS1216 to the serial clock edge. Operands: None Bytes: 1 Encoding: 1111 1100 Data Transfer Sequence:
DIN 1111 1100
Description: Restore the registers to their power-up values. This command will also stop the Read Continuous mode. It does not affect the contents of RAM. Operands: None Bytes: 1 Encoding: 1111 1110 Data Transfer Sequence:
DIN 1111 1110
DOUT
xxxx xxxx DOUT xxxx xxxx
SLEEP
Sleep Mode
Description: Puts the ADS1216 into a low power sleep mode. To exit sleep mode strobe SCLK. Operands: None Bytes: 1 Encoding: 1111 1101 Data Transfer Sequence:
DIN 1111 1101
DOUT
xxxx xxxx
LSB MSB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 x rreg 0 rram 0 x creg 0 wreg 0 wram 0 x x x x x 0001 rdata rreg 1 rram 1 x creg 1 wreg 1 wram 1 x x x x x 0010 x rreg 2 rram 2 x creg 2 wreg 2 wram 2 x x x x x cram 2 0011 rdatac rreg 3 rram 3 x creg 3 wreg 3 wram 3 x x x x x 0100 x rreg 4 rram 4 x creg 4 wreg 4 wram 4 x x x x x 0101 x rreg 5 rram 5 x creg 5 wreg 5 wram 5 x x x x x 0110 x rreg 6 rram 6 x creg 6 wreg 6 wram 6 x x x x x 0111 x rreg 7 rram 7 x creg 7 wreg 7 wram 7 x x x x x cram 7 csramx 7 cs ram 7 x 1000 x rreg 8 x x crega wreg 8 x x x x x x x csa ramx csa ram x 1001 x rreg 9 x x x wreg 9 x x x x x x x x x x 1010 x rreg A x x x wreg A x x x x x x x x x x 1011 x rreg B x x x wreg B x x x x x x x x x x 1100 x rreg C x x x wreg C x x x x x x x x x dsync 1101 x rreg D x x x wreg D x x x x x x x x x sleep 1110 x rreg E x x x wreg E x x x x x x x x csreg x reset x x 1111 stopc rreg F x x x wreg F x x x x x x x
cram 0 cram 1 csramx csramx 0 1 cs ram 0 self cal cs ram 1 self ocal
cram 3 cram 4
cram 5 cram 6
csramx csramx csramx csramx csramx 2 3 4 5 6 cs ram2 self gcal cs ram 3 sys ocal cs ram 4 sys gcal cs ram 5 x cs ram 6 x
x = Reserved
TABLE IV. Command Map. 22
ADS1216
SBAS171B
SERIAL PERIPHERAL INTERFACE The Serial Peripheral Interface (SPI), allows a controller to communicate synchronously with the ADS1216. The ADS1216 operates in slave only mode. SPI Transfer Formats During an SPI transfer, data is simultaneously transmitted and received. The SCLK signal synchronizes shifting and sampling of the information on the two serial data lines: DIN and DOUT. The CS signal allows individual selection of an ADS1216 device; an ADS1216 with CS HIGH is not active on the bus. Clock Phase and Polarity Controls (POL) The clock polarity is specified by the POL pin, which selects an active HIGH or active LOW clock, and has no effect on the transfer format. Serial Clock (SCLK) SCLK, a Schmitt Trigger input to the ADS1216, is generated by the master device and synchronizes data transfer on the DIN and DOUT lines. When transferring data to or from the ADS1216, burst mode may be used i.e., multiple bits of data may be transferred back-to-back with no delay in SCLKs or toggling of CS. Chip Select (CS) The chip select (CS) input of the ADS1216 must be externally asserted before a master device can exchange data with the ADS1216. CS must be LOW before data transactions and must stay LOW for the duration of the transaction. DIGITAL INTERFACE The ADS1216's programmable functions are controlled using a set of on-chip registers, as outlined previously. Data is written to these registers via the part's serial interface and read access to the on-chip registers is also provided by this interface. The ADS1216's serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The DIN line is used for transferring data into the on-chip registers while the DOUT line is used for accessing data from the on-chip registers. SCLK is the serial clock input for the device and all data transfers (either on DIN or DOUT) take place with respect to this SCLK signal. The DRDY line is used as a status signal to indicate when data is ready to be read from the ADS1216's data register. DRDY goes LOW when a new data word is available in the DOR register. It is reset HIGH when a read operation from the data register is complete. It also goes HIGH prior to the updating of the output register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. CS is used to select the device. It can be used to decode the ADS1216 in systems where a number of parts are connected to the serial bus.
The timing specification shows the timing diagram for interfacing to the ADS1216 with CS used to decode the part. The ADS1216 serial interface can operate in three-wire mode by tying the CS input LOW. In this case, the SCLK, DIN, and DOUT lines are used to communicate with the ADS1216 and the status of DRDY can be obtained by interrogating bit 7 of the M/DEC1 register. This scheme is suitable for interfacing to microcontrollers. If CS is required as a decoding signal, it can be generated from a port pin. DEFINITION OF TERMS Analog Input Voltage--the voltage at any one analog input relative to AGND. Analog Input Differential Voltage--given by the following equation: (IN+ - IN-). Thus, a positive digital output is produced whenever the analog input differential voltage is positive, while a negative digital output is produced whenever the differential is negative. For example, when the converter is configured with a 2.5V reference and placed in a gain setting of 1, the positive full-scale output is produced when the analog input differential is 2.5V. The negative full-scale output is produced when the differential is -2.5V. In each case, the actual input voltages must remain within the AGND to AVDD range. Conversion Cycle--the term "conversion cycle" usually refers to a discrete A/D conversion operation, such as that performed by a successive approximation converter. As used here, a conversion cycle refers to the tDATA time period. However, each digital output is actually based on the modulator results from several tDATA time periods.
FILTER SETTING fast settling sinc2 sinc3 MODULATOR RESULTS 1 tDATA time period 2 tDATA time period 3 tDATA time period
Data Rate--The rate at which conversions are completed. See definition for fDATA. Decimation Ratio--defines the ratio between the output of the modulator and the output Data Rate. Valid values for the Decimation Ratio are from 20 to 2047. Larger Decimation Ratios will have lower noise and vice-versa.
ADS1216
SBAS171B
23
Effective Resolution--the effective resolution of the ADS1216 in a particular configuration can be expressed in two different units: bits rms (referenced to output) and Vrms (referenced to input). Computed directly from the converter's output data, each is a statistical calculation. The conversion from one to the other is shown below. "Effective number of bits" (ENOB) or "effective resolution" is commonly used to define the usable resolution of the A/D converter. It is calculated from empirical data taken directly from the device. It is typically determined by applying a fixed known signal source to the analog input and computing the standard deviation of the data sample set. The rms noise defines the interval about the sample mean (which implies that 95% of the data values fall within this range) and the peak-to-peak noise defines the 3 interval about the sample mean (which implies that 99.6% of the data values fall within this range). The data from the A/D converter is output as codes, which then can be easily converted to other units, such as ppm or volts. The equations and table below show the relationship between bits or codes, ppm, and volts. -20 log ( ppm ) ENOB = 6.02
fOSC--the frequency of the crystal oscillator or CMOS compatible input signal at the XIN input of the ADS1216. fMOD--the frequency or speed at which the modulator of the ADS1216 is running. This depends on the SPEED bit as given by the following equation:
SPEED = 0 mfactor 128
SPEED = 1 256
fMOD =
fOSC mfactor
fSAMP--the frequency, or switching speed, of the input sampling capacitor. The value is given by one of the following equations:
PGA SETTING 1, 2, 4, 8 SAMPLING FREQUENCY f SAMP = f SAMP = f SAMP = f SAMP = fOSC mfactor fOSC * 2 mfactor fOSC * 4 mfactor fOSC * 8 mfactor
16
32
64, 128 BITS rms BIPOLAR Vrms UNIPOLAR Vrms
2 * VREF PGA 10
24 22 20 18 16 14 12
6.02 * ER 20
VREF PGA 10
6.02 * ER 20
fDATA--the frequency of the digital output data produced by the ADS1216, fDATA is also referred to as the Data Rate.
fMOD fOSC fDATA = = Decimation Ratio mfactor * Decimation Ratio
298nV 1.19V 4.77V 19.1V 76.4V 505V 1.22mV
149nV 597nV 2.39V 9.55V 38.2V 152.7V 610V
Filter Selection--the ADS1216 uses a (sinx /x) filter or sinc filter. Actually there are three different sinc filters that can be selected. A fast settling filter will settle in one tDATA cycle. The sinc2 filter will settle in two cycles and have lower noise. The sinc3 will achieve lowest noise and higher number of effective bits, but requires three cycles to settle. The ADS1216 will operate with any one of these filters, or it can operate in an auto mode, where it will select the fast settling filter after a new channel is selected and will then switch to sinc2 followed by sinc3. This allows fast settling response and still achieves low noise after the necessary number of tDATA cycles.
Full-Scale Range (FSR)--as with most A/D converters, the full-scale range of the ADS1216 is defined as the "input", which produces the positive full-scale digital output minus the "input", which produces the negative full-scale digital output. The full-scale range changes with gain setting as shown in Table V. For example, when the converter is configured with a 2.5V reference and is placed in a gain setting of 2, the full-scale range is: [1.25V (positive full-scale) minus -1.25V (negative full-scale)] = 2.5V. Least Significant Bit (LSB) Weight--this is the theoretical amount of voltage that the differential voltage at the analog input would have to change in order to observe a change in the output data of one least significant bit. It is computed as follows: LSB Weight = Full - Scale Range 2N
where N is the number of bits in the digital output. tDATA--the inverse of fDATA, or the period between each data output.
24
ADS1216
SBAS171B
5V SUPPLY ANALOG INPUT(1) GAIN SETTING 1 2 4 8 16 32 64 128 FULL-SCALE RANGE 5V 2.5V 1.25V 0.625V 312.5mV 156.25mV 78.125mV 39.0625mV DIFFERENTIAL INPUT VOLTAGES(2) 2.5V 1.25V 0.625V 312.5mV 156.25mV 78.125mV 39.0625mV 19.531mV PGA OFFSET RANGE 1.25V 0.625V 312.5mV 156.25mV 78.125mV 39.0625mV 19.531mV 9.766mV FULL-SCALE RANGE 2 * VREF PGA
GENERAL EQUATIONS DIFFERENTIAL INPUT VOLTAGES(2) VREF PGA PGA SHIFT RANGE VREF 2 * PGA
NOTES: (1) With a 2.5V reference. (2) The ADS1216 allows common-mode voltage as long as the absolute input voltage on AINP or AINN does not go below AGND or above AVDD.
TABLE V. Full-Scale Range versus PGA Setting.
ADS1216
SBAS171B
25
TOPIC INDEX
TOPIC PAGE
ABSOLUTE MAXIMUM RATINGS ..........................................................................................................................2 PACKAGE/ORDERING INFORMATION .................................................................................................................2 ELECTRICAL CHARACTERISTICS (AVDD = 5V) .............................................................................................. 2-3 ELECTRICAL CHARACTERISTICS (AVDD = 3V) .............................................................................................. 4-5 PIN CONFIGURATION ............................................................................................................................................6 TIMING CHARACTERISTICS ..................................................................................................................................7 TYPICAL CHARACTERISTICS ......................................................................................................................... 8-11 OVERVIEW .............................................................................................................................................................12 MEMORY ................................................................................................................................................................14 ADS1216 REGISTER BANK TOPOLOGY ...........................................................................................................15 DETAILED REGISTER DEFINITIONS ............................................................................................................ 16-17 COMMAND DEFINITIONS ............................................................................................................................... 18-22 ADS1216 COMMAND MAP ...................................................................................................................................22 SERIAL PERIPHERAL INTERFACE .....................................................................................................................23 DIGITAL INTERFACE ............................................................................................................................................23 DEFINITION OF TERMS .................................................................................................................................. 23-24
26
ADS1216
SBAS171B
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