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| ADS8325 ADS8 325 ADS8 325 SBAS226A - MARCH 2002 - REVISED JUNE 2003 16-Bit, High-Speed, 2.7V to 5.5V microPower Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES q q q q q q q 16-BITS NO MISSING CODES VERY LOW NOISE: 3LSBp-p EXCELLENT LINEARITY: 1.5LSB typ microPOWER: 4.5mW at 100kHz 1mW at 10kHz MSOP-8 AND SON-8 PACKAGES (SON Package Size Same as 3x3 QFN) 16-BIT UPGRADE TO THE 12-BIT ADS7816 AND ADS7822 PIN-COMPATIBLE WITH THE ADS7816, ADS7822, ADS7826, ADS7827, ADS7829, AND ADS8320 SERIAL (SPITM/SSI) INTERFACE DESCRIPTION The ADS8325 is a 16-bit, sampling, Analog-to-Digital (A/D) converter specified for a supply voltage range from 2.7V to 5.5V. It requires very little power, even when operating at the full 100kHz data rate. At lower data rates, the high speed of the device enables it to spend most of its time in the powerdown mode. For example, the average power dissipation is less than 1mW at a 10kHz data rate. The ADS8325 offers excellent linearity and very low noise and distortion. It also features a synchronous serial (SPI/SSI compatible) interface and a differential input. The reference voltage can be set to any level within the range of 2.5V to VDD. Low power and small size make the ADS8325 ideal for portable and battery-operated systems. It is also a perfect fit for remote data acquisition modules, simultaneous multichannel systems, and isolated data acquisition. The ADS8325 is available in MSOP-8 and SON-8 packages. The SON package size is the same as a 3x3 QFN package. q APPLICATIONS q q q q BATTERY-OPERATED SYSTEMS REMOTE DATA ACQUISITION ISOLATED DATA ACQUISITION SIMULTANEOUS SAMPLING, MULTI-CHANNEL SYSTEMS q INDUSTRIAL CONTROLS q ROBOTICS q VIBRATION ANALYSIS SAR REF ADS8325 DOUT +IN CDAC -IN S/H Amp Comparator CS/SHDN Serial Interface DCLOCK Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2002-2003, Texas Instruments Incorporated www.ti.com ABSOLUTE MAXIMUM RATINGS(1) over operating free-air temperature, unless otherwise noted. Supply Voltage, DGND to VDD .................................................................. -0.3V to 6V Analog Input Voltage(2) ............................................................... -0.3V to VDD + 0.3V Reference Input Voltage(2) ........................................................ -0.3V to VDD + 0.3V Digital Input Voltage(2) ............................................................. -0.3V to VDD + 0.3V Input Current to Any Pin Except Supply ......................... -20mA to 20mA Power Dissipation ....................................... See Dissipation Rating Table Operating Virtual Junction Temperature Range, TJ ...... -40C to +150C Operating Free-Air Temperature Range, TA .................... -40C to +85C Storage Temperature Range, TSTG ................................ -65C to +150C Lead Temperature 1.6mm (1/16 inch) from Case for 10sec ..................... 260C NOTES: (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions of extended periods may affect device reliability. (2) All voltage values are with respect to ground terminal. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION MAXIMUM NO INTEGRAL MISSING LINEARITY CODES ERROR ERROR (LSB) (LSB)(1) 6 15 SPECIFIED PACKAGEPACKAGE TEMPERATURE LEAD DESIGNATOR(2) RANGE MSOP-8 DGK -40C to 85C PRODUCT ADS8325I PACKAGE MARKING B25 ORDERING NUMBER ADS8325IDGKT ADS8325IDGKR ADS8325IBDGKT ADS8325IBDGKR ADS8325IDRBT ADS8325IDRBR ADS8325IBDRBT ADS8325IBDRBR TRANSPORT MEDIA, QUANTITY Tape and Reel, 250 Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 2500 " ADS8325IB " 4 " 16 " MSOP-8 " DGK " -40C to 85C " B25 " ADS8325I " 6 " 15 " SON-8 " DRB " -40C to 85C " B25 " ADS8325IB " 4 " 16 " SON-8 " DRB " -40C to 85C " B25 " " " " " " " NOTE: (1) No Missing Codes Error specifies a 5V power supply and reference voltage. (2) For the most current specifications and package information, refer to our web site at www.ti.com. PACKAGE DISSIPATION RATING TABLE PACKAGE DGK DRB R JC 39.1C/W 5C/W R JA 206.3C/W 45.8C/W DERATING FACTOR ABOVE TA = 25C 4.847mW/C 3.7mW/C TA 25C POWER RATING 606mW 370mW TA = 70C POWER RATING 388mW 204mW TA = 85C POWER RATING 315mW 148mW EQUIVALENT INPUT CIRCUIT VDD RON 20 ANALOG IN C(SAMPLE) 20pF REF 5k GND Diode Turn-On Voltage: 0.35V Equivalent Analog Input Circuit GND Equivalent Reference Input Circuit GND VDD Shut-Down Switch VDD 20pF I/O Equivalent Digital Input/Output Circuit RECOMMENDED OPERATING CONDITIONS MIN Supply Voltage GND to VDD Low-Voltage Levels 5V Logic Levels 2.7 4.5 2.5 -0.3 0 -40 0 TYP 5.0 MAX 3.6 5.5 VDD 0.5 VREF 125 UNIT V V V V V C Reference Input Voltage Analog Input Voltage -IN +IN - (-IN) Operating Junction Temperature Range, TJ 2 ADS8325 www.ti.com SBAS226A ELECTRICAL CHARACTERISTICS: VDD = +5V Over recommended operating free-air temperature at -40C to +85C, VREF = +5V, -IN = GND, fSAMPLE = 100kHz, and fCLK = 24 * fSAMPLE, unless otherwise noted. ADS8325I PARAMETER ANALOG INPUT Full-Scale Range Operating Common-Mode Signal Input Resistance Input Capacitance Input Leakage Current Differential Input Capacitance Full-Power Bandwith DC ACCURACY Resolution No Missing Code Integral Linearity Error Offset Error Offset Error Drift Gain Error Gain Error Drift Noise Power-Supply Rejection SAMPLING DYNAMICS Conversion Time Acquisition Time Throughout Rate Clock Frequency AC ACCURACY Total Harmonic Distortion Spurious-Free Dynamic Range Signal-to-Noise Ratio Signal-to-Noise + Distortion Effective Number of Bits VOLTAGE REFERENCE INPUT Reference Voltage Reference Input Resistance Reference Input Capacitance Reference Input Current CS = VDD DIGITAL INPUTS(1) Logic Family High-Level Input Voltage Low-Level Input Voltage Input Current Input Capacitance DIGITAL OUTPUTS(1) Logic Family High-Level Output Voltage Low-Level Output Voltage High-Impedance-State Output Current Output Capacitance Load Capacitance Data Format FSR CONDITIONS +IN - (-IN) -IN = GND -IN = GND, During Sampling -IN = GND +IN to -IN, During Sampling fS Sinewave, SINAD at -3dB 16 15 3 0.75 0.2 0.3 20 3 6.667 1.875 0.024 THD SFDR SNR SINAD ENOB 5Vp-p Sinewave, at 1kHz 5Vp-p Sinewave, at 1kHz 5Vp-p Sinewave, at 1kHz -100 -100 -90 -90 14.6 2.5 CS = GND, fSAMPLE = 0Hz CS = VDD 5 5 20 1 0.1 CMOS VIH VIL IIN CI 0.7 * VDD -0.3 VI = VDD or GND 5 CMOS VOH VOL IOZ CO CL VDD = 4.5V, IOH = -100A VDD = 4.5V, IOL = 100A CS = VDD, VI = VDD or GND 4.44 0.5 50 5 30 Straight Binary VDD + 0.3 0.3 * VDD 50 V V nA pF pF VDD + 0.3 V V nA pF 6 1.5 24 666.7 100 2.4 -106 -108 -91 -91 14.7 MIN 0 -0.3 5 45 50 20 20 16 1.5 0.5 4 1 12 TYP MAX VREF 0.5 MIN ADS8325IB TYP MAX UNITS V V G pF nA pF kHz Bits Bits LSB mV ppm/C LSB ppm/C VRMS LSB s s kSPS MHz dB dB dB dB Bits V k G pF mA A FSBW NMC INL VOS TCVOS GERR TCGERR 4.75V VDD 5.25 tCONV tAQ 24kHz < fCLK 2.4MHz fCLK = 2.4MHz 1.5 indicates the same specifications as the ADS8325I. NOTE: (1) Applies for 5.0V nominal supply: VDD (min) = 4.5V and VDD (max) = 5.5V. ADS8325 SBAS226A www.ti.com 3 ELECTRICAL CHARACTERISTICS: VDD = +2.7V Over recommended operating free-air temperature at -40C to +85C, VREF = +2.5V, -IN = GND, fSAMPLE = 100kHz, and fCLK = 24 * fSAMPLE, unless otherwise noted. ADS8325I PARAMETER ANALOG INPUT Full-Scale Range Operating Common-Mode Signal Input Resistance Input Capacitance Input Leakage Current Differential Input Capacitance Full-Power Bandwith DC ACCURACY Resolution No Missing Code Integral Linearity Error Offset Error Offset Error Drift Gain Error Gain Error Drift Noise Power-Supply Rejection SAMPLING DYNAMICS Conversion Time Acquisition Time Throughout Rate Clock Frequency AC ACCURACY Total Harmonic Distortion Spurious-Free Dynamic Range Signal-to-Noise Ratio Signal-to-Noise + Distortion Effective Number of Bits VOLTAGE REFERENCE INPUT Reference Voltage Reference Input Resistance Reference Input Capacitance Reference Input Current CS = VDD DIGITAL INPUTS(1) Logic Family High-Level Input Voltage Low-Level Input Voltage Input Current Input Capacitance DIGITAL OUTPUTS(1) Logic Family High-Level Output Voltage Low-Level Output Voltage High-Impedance-State Output Current Output Capacitance Load Capacitance Data Format FSR CONDITIONS +IN - (-IN) -IN = GND -IN = GND, During Sampling -IN = GND +IN to -IN, During Sampling fS Sinewave, SINAD at -3dB 16 NMC INL VOS TCVOS GERR TCGERR 2.7V VDD 3.6V tCONV tAQ 24kHz < fCLK 2.4MHz fCLK = 2.4MHz 6.667 1.875 0.024 THD SFDR SNR SINAD ENOB 2.5Vp-p Sinewave, at 1kHz 2.5Vp-p Sinewave, at 1kHz 2.5Vp-p Sinewave, at 1kHz -94 -96 -85 -85 13.8 2.5 CS = GND, fSAMPLE = 0Hz CS = VDD 5 5 20 0.5 0.1 LVCMOS VIH VIL IIN CI VDD = 3.6V VDD = 2.7V VI = VDD or GND 2 -0.3 5 LVCMOS VOH VOL IOZ CO CL VDD = 2.7V, IOH = -100A VDD = 2.7V, IOL = 100A CS = VDD, VI = VDD or GND VDD - 0.2 0.2 50 5 30 Straight Binary VDD + 0.3 0.8 50 V V nA pF pF VDD + 0.3 V V nA pF 14 3 0.75 3 33 0.3 20 7 6 1.5 MIN 0 -0.3 5 45 50 20 4 15 1.5 0.5 16 4 1 TYP MAX VREF 0.5 MIN Bits Bits LSB mV ppm/C LSB ppm/C VRMS LSB s s kSPS MHz -86 -85.5 13.9 dB dB dB dB Bits V k G pF mA A ADS8325IB TYP MAX UNITS V V G pF nA pF kHz FSBW 666.7 100 2.4 0.75 indicates the same specifications as the ADS8325I. NOTE: (1) Applies for 3.0V nominal supply: VDD (min) = 2.7V and VDD (max) = 3.6V. 4 ADS8325 www.ti.com SBAS226A ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature at -40C to 85C, VREF = VDD, -IN = GND, fSAMPLE = 100kHz, and fCLK = 24 * fSAMPLE, unless otherwise noted. ADS8325I PARAMETER POWER-SUPPLY REQUIREMENTS Power Supply (VDD) Operating Supply Current (IDD) Power-Down Supply Current (IDD) Power Dissipation Power Dissipation in Power-Down indicates the same specifications as the ADS8325I. CONDITIONS Low-Voltage Levels 5V Logic Levels VDD = 3V VDD = 5V VDD = 3V VDD = 5V VDD = 3V VDD = 5V VDD = 3V, CS = VDD VDD = 5V, CS = VDD MIN 2.7 4.5 0.75 0.9 0.1 0.2 2.25 4.5 0.3 0.6 TYP MAX 3.6 5.5 1.5 1.5 MIN ADS8325IB TYP MAX UNITS V V mA mA A A mW mW W W 4.5 7.5 PIN CONFIGURATION Top View MSOP PIN DESCRIPTIONS NAME REF +IN -IN PIN 1 2 3 4 5 6 7 8 I/O AI AI AI P DI DO DI P DESCRIPTION Reference Input Noninverting Input Inverting Analog Input Ground Chip Select when LOW, Shutdown Mode when HIGH. The serial output data word. Data Clock synchronizes the serial data transfer and determines conversion speed. Power Supply REF +IN -IN GND 1 2 ADS8325 3 4 8 7 6 5 +VDD DCLOCK DOUT CS/SHDN GND CS/SHDN DOUT DCLOCK VDD Top View SON NOTE: AI is Analog Input, DI is Digital Input, DO is Digital Output, and P is Power-Supply Connection. REF +IN -IN GND 1 2 ADS8325 3 4 8 7 6 5 +VDD DCLOCK DOUT CS/SHDN ADS8325 SBAS226A www.ti.com 5 TIMING DIAGRAMS Timing Diagrams and Test Circuits for the Parameters in the Timing Characteristics table. Complete Cycle CS/SHDN tSUCS Sample DCLOCK tCSD DOUT Hi-Z 0 tSMPL B15 B14 B13 B12 B11 B10 B9 B8 (MSB) tCONV B7 B6 B5 B4 B3 B2 B1 B0 (LSB) Use positive clock edge for data transfer Hi-Z Conversion Power Down NOTE: A minimum of 22 clock cycles are required for 16-bit conversion. Shown are 24 clock cycles. If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again. 1.4V 3k DOUT 100pF CLOAD Test Point DOUT tr tf 90% 10% Voltage Waveforms for DOUT Rise and Fall Times, tr, tf Load Circuit for tdDO, tr, and tf Test Point DCLOCK tdDO DOUT thDO Voltage Waveforms for DOUT Delay Times, tdDO DOUT 3k 100pF CLOAD Load Circuit for tdis and ten VCC tdis Waveform 2, ten tdis Waveform 1 CS/SHDN 90% CS/SHDN DCLOCK 1 4 5 DOUT Waveform 1(1) tdis DOUT Waveform 2(2) Voltage Waveforms for tdis 90% 10% DOUT ten Voltage Waveforms for ten B15 NOTES: (1) Waveform 1 is for an output with internal conditions such that the output is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with internal conditions such that the output is LOW unless disabled by the output control. TIMING CHARACTERISTICS SYMBOL tSMPL tCONV tCYC tCSD tSUCS tHDO tDIS tEN tF tR DESCRIPTION Analog Input Sample Time Conversion Time Throughput Rate CS Falling to DCLOCK LOW CS Falling to DCLOCK Rising DCLOCK Falling to Current DOUT Not Valid CS Rising to DOUT Tri-State DCLOCK Falling to DOUT Enabled DOUT Fall Time DOUT Rise Time MIN 4.5 16 100 0 20 5 15 70 20 5 7 TYP MAX 5.0 UNITS Clk Cycles Clk Cycles kHz ns ns ns ns ns ns ns 100 50 25 25 6 ADS8325 www.ti.com SBAS226A TYPICAL CHARACTERISTICS: VDD = +5V At TA = 25C, VDD = +5V, VREF = +5V, fSAMPLE = 100kHz, fCLK = 24 * fSAMPLE, unless otherwise noted. 3 2 1 0 -1 -2 -3 0000H INTEGRAL LINEARITY ERROR vs CODE 3 2 1 DLE(LSBS) DIFFERENTIAL LINEARITY ERROR vs CODE ILE(LSBS) 0 -1 -2 -3 0000H 4000H 8000H Output Code C000H FFFFH 4000H 8000H Output Code C000H FFFFH FREQUENCY SPECTRUM (8192 point FFT, FIN = 1.0132kHz, -0.2dB) 0 -20 -40 0 -20 -40 FREQUENCY SPECTRUM (8192 point FFT, FIN = 10.0022kHz, -0.2dB) Amplitude (dB) -60 -80 -100 -120 -140 -160 0 10 20 30 40 50 Frequency (kHz) Amplitude (dB) -60 -80 -100 -120 -140 -160 0 10 20 30 40 50 Frequency (kHz) 105 100 SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY 110 105 SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY SFDR -110 -105 -100 SNR 100 SNR and SINAD (dB) 95 SFDR (dB) 85 80 SINAD 75 70 65 1 10 Frequency (kHz) 100 245 90 85 80 75 70 1 10 Frequency (kHz) 100 NOTE: (1) First nine harmonics of the input frequency. THD(1) -90 -85 -80 -75 -70 245 ADS8325 SBAS226A www.ti.com THD (dB) 90 95 -95 7 TYPICAL CHARACTERISTICS: VDD = +5V (Cont.) At TA = 25C, VDD = +5V, VREF = +5V, fSAMPLE = 100kHz, fCLK = 24 * fSAMPLE, unless otherwise noted. 100 Signal-to-Noise + Distortion (dB) SIGNAL-TO-NOISE + DISTORTION vs INPUT LEVEL 15.0 EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY 14.5 90 80 70 60 50 40 30 20 10 -80 FIN = 1.0132kHz Effective Number of Bits 14.0 13.5 13.0 12.5 12.0 11.5 11.0 -70 -60 -50 -40 -30 -20 -10 0 1 10 Frequency (kHz) 100 Input Level (dB) 0.4 0.2 CHANGE IN SIGNAL-TO-NOISE + DISTORTION vs TEMPERATURE FIN = 1.0132kHz, -0.2dB 2.0 1.5 Delta from 25C (LSBS) 1.0 0.5 0.0 -0.5 -1.0 -1.5 CHANGE IN GAIN vs TEMPERATURE Delta from 25C (dB) 0.0 -0.2 -0.4 -0.6 -0.8 -50 -25 0 25 50 75 100 Temperature (C) -50 -25 0 25 50 75 100 Temperature (C) 3.0 2.5 Delta from 25C (LSBS) CHANGE IN UPO vs TEMPERATURE 1.1 SUPPLY CURRENT vs TEMPERATURE 1.5 1.0 0.5 0.0 -0.5 -1.0 -50 Supply Current (mA) 2.0 1.0 0.9 0.8 0.7 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (C) Temperature (C) 8 ADS8325 www.ti.com SBAS226A TYPICAL CHARACTERISTICS: VDD = +2.7V At TA = 25C, VDD = 2.7V, VREF = 2.5V, fSAMPLE = 100kHz, fCLK = 24 * fSAMPLE, unless otherwise noted. 3 2 1 INTEGRAL LINEARITY ERROR vs CODE 3 2 1 DLE(LSBS) DIFFERENTIAL LINEARITY ERROR vs CODE ILE(LSBS) 0 -1 -2 -3 0000H 0 -1 -2 -3 0000H 4000H 8000H Output Code C000H FFFFH 4000H 8000H Output Code C000H FFFFH FREQUENCY SPECTRUM (8192 point FFT, FIN = 1.0132kHz, -0.2dB) 0 -20 -40 0 -20 -40 FREQUENCY SPECTRUM (8192 point FFT, FIN = 10.0022kHz, -0.2dB) Amplitude (dB) -60 -80 -100 -120 -140 -160 0 10 20 30 40 50 Frequency (kHz) Amplitude (dB) -60 -80 -100 -120 -140 -160 0 10 20 30 40 50 Frequency (kHz) 95 SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY 100 90 80 SPURIOUS FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY -100 -90 85 SNR SNR and SINAD (dB) SFDR -80 -70 -60 70 60 65 55 SINAD 50 40 NOTE: (1) First nine harmonics of the input frequency. 1 THD(1) -50 -40 45 1 10 Frequency (kHz) 100 245 10 Frequency (kHz) 100 245 ADS8325 SBAS226A www.ti.com 9 THD (dB) 75 SFDR (dB) TYPICAL CHARACTERISTICS: VDD = +2.7V (Cont.) At TA = 25C, VDD = 2.7V, VREF = 2.5V, fSAMPLE = 100kHz, fCLK = 24 * fSAMPLE, unless otherwise noted. 100 SIGNAL-TO-NOISE + DISTORTION vs INPUT LEVEL FIN = 1.0132kHz EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 1 10 Frequency (kHz) 100 Signal-to-Noise + Distortion (dB) 90 80 70 60 50 40 30 20 10 -80 -70 -60 -50 -40 -30 -20 -10 0 Input Level (dB) 0.4 0.2 CHANGE IN SIGNAL-TO-NOISE + DISTORTION vs TEMPERATURE FIN = 1.0132kHz, -0.2dB Delta from 25C (LSBS) Effective Number of Bits 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 CHANGE IN GAIN vs TEMPERATURE Delta from 25C (dB) 0.0 -0.2 -0.4 -0.6 -0.8 -50 -25 0 25 50 75 100 Temperature (C) -50 -25 0 25 50 75 100 Temperature (C) 1.2 CHANGE IN UPO vs TEMPERATURE 0.9 SUPPLY CURRENT vs TEMPERATURE Delta from 25C (LSBS) 0.8 Supply Current (mA) 0.8 0.4 0.0 0.7 -0.4 -0.8 -50 0.6 -25 0 25 50 75 100 -50 -25 0 25 50 75 100 Temperature (C) Temperature (C) 10 ADS8325 www.ti.com SBAS226A THEORY OF OPERATION The ADS8325 is a classic Successive Approximation Register (SAR) Analog-to-Digital (A/D) converter. The architecture is based on capacitive redistribution that inherently includes a sample-andhold function. The converter is fabricated on a 0.6 CMOS process. The architecture and process allow the ADS8325 to acquire and convert an analog signal at up to 100,000 conversions per second while consuming less than 4.5mW from +VDD. The ADS8325 requires an external reference, an external clock, and a single power source (VDD). The external reference can be any voltage between 2.5V and 5.5V. The value of the reference voltage directly sets the range of the analog input. The reference input current depends on the conversion rate of the ADS8325. The external clock can vary between 24kHz (1kHz throughput) and 2.4MHz (100kHz throughput). The duty cycle of the clock is essentially unimportant as long as the minimum high and low times are at least 200ns (VDD = 4.75V or greater). The minimum clock frequency is set by the leakage on the internal capacitors to the ADS8325. The analog input is provided to two input pins: +IN and -IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. The digital result of the conversion is clocked out by the DCLOCK input and is provided serially, most significant bit first, on the DOUT pin. The digital data that is provided on the DOUT pin is for the conversion currently in progress--there is no pipeline delay. It is possible to continue to clock the ADS8325 after the conversion is complete and to obtain the serial data least significant bit first. See the Digital Timing section for more information. The range of the -IN input is limited to -0.3V to +0.5V. Due to this, the differential input could be used to reject signals that are common to both inputs in the specified range. Thus, the -IN input is best used to sense a remote signal ground that may move slightly with respect to the local ground potential. The general method for driving the analog input of the ADS8325 is shown in Figures 1 and 2. The -IN input is held at the common-mode voltage. The +IN input swings from -IN (or common-mode voltage) to -IN + VREF (or commonmode voltage + VREF), and the peak-to-peak amplitude is +VREF. The value of VREF determines the range over which the common-mode voltage may vary (see Figure 3). Figures 5 and 6 illustrate the typical change in gain and offset as a function of the common-mode voltage applied to the -IN pin. 0V to +VREF Peak-to-Peak Common-Mode Voltage ADS8325 FIGURE 2. Methods of Driving the ADS8325 The input current required by the analog inputs depends on a number of factors: sample rate, input voltage, source impedance, and power-down mode. Essentially, the current into the ADS8325 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (20pF) to a 16-bit settling level within 4.5 clock cycles (1.875s). When the converter goes into the hold mode, or while it is in the power-down mode, the input impedance is greater than 1G. ANALOG INPUT The analog input of ADS8325 is differential. The +IN and -IN input pins allow for a differential input signal. The amplitude of the input is the difference between the +IN and -IN input, or (+IN) - (-IN). Unlike some converters of this type, the -IN input is not resampled later in the conversion cycle. When the converter goes into the hold mode or conversion, the voltage difference between +IN and -IN is captured on the internal capacitor array. Common-Mode Voltage + VREF +VREF +IN Common-Mode Voltage -IN = Common-Mode Voltage NOTE: The maximum differential voltage between +IN and -IN of the ADS8325 is VREF. See Figure 3 for a further explanation of the common-mode voltage range for differential inputs. t FIGURE 1. Differential Input Mode of the ADS8325. ADS8325 SBAS226A www.ti.com 11 CHANGE IN GAIN vs COMMON-MODE VOLTAGE 60 Delta Relative to VCM = 0V (LSBS) Common Voltage Range (V) 1 VDD = 5V 0.5 0 -0.3 50 40 30 20 10 0 VDD = 5V VREF = 4V -1 2 2.5 3 4 VREF (V) 4.8 5 6 -10 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 VCM (V) FIGURE 3. +IN Analog Input: Common-Mode Voltage Range vs VREF. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the -IN input should not drop below GND - 0.3V or exceed GND + 0.5V. The +IN input should always remain within the range of GND - 0.3V to VDD + 0.3V, or -IN to -IN + VREF, whichever limit is reached first. Outside of these ranges, the converter's linearity may not meet specifications. To minimize noise, low bandwidth input signals with lowpass filters should be used. In each case, care should be taken to ensure that the output impedance of the sources driving the +IN and -IN inputs are matched. Often, a small capacitor (20pF) between the positive and negative inputs helps to match their impedance. To obtain maximum performance from the ADS8325, the input circuit from Figure 4 is recommended. FIGURE 5. Change in Gain vs Common-Mode Voltage. CHANGE IN UPO vs COMMON-MODE VOLTAGE 30 Delta Relative to VCM = 0V (LSBS) VDD = 5V VREF = 4V 20 10 0 -10 -20 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 VCM (V) FIGURE 6. Change in Unipolar Offset vs Common-Mode Voltage. 50 OPA340 100pF +IN 20 20pF OPA340 50 +IN 100pF 20 20pF ADS8325 1nF ADS8325 -IN 20 20pF OPA340 50 -IN 100pF 20 20pF Single-Ended Differential FIGURE 4. Single-Ended and Differential Methods of Interfacing the ADS8325. 12 ADS8325 www.ti.com SBAS226A REFERENCE INPUT The external reference sets the analog input range. The ADS8325 will operate with a reference in the range of 2.5V to VDD. There are several important implications to this. As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is often referred to as the Least Significant Bit (LSB) size and is equal to the reference voltage divided by 65,536. This means that any offset or gain error inherent in the A/D converter will appear to increase, in terms of LSB size, as the reference voltage is reduced. For a reference voltage of 2.5V, the value of LSB is 38.15V, and for reference voltage of 5V, the LSB is 76.3V. The noise inherent in the converter will also appear to increase with lower LSB size. With a 5V reference, the internal noise of the converter typically contributes only 1.5LSBs peak-to-peak of potential error to the output code. When the external reference is 2.5V, the potential error contribution from the internal noise will be 2 times larger (3LSBs). The errors due to the internal noise are Gaussian in nature and can be reduced by averaging consecutive conversion results. For more information regarding noise, consult the typical characteristic "Peak-to-Peak Noise vs Reference Voltage." Note that the Effective Number Of Bits (ENOB) figure is calculated based on the converter's signal-to-(noise + distortion) ratio with a 1kHz, 0dB input signal. SINAD is related to ENOB as follows: SINAD = 6.02 * ENOB + 1.76 As the difference between the power-supply voltage and reference voltage increases, the gain and offset performance of the converter will decrease. Figure 7 shows the typical change in gain and offset as a function of the difference between the power-supply voltage and reference voltage. For the combination of VDD = 2.7V and VREF = 2.5V, or VDD = 5V and VREF = 5V, offset and gain error will be minimal. The most dramatic difference in offset can be seen when VDD = 5V and VREF = 2.5V. With lower reference voltages, extra care should be taken to provide a clean layout including adequate bypassing, a clean power supply, a low-noise reference, and a low-noise input signal. Due to the lower LSB size, the converter will also be more sensitive to external sources of error, such as nearby digital signals and electromagnetic interference. The equivalent input circuit for the reference voltage is presented in the Figure 8. The 5k resistor presents a constant load during the conversion process. At the same time, an equivalent capacitor of 20pF is switched. To obtain optimum performance from the ADS8325, special care must be taken in designing the interface circuit to the reference input pin. To ensure a stable reference voltage, a 47F tantalum capacitor with low ESR should be connected as close as possible to the input pin. If a high output impedance reference source is used, an additional operational amplifier with a current limiting resistor must be placed in front of the capacitors. ADS8325 100 OPA340 47F VREF 5k 20pF FIGURE 8. Input Reference Circuit and its Interface. When the ADS8325 is in power-down mode, the input resistance of the reference pin will have a value of 5G. Since the input capacitors must be recharged before the next conversion starts, an operational amplifier with good dynamic characteristics must be used to buffer the reference input. NOISE The transition noise of the ADS8325 itself is extremely low (see Figures 9 and 10); it is much lower than competing A/D converters. These histograms were generated by applying a low-noise DC input and initiating 5000 conversions. The digital output of the A/D converter will vary in output code due to the internal noise of the ADS8325. This is true for all 16-bit, SARtype A/D converters. Using a histogram to plot the output codes, the distribution should appear bell-shaped with the peak of the bell curve representing the nominal code for the input value. The 1, 2, and 3 distributions will represent the 68.3%, 95.5%, and 99.7%, respectively, of all codes. The transition noise can be calculated by dividing the number of codes measured by 6 and this will yield the 3 distribution, or 99.7%, of all codes. Statistically, up to three codes could fall outside the distribution when executing 1000 conversions. The ADS8325, with < 3 output codes for the 3 distribution, will yield a < 0.5LSBs of transition noise. Remember, to achieve this low-noise performance, the peak-to-peak noise of the input signal and reference must be < 50V. CHANGE IN OFFSET AND GAIN vs SUPPLY/REFERENCE DIFFERENTIAL 3.0 2.5 2.0 Delta (mV) 1.5 1.0 Offset Gain 0.5 0 -0.5 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 VDD to VREF (V) FIGURE 7. Change in Offset and Gain versus the Difference between Power-Supply and Reference Voltage. ADS8325 SBAS226A www.ti.com 13 4005 VDD = 5.0V VREF = 5.0V DIGITAL INTERFACE SIGNAL LEVELS The ADS8325 has a wide range of power-supply voltage. The A/D converter, as well as the digital interface circuit, is designed to accept and operate from 2.7V up to 5.5V. This voltage range will accommodate different logic levels. When the ADS8325's power-supply voltage is in the range of 4.5V to 5.5V (5V logic level), the ADS8325 can be connected directly to another 5V CMOS integrated circuit. 519 0 7FFD 7FFE 7FFF Code 476 0 8000 8001 Another possibility is that the ADS8325's power-supply voltage is in the range of 2.7V to 3.6V. The ADS8325 can be connected directly to another 3.3V LVCMOS integrated circuit. FIGURE 9. 5000 Conversion Histogram of a DC Input. SERIAL INTERFACE The ADS8325 communicates with microprocessors and other digital systems via a synchronous 3-wire serial interface, as illustrated in the Timing Diagram and Timing Characteristics table. The DCLOCK signal synchronizes the data transfer with each bit being transmitted on the falling edge of DCLOCK. Most receiving systems will capture the bitstream on the rising edge of DCLOCK. However, if the minimum hold time for DOUT is acceptable, the system can use the falling edge of DCLOCK to capture each bit. A falling CS signal initiates the conversion and data transfer. The first 4.5 to 5.0 clock periods of the conversion cycle are used to sample the input signal. After the fifth falling DCLOCK edge, DOUT is enabled and will output a LOW value for one clock period. For the next 16 DCLOCK periods, DOUT will output the conversion result, most significant bit first. After the least significant bit (B0) has been output, subsequent clocks will repeat the output data, but in a least significant bit first format. After the most significant bit (B15) has been repeated, DOUT will tri-state. Subsequent clocks will have no effect on the converter. A new conversion is initiated only when CS has been taken HIGH and returned LOW. VDD = 2.7V VREF = 2.5V 3499 649 90 7FFD 7FFE 7FFF Code 683 79 8000 8001 FIGURE 10. 5000 Conversion Histogram of a DC Input. AVERAGING The noise of the A/D converter can be compensated by averaging the digital codes. By averaging conversion results, transition noise will be reduced by a factor of 1/ n , where n is the number of averages. For example, averaging four conversion results will reduce the transition noise from 0.5LSB to 0.25LSB. Averaging should only be used for input signals with frequencies near DC. For AC signals, a digital filter can be used to low-pass filter and decimate the output codes. This works in a similar manner to averaging; for every decimation by 2, the signalto-noise ratio will improve 3dB. DATA FORMAT The output data from the ADS8325 is in Straight Binary format (see Figure 11). This figure represents the ideal output code for a given input voltage and does not include the effects of offset, gain error, or noise. 14 ADS8325 www.ti.com SBAS226A Straight Binary 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 65535 65534 65533 Digital Output Code 1000 0000 0000 0001 1000 0000 0000 0000 0111 1111 1111 1111 32769 32768 32767 0000 0000 0000 0010 2 0000 0000 0000 0001 1 0 0000 0000 0000 0000 VZ = VCM = 0V 38.15V 2.499962V 2.500038V VFS = VCM + VREF = 5V VFS - 1LSB = 4.999924V VMS = VCM + VREF/2 = 2.5V 76.29V 152.58V 16-BIT Zero Code Midscale Code Full-Scale Code Straight Binary Output VZ = 0000H VMS = 8000H VFS = 7FFFH Unipolar Analog Input VCODE = VCM VCODE = VCM + VREF/2 VCODE = (VCM + VREF) - 1LSB Unipolar Analog Input Voltage 4.999847V 1LSB = 76.29V VCM = 0V VREF = 5V FIGURE 11. Ideal Conversion Characteristics (Condition: VCM = 0V, VREF = 5V). POWER DISSIPATION The architecture of the converter, the semiconductor fabrication process, and a careful design, allow the ADS8325 to convert at up to a 100kHz rate while requiring very little power. However, for the absolute lowest power dissipation, there are several things to keep in mind. The power dissipation of the ADS8325 scales directly with conversion rate. Therefore, the first step to achieving the lowest power dissipation is to find the lowest conversion rate that will satisfy the requirements of the system. In addition, the ADS8325 is in power-down mode under two conditions: when the conversion is complete and whenever CS is HIGH (see Timing Diagram). Ideally, each conversion should occur as quickly as possible, preferably at a 2.4MHz clock rate. This way, the converter spends the longest possible time in the power-down mode. This is very important as the converter not only uses power on each DCLOCK transition (as is typical for digital CMOS components), but also uses some current for the analog circuitry, such as the comparator. The analog section dissipates power continuously until the power-down mode is entered. See Figures 12 and 13 for the current consumption of the ADS8325 versus sample rate. For these graphs, the converter is clocked at 2.4MHz regardless of the sample rate. CS is held HIGH during the remaining sample period. There is an important distinction between the power-down mode that is entered after a conversion is complete and the full power-down mode that is enabled when CS is HIGH. CS LOW will shutdown only the analog section. The digital section is completely shutdown only when CS is HIGH. Thus, if CS is left LOW at the end of a conversion, and the converter is continually clocked, the power consumption will not be as low as when CS is HIGH. ADS8325 SBAS226A Step www.ti.com 15 POWER SUPPLY AND REFERENCE CURRENT vs SAMPLE RATE 1000 TA = 25C VDD = 5.0V VREF = 5.0V FCLK = 2.4MHz Current (A) LAYOUT For optimum performance, care should be taken with the physical layout of the ADS8325 circuitry. This will be particularly true if the reference voltage is low and/or the conversion rate is high. At a 100kHz conversion rate, the ADS8325 makes a bit decision every 416ns. That is, for each subsequent bit decision, the digital output must be updated with the results of the last bit decision, the capacitor array appropriately switched and charged, and the input to the comparator settled to a 16-bit level all within one clock cycle. The basic SAR architecture is sensitive to spikes on the power supply, reference, and ground connections that occur just prior to latching the comparator output. Thus, during any single conversion for an n-bit SAR converter, there are n "windows" in which large external transient voltages can easily affect the conversion result. Such spikes might originate from switching power supplies, digital logic, and high-power devices, to name a few. This particular source of error can be very difficult to track down if the glitch is almost synchronous to the converter's DCLOCK signal as the phase difference between the two changes with time and temperature, causing sporadic misoperation. With this in mind, power to the ADS8325 should be clean and well bypassed. A 0.1F ceramic bypass capacitor should be placed as close as possible to the ADS8325 package. In addition, a 1F to 10F capacitor and a 5 or 10 series resistor may be used to low-pass filter a noisy supply. The reference should be similarly bypassed with a 47F capacitor. Again, a series resistor and large capacitor can be used to low-pass filter the reference voltage. If the reference voltage originates from an op amp, make sure that the op amp can drive the bypass capacitor without oscillation (the series resistor can help in this case). Keep in mind that while the ADS8325 draws very little current from the reference on average, there are still instantaneous current demands placed on the external input and reference circuitry. Texas Instrument's OPA627 op amp provides optimum performance for buffering both the signal and reference inputs. For low-cost, low-voltage, single-supply applications, the OPA2350 or OPA2340 dual op amps are recommended. Also, keep in mind that the ADS8325 offers no inherent rejection of noise or voltage variation in regards to the reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. While high-frequency noise can be filtered out as described in the previous paragraph, voltage variation due to the line frequency (50Hz or 60Hz) can be difficult to remove. The GND pin on the ADS8325 should be placed on a clean ground point. In many cases, this will be the "analog" ground. Avoid connecting the GND pin too close to the grounding point for a microprocessor, microcontroller, or digital signal processor. If needed, run a ground trace directly from the converter to the power-supply connection point. The ideal layout will include an analog ground plane for the converter and associated analog circuitry. IDD 100 IREF 10 1 10 Sample Rate (kHz) 100 FIGURE 12. Power-Supply and Reference Current vs Sample Rate at VDD = 5V. POWER SUPPLY AND REFERENCE CURRENT vs SAMPLE RATE 1000 TA = 25C VDD = 2.7V VREF = 2.5V FCLK = 2.4MHz Current (A) IDD 100 IREF 10 1 10 Sample Rate (kHz) 100 FIGURE 13. Power-Supply and Reference Current vs Sample Rate at VDD = 2.7V. SHORT CYCLING Another way to save power is to utilize the CS signal to short cycle the conversion. Due to the ADS8325 placing the latest data bit on the DOUT line as it is generated, the converter can easily be short cycled. This term means that the conversion can be terminated at any time. For example, if only 14 bits of the conversion result are needed, then the conversion can be terminated (by pulling CS HIGH ) after the 14th bit has been clocked out. This technique can be used to lower the power dissipation (or to increase the conversion rate) in those applications where an analog signal is being monitored until some condition becomes true. For example, if the signal is outside a predetermined range, the full 16-bit conversion result may not be needed. If so, the conversion can be terminated after the first n bits, where n might be as low as 3 or 4. This results in lower power dissipation in both the converter and the rest of the system as they spend more time in power-down mode. 16 ADS8325 www.ti.com SBAS226A APPLICATION CIRCUITS Figure 14 shows a basic data acquisition system. The ADS8325 input range is connected to 2.5V or 4.096V. The 5 resistor and 1F to 10F capacitor filters the microcon- troller "noise" on the supply, as well as any high-frequency noise from the supply itself. The exact values should be picked such that the filter provides adequate rejection of noise. Operational amplifiers and voltage reference are connected to analog power supply, AVDD. DVDD 2.7V to 3.6V 0.1F AVDD 2.7V to 5V REF3025 IN 0.47F OUT GND 100 OPA340 47F ADS8325 DSP 50 OPA340 VCM + (0V to 2.5V) 100pF 1nF 50 OPA340 VCM 100pF -IN +IN CS DOUT DCLOCK GND GND TMS320C6xx or TMS320C5xx or TMS320C2xx REF VDD 0.1F + 10F 5 + 10F DVDD 4.5V to 5.5V 0.1F AVDD 4.3V to 5.5V REF3040 IN 0.47F OUT GND 100 OPA340 47F ADS8325 Microcontroller or DSP +IN 100pF CS DOUT DCLOCK -IN GND GND REF VDD 0.1F + 10F 5 + 10F 50 OPA340 0V to 4.096V FIGURE 14. Two Examples of a Basic Data Acquisition System. ADS8325 SBAS226A www.ti.com 17 PACKAGE DRAWING DGK (R-PDSO-G8) 0,38 0,25 8 5 PLASTIC SMALL-OUTLINE PACKAGE 0,65 0,08 M 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 3,05 2,95 4 0- 6 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073329/C 08/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-187 18 ADS8325 www.ti.com SBAS226A PACKAGE DRAWING (Cont.) ADS8325 SBAS226A www.ti.com 19 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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