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ADS8364
ADS 836
(R)
4
SBAS219 - JUNE 2002
250kHz, 16-Bit, 6-Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTERS
FEATURES
q q q q q q q q 6 INPUT CHANNELS FULLY DIFFERENTIAL INPUTS 6 INDEPENDENT 16-BIT ADC 4s TOTAL THROUGHPUT PER CHANNEL TESTED NO MISSING CODES TO 14 BITS BUFFERED REFERENCE INPUTS LOW POWER: 450mW TQFP-64 PACKAGE
DESCRIPTION
The ADS8364 includes six, 16-bit, 250KHz ADCs (Analog to Digital Converters) with 6 fully differential input channels grouped into two pairs for high-speed simultaneous signal acquisition. Inputs to the sample-and-hold amplifiers are fully differential and are maintained differential to the input of the ADC. This provides excellent common-mode rejection of 80dB at 50KHz that is important in high-noise environments. The ADS8364 offers a flexible high-speed parallel interface with a direct address mode, a cycle, and a FIFO mode. The output data for each channel is available as a 16-bit word.
APPLICATIONS
q MOTOR CONTROL q MULTI-AXIS POSITIONING SYSTEMS q 3-PHASE POWER CONTROL
CH A0+ CH A0- S/H Amp CDAC Comp
SAR HOLDA
CH A1+ CH A1- S/H Amp
CDAC Comp
Interface
A0 A1 A2 ADD RD WR CS FD EOC CLK
Conversion and Control CH B0+ CH B0- S/H Amp CDAC Comp
SAR HOLDB FIFO Register 6x CDAC S/H Amp Comp 16
RESET BYTE
CH B1+ CH B1-
Data Input/Output
CH C0+ CH C0- S/H Amp
CDAC Comp
SAR
HOLDC CH C1+ CH C1- S/H Amp REFIN REFOUT Internal 2.5V Reference Comp
CDAC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2002, Texas Instruments Incorporated
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings over operating free-air temperature (unless otherwise noted)(1) Supply Voltage, AGND to AVDD ............................................................... -0.3V to 6V Supply Voltage, BGND to BVDD ............................................................... -0.3V to 6V Supply Voltage, DGND to DVDD .............................................................. -0.3V to 6V Analog Input Voltage Range ..................... AGND - 0.3V to AVDD + 0.3V Reference Input Voltage ........................... AGND - 0.3V to AVDD + 0.3V Digital Input Voltage Range ...................... BGND - 0.3V to BVDD + 0.3V Ground Voltage Differences, AGND to BGND/DGND ..................... 0.3V Voltage Differences, BVDD, DVDD to AGND .......................... -0.3V to 6V Input Current ot Any Pin Except Supply ......................... -20mA to 20mA Power Dissipation ....................................... See Dissipation Rating Table Operating Virtual Junction Temperature Range, TJ ........ -40C to 150C Operating Free-Air Temperature Range, TA ...................... -40C to 85C Storage Temperature Range, TSTG .................................. -65C to 150C Lead Temperature 1.6mm (1/16 inch) from Case for 10sec ..................... 260C NOTE: (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions of extended periods may affect device reliability.
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
MAXIMUM INTEGRAL LINEARITY ERROR (LSB) 8 NO MISSING CODES ERROR (LSB) 14 SPECIFIED TEMPERATURE RANGE -40C to +85C
PRODUCT ADS8364Y
PACKAGE-LEAD TQFP-64
PACKAGE DESIGNATOR(1) PAG
ORDERING NUMBER (2)
TRANSPORT MEDIA, QUANTITY
"
"
"
"
"
"
ADS8364Y/250 Tape and Reel, 250 ADS8364Y/2K Tape and Reel, 2000
NOTES: (1) For the most current specifications and package information, refer to our website at www.ti.com (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of "ADS8364Y/2K" will get a single 2000-piece Tape and Reel.
PACKAGE DISSIPATION RATING TABLE
DERATING FACTOR ABOVE TA = 25C 14.598mW/C 23.364mw/C TA 25C POWER RATING 1824mW 2920mW TA = 70C POWER RATING 1168mW 1869mW TA = 85C POWER RATING 949mW 1519mW
BOARD Low-K(1) High-K(2)
PACKAGE DGK DGK
RJC 8.6C/W 8.6C/W
RJA 68.5C/W 42.8C/W
NOTES: (1) The JEDEC Low K (1s) board design used to derive this data was a 3 inch x 3 inch, two layer board with 2-ounce copper traces on top of the board. (2) The JEDEC High K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1-ounce internal power and ground planes and 2 ounce copper traces on top and bottom of the board. RECOMMENDED OPERATING CONDITIONS Supply Voltage, AGND to AVDD Supply Voltage, BGND to BVDD Supply Voltage, DGND to DVDD Difference AVDD to DVDD Reference Input Voltage Operating Common-Mode Signal Analog Inputs Operating Junction Temperature Range, TJ Low-Voltage Levels 5V Logic Levels MIN 4.75 2.7 4.5 4.75 -0.3 1.5 2.2 0 -40 NOM 5 5 5 0 2.5 2.5 MAX 5.25 3.6 5.5 5.25 0.3 2.6 2.8 VREF 125 UNIT V V V V V V V V C
-IN +IN - (-IN)
EQUIVALENT INPUT CIRCUIT
AVDD RON = 20 AIN C(SAMPLE) = 20pF DIN BVDD Diode Turn-on Voltage: 0.35V
AGND Equivalent Analog Input Circuit
BGND Equivalent Digital Input Circuit
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ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range at -40C to 85C, AVDD = DVDD = 5V, BVDD = 3V, VREF = internal +2.5V, fCLK = 5MHz, fSAMPLE = 250kSPS, unless otherwise noted. ADS8364Y PARAMETER ANALOG INPUT Full-Scale Range Operating Common-Mode Signal Input Resistance Input Capacitance Input Leakage Current Differential Input Resistance Differential Input Capacitance Common-Mode Rejection Ratio Bandwith DC ACCURACY Relsolution No Missing Codes Integral Linearity Error Integral Linearity Match Differential Nonlinearity Bipolar Offset Error Bipolar Offset Error Match Bipolar Offset Error Drift Gain Error Gain Error Match Gain Error Drift Noise Power-Supply Rejection Ratio SAMPLING DYNAMICS Conversion Time per ADC Acquisition Time Throughout Rate Aperture Delay Aperture Delay Matching Aperture Jitter Clock Frequncy AC ACCURACY Total Harmonic Distortion Spurous-Free Dynamic Range Signal-to-Noise Ratio Signal-to-Noise Ratio + Distortion Channel-to-Channel Isolation Effective Number of Bits VOLTAGE REFERENCE OUTPUT Reference Voltage Output Initial Accuracy Output Voltage Temperature Drift Output Voltage Noise Power-Supply Refection Ratio Output Current Short-Circuit Current Turn-On Settling Time VOLTAGE REFERENCE INPUT Reference Voltage Input Reference Input Resistance Reference Input Capacitance Reference Input Current NOTE: (1) All values are at TA = 25C. (FSR) CONDITIONS +IN - (-IN) 2.2 -IN = VREF -IN = VREF -IN = VREF -IN = VREF -IN = VREF At DC VIN = 1.25Vp-p at 50kHz FS Sinewave, -3dB 16 14 Only Pair Wise Matching Specified only for 14-Bit Only Pair Wise Matching (TCVOS) (GERR) (TCGERR) (PSRR) (tCONV) (tAQ) 4.75V < AVDD < 5.25V 50kHz fCLK 5MHz fCLK = 5MHz 3.2 800 Referenced to VREF Only Pair Wise Matching 3 1.5 1.5 0.05 0.2 0.8 0.05 0.005 2 120 -87 8 20 25 1 40 50 84 80 300 MIN TYP(1) MAX VREF 2.8 UNITS V V pF nA pF dB dB MHz Bits Bits LSB LSB LSB mV mV ppm/C %FSR %FSR ppm/C VRMS dB s ns kSPS ns ps ps MHz dB dB dB dB dB Bits 2.525 1 V % ppm/C Vp-p VRMS dB A mA s V M pF A
(CMRR) (BW)
(NMC) (INL) (DNL) (VOS)
2 1 0.25 0.05
320 250 5 100 50
0.05 (THD) (SFDR) (SNR) (SINAD) (ENOB) (VOUT) (dVOUT/dT) f = 0.1Hz to 10Hz, CL = 10F f = 10Hz to 10kHz, CL = 10F (PSRR) (IOUT) (ISC) to 0.1% at CL = 0 (VIN) 1.5 100 2.475 VIN = 2.5Vp-p at 100kHz VIN = 2.5Vp-p at 100kHz VIN = 2.5Vp-p at 100kHz VIN = 2.5Vp-p at 100kHz VIN = 2.5Vp-p at 50kHz -92 93.5 83.2 82.5 95 13.3 2.5 20 40 8 60 10 0.5 100 2.5 5
5
2.6
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ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range at -40C to 85C, AVDD = DVDD = 5V, VREF = internal +2.5V, fCLK = 5MHz, fSAMPLE = 250kSPS, unless otherwise noted. ADS8364Y PARAMETER DIGITAL Logic Family High-Level Input Voltage Low-Level Input Voltage Input Current Input Capacitance DIGITAL OUTPUTS(2) Logic Family High-Level Output Voltage Low-Level Output Voltage High-Impedance-State Output Current Output Capacitance Load Capacitance Data Format DIGITAL INPUTS(3) Logic Family High-Level Input Voltage Low-Level Input Voltage Input Current Input Capacitance DIGITAL OUTPUTS(3) Logic Family High-Level Output Voltage Low-Level Output Voltage High-Impedance-State Output Current Output Capacitance Load Capacitance Data Format POWER SUPPLY Analog Supply Voltage Buffer I/O Supply Current Digital Supply Voltage Analog Operating Supply Current Buffer I/O Operating Supply Current Digital Operating Supply Current Power Dissipation INPUTS(2) CONDITIONS MIN TYP(1) CMOS (VIH) (VIL) (IIN) (CI) 0.7 * BVDD -0.3 VI = BVDD or GND 5 CMOS (VOH) (VOL) (IOZ) (CO) (CL) BVDD = 4.5V, IOH = -100A BVDD = 4.5V, IOL = 100A CS = BVDD, VI = BVDD or GND 4.44 0.5 50 5 30 Binary Two's Complement LVCMOS (VIH) (VIL) (IIN) (CI) BVDD = 3.6V BVDD = 2.7V VI = BVDD or GND 2 -0.3 5 LVCMOS (VOH) (VOL) (IOZ) (CO) (CL) BVDD = 2.7V, IOH = -100A BVDD = 2.7V, IOL = 100A CS = BVDD, VI = BVDD or GND BVDD - 0.2 0.2 50 5 30 Binary Two's Complement (AVDD) (BVDD) (DVDD) (AIDD) (BIDD) (DIDD) BVDD = 3V BVDD = 5V 4.75 2.7 4.5 4.75 80 BVDD = 3V BVDD = 5V 200 2.5 413.1 413.5 5.25 3.6 5.5 5.25 90 300 300 4 470.9 471.5 V V V V mA A A mA mW mW V V nA pF pF BVDD + 0.3 0.8 50 V V nA pF V V nA pF pF BVDD + 0.3 0.3 * BVDD 50 V V nA pF MAX UNITS
Low-Voltage Levels 5V Logic Levels
NOTES: (1) All values are at TA = 25C. (2) Applies for 5.0V nominal Supply: BVDD (min) = 4.5V and BVDD (max) = 5.5V. (3) Applies for 3.0V nominal Supply: BVDD (min) = 2.7V and BVDD (max) = 3.6V.
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PIN CONFIGURATION
HOLD C
HOLD B
HOLD A
CH A0+
REFOUT
CH A0-
RESET
AGND
64 CH A1- CH A1+ AVDD AGND SGND CH B0+ CH B0- AVDD AGND 1 2 3 4 5 6 7 8 9
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49 48 D0 47 D1 46 D2 45 D3 44 D4 43 D5 42 D6 41 D7
ADS8364
BGND
REFIN
AVDD
BVDD
ADD
A0
A1
A2
40 D8 39 D9 38 D10 37 D11 36 D12 35 D13 34 D14 33 D15
SGND 10 CH B1- 11 CH B1+ 12 AVDD 13 AGND 14 SGND 15 CH C0+ 16 17
CH C0-
18
CH C1-
19
CH C1+
20
NC
21
DGND
22
DVDD
23
BYTE
24
BVDD
25
BGND
26
FD
27
EOC
28
CLK
29
RD
30
WR
31
CS
32
BGND
PIN DESCRIPTIONS
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME I/O DESCRIPTION PIN 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NAME BGND DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BGND BVDD RESET ADD A2 A1 A0 HOLDA HOLDB HOLDC AVDD AGND REFOUT REFIN CH A0+ CH A0- I/O P DO DO DO DO DO DO DO DO DIO DIO DIO DIO DIO DIO DIO DIO P P DI DI DI DI DI DI DI DI P P AO AI AI AI DESCRIPTION Buffer Digital Ground Data Bit 15-MSB Data Bit 14 Data Bit 13 Data Bit 12 Data Bit 11 Data Bit 10 Data Bit 9 Data Bit 8 Data Bit 7, Software Input 7 Data Bit 6, Software Input 6 Data Bit 5, Software Input 5 Data Bit 4, Software Input 4 Data Bit 3, Software Input 3 Data Bit 2, Software Input 2 Data Bit 1, Software Input 1 Data Bit 0, Software Input 0 Buffer Digital Ground Power Supply for Digital interface from 3V to 5V Global Reset, Active LOW Address Mode Select Address Line 3 Address Line 2 Address Line 1 Hold Command A Hold Command B Hold Command C Analog Power Supply Analog Ground Reference Output, attach a 0.1F and 10F capacitors. Reference Input Noninverting Input Channel A0 Inverting Input Channel A0 CH A1- AI Inverting Input Channel A1 CH A1+ AI Noninverting Input channel A1 AVDD P Analog Power Supply AGND P Analog Ground SGND P Signal Ground CH B0+ AI Noninverting Input Channel B0 CH B0- AI Inverting Input Channel B0 AVDD P Analog Power Supply AGND P Analog Ground SGND P Signal Ground CH B1- AI Inverting Input Channel B1 CH B1+ AI Noninverting Input Channel B1 AVDD P Analog Power Supply AGND P Analog Ground SGND P Signal Ground CH C0+ AI Noninverting Input Channel C0 CH C0- AI Inverting Input Channel C0 CH C1- AI Inverting Input Channel C1 CH C1+ AI Noninverting Input Channel C1 NC - No Connection DGND P Digital ground connected to AGND. DVDD P +5V Power Supply for Digital Logic Connected to AVDD. BYTE DI 2 x 8 Output Capability. Active HIGH. BVDD P Power supply for digital interface from 3V to 5V. BGND P Buffer Digital Ground FD DO First Data, A0 Data EOC DO End of Conversion, Active LOW CLK DI An external CMOS compatible clock can be applied to the CLK input to synchronize the conversion process to an external source. RD DI Read, Active LOW WR DI Write, Active LOW CS DI Chip Select, Active LOW
29 30 31
NOTE: AI is Analog Input, AO is Analog Output, DI is Digital Input, DO is Digital Output, DIO is Digital Input/Output, P is Power-Supply Connection.
ADS8364
SBAS219
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TIMING CHARACTERISTICS
tC1 CLK tW1 tD1 1 2 CONVERSION tCONV 16 17 18 19 20 1 2
ACQUISITION tACQ
HOLDX tW3 EOC tW2
CS tD4 RD tW5 tD6 D15-D8 Bits 15-8 tD7 Bits 15-8 tW6 tD5
D7-D0
Bits 7-0
Bits 7-0
BYTE
TIMING CHARACTERISTICS TABLE
Timing Characteristics over recommended operating free-air temperature range TMIN to TMAX, AVDD = DVDD = 5V, REFIN = REFOUT internal reference +2.5V. fCLK = 5MHz, fSAMPLE = 250kHz, BVDD = 2.7 / 5V (unless otherwise noted). SPEC tCONV tACQ tC1 tW1 tD1(5) tW2 tW3 tW4 tW5 tD2 tD4 tD5 tW6 tW7 tD6 tD7 tD8 tD9 DESCRIPTION Conversion Time Acquistion Time Cycle Time of CLK Pulse Width CLK HIGH Time or LOW Time. Delay Time of Rising Edge of Clock After Falling Edge of HOLD (A,B,C) Pulse Width of HOLDX HIGH Time to be Recognized again Pulse Width of HOLDX LOW Time Pulse Width of RESET Pulse Width of RD HIGH Time Delay Time of First Hold After RESET Delay Time of Falling Edge of RD After Falling Edge of CS Delay Time of Rising Edge of CS After Rising Edge of RD Pulse Width of RD and CS Both LOW Time Pulse Width of RD HIGH Time Delay Time of Data Valid After Falling Edge RD Delay Time of Data Hold From Rising Edge of RD Delay Time of RD HIGH After CS LOW Delay Time of RD Low After Address Setup MIN TYP(1) MAX 3.2 0.8 200 60 10 15 30 20 30 20 40 30 40 20 40 0 0 50 70 20 40 40 60 5 10 50 60 10 20 UNITS s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD
= = = = = = = = = =
5V 3V 5V 3V 5V 3V 5V 3V 5V 3V
BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD
= = = = = = = = = = = =
5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V
NOTES: (1) Assured by design. (2) All input signals are specified with tr = tf = 5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2. (3) See timing diagram above. (4) BYTE is asynchronous; when BYTE is 0, bits 15 through 0 appear at DB15-DB0. When BYTE is 1, bits 15 through 8 appear on DB7-DB0. RD may remain LOW between changes in BYTE. (5) Only important when synchronization to clock is important.
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TYPICAL CHARACTERISTICS
At TA = +25C, AVDD = DVDD = +5V, BVDD = 3V VREF = internal +2.5V and fCLK = 5MHz, fSAMPLE = 250kHz, unless otherwise noted.
5 4 3 2
INTEGRAL LINEARITY ERROR vs CODE Typical curve for all six channels
3 2 1
DIFFERENTIAL LINEARITY ERROR vs CODE Typical curve for all six channels.
INL (LSB)
1 0 -1 -2 -3 -4 -5 0000H 4000H 8000H Output Code C000H FFFFH
DNL (LSB)
0 -1 -2 -3 0000H
4000H
8000H Output Code
C000H
FFFFH
4
Minimum and Maximum INL (LSB)
MINIMUM AND MAXIMUM INL OF ALL CHANNELS vs TEMPERATURE
Minimum and Maximum DNL (LSB)
3 2 1 0 -1 -2 -3
MINIMUM AND MAXIMUM DNL OF ALL CHANNELS vs TEMPERATURE
3 2 1 0 -1 -2 -3 -50 -25 0 25 Temperature (C) 50 75 100
-50
-25
0
25 Temperature (C)
50
75
100
3.0 2.0
INTEGRAL LINEARITY MATCH OF CHANNELS A0 AND A1 vs CODE
FREQUENCY SPECTRUM (4096 point FFT, FIN = 100kHz, -0.2dB) 0 -20 -40
INL Match (LSB)
1.0 0.0 -1.0 -2.0 -3.0 0000H
Amplitude (dB)
-60 -80 -100 -120 -140 -160
4000H
8000H Output Code
C000H
FFFFH
0
31
62 Frequency (kHz)
93
125
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TYPICAL CHARACTERISTICS (Cont.)
At TA = +25C, AVDD = DVDD = +5V, BVDD = 3V VREF = internal +2.5V and fCLK = 5MHz, fSAMPLE = 250kHz, unless otherwise noted.
100 95
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY
1.0 0.8
SNR and SINAD (dB)
SNR
DELTA OF SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE + DISTORTION vs TEMPERATURE (ALL CH)
SNR and SINAD (dB)
90 85 80 75 70 65 60 55 50 1 10
0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 SINAD SNR
SINAD
100 125
-1.0 -50 -25 0 25 50 75 100 Temperature (C)
Frequency (kHz)
110 100 90
SFDR (dB)
SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (All CH) SFR
DELTA OF SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMOINC DISTORTION vs TEMPERATURE (ALL CH)
-110 -100
3 2 THD SFDR (dB) THD (dB) 1 0 -1 SFR -2 -3 -50 -25 0 25 50 75 Temperature (C)
3 2 1 0 -1 -2 -3 100 THD (dB)
THD
-90 -80 -70 -60 -50 100 125
80 70 60 50 1 10 Frequency (kHz)
0.40 0.35
OFFSET OF ALL CHANNELS vs TEMPERATURE
0.40
OFFSET MATCHING BETWEEN CHANNELS vs TEMPERATURE
Channel A
Offset Matching (mV)
0.30
Offset (mV)
0.30
0.25 0.20 0.15 0.10 0.05 0.00 -50 -25 0 25 50 75 100 Temperature (C)
0.20
Channel B Channel C
0.10
0.00
-50 -25 0 25 50 75 100 Temperature (C)
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TYPICAL CHARACTERISTICS (Cont.)
At TA = +25C, AVDD = DVDD = +5V, BVDD = 3V VREF = internal +2.5V and fCLK = 5MHz, fSAMPLE = 250kHz, unless otherwise noted.
0.0030
Positive Gain Match (%FSR)
POSITIVE GAIN MATCH OF ALL CHANNELS vs TEMPERATURE
0.0025
NEGATIVE GAIN MATCH OF ALL CHANNELS vs TEMPERATURE Channel C
Negative Gain Match (%FSR)
0.0020 Channel A 0.0015 Channel B 0.0010
0.0025 Channel B 0.0020 Channel A 0.0015
Channel C
0.0005
0.0010 -50 -25 0 25 50 75 100 Temperature (C)
0.0000 -50
-25
0
25
50
75
100
Temperature (C)
0.065 0.060
GAIN ERROR OF CHANNELS vs TEMPERATURE
2.49600
REFOUT vs TEMPERATURE
0.055 0.050 0.045 0.040 0.035 0.030 -50 -25 0 25 50 Temperature (C) 75 100
Reference Voltages (V)
Gain Error (%FSR)
Channel A Channel B Channel C
2.49400 2.49200 2.49000 2.48800 2.48600 2.48400 2.48200 -50 -25 0 25 50 75 100 Temperature (C)
-80
CHANNEL-TO-CHANNEL ISOLATION
83.0 82.0
IQ vs TEMPERATURE
-90
Signal on Ch B1 (dB)
81.0 80.0
IQ (mV)
-95
79.0 78.0 77.0
-100
-105
76.0 75.0
-110 0 10 20 30 40 50 AC Frequency on Ch B0 (kHz)
74.0 -50 -25 0 25 50 75 100 Temperature (C)
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INTRODUCTION
The ADS8364 is a high-speed, low-power, 6-channel simultaneous sampling and converting, 16-bit ADC that operates from a single +5V supply. The input channels are fully differential with a typical common-mode rejection of 80dB. The part contains six 4s successive approximation ADCs, six differential sample-and-hold amplifiers, an internal +2.5V reference with REFIN and REFOUT pins and a high-speed parallel interface. There are six analog inputs that are grouped into three channel pairs (A, B, and C). There are six ADCs, one for each input that can be sampled and converted simultaneously, thus preserving the relative phase information of the signals on both analog inputs. Each pair of channels has a hold signal (HOLDA, HOLDB, and HOLDC) to allow simultaneous sampling on each channel pair, on four or on all six channels. The part accepts a differential analog input voltage in the range of -VREF to +VREF, centered on the common-mode voltage (see the Analog Input Section). The part will also accept bipolar input ranges when a level shift circuit is used at the front end (see Figure 6). A conversion is initiated on the ADS8364 by bringing the HOLDX pin LOW for a minimum of 20ns. HOLDX LOW places the sample-and-hold amplifiers of the X channels in the hold state simultaneously and the conversion process is started on each channel. The EOC output will go LOW for half a clock cycle when the conversion is latched into the output register. The data can be read from the parallel output bus following the conversion by bringing both RD and CS LOW. Conversion time for the ADS8364 is 3.2s when a 5MHz external clock is used. The corresponding acquisition time is 0.8s. To achieve the maximum output data rate (250kHz), the read function can be performed during the next conversion. Note: This mode of operation is described in more detail in the Timing and Control section of this data sheet.
50ps (also known as aperture jitter). These specifications reflect the ability of the ADS8364 to capture AC input signals accurately at the exact same moment in time.
REFERENCE
Under normal operation, the REFOUT (pin 61) can directly be connected to the REFIN pin (pin 62) to provide an internal +2.5V reference to the ADS8364. The ADS8364 can operate, however, with an external reference in the range of 1.5V to 2.6V, for a corresponding full-scale range of 3.0V to 5.2V, as long as the input does not exceed the AVDD + 0.3V value. The reference of the ADS8364 is double-buffered. If the internal reference is used to drive an external load, a buffer is provided between the reference and the load applied to pin 61 (the internal reference can typically source 10A of current--load capacitance should be 0.1F and 10F to minimize noise). If an external reference is used, the threesecond buffers provide isolation between the external reference and the CDACs. These buffers are also used to recharge all of the capacitors of all CDACs during conversion.
ANALOG INPUT
The analog input is bipolar and fully differential. There are two general methods of driving the analog input of the ADS8364: single-ended or differential, as shown in Figure 1 and Figure 2. When the input is single-ended, the -IN input is held at the common-mode voltage. The +IN input swings around the same common voltage and the peak-to-peak amplitude is the (common-mode + VREF) and the (common-mode - VREF). The value of VREF determines the range over which the common-mode voltage may vary (see Figure 3).
SAMPLE-AND-HOLD SECTION
The sample-and-hold amplifiers on the ADS8364 allow the ADCs to accurately convert an input sine wave of full-scale amplitude to 16-bit resolution. The input bandwidth of the sample-and-hold is greater than the Nyquist rate (Nyquist equals one-half of the sampling rate) of the ADC even when the ADC is operated at its maximum throughput rate of 250kHz. The typical small-signal bandwidth of the sampleand-hold amplifiers is 300MHz. Typical aperture delay time or the time it takes for the ADS8364 to switch from the sample to the hold mode following the negative edge of HOLDX signal is 5ns. The average delta of repeated aperture delay values is typically
-VREF to +VREF peak-to-peak Common Voltage Single-Ended Input
ADS8364
VREF peak-to-peak Common Voltage ADS8364 VREF peak-to-peak Differential Input
FIGURE 1. Methods of Driving the ADS8364 Single-Ended or Differential.
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CM + VREF +VREF CM Voltage
+IN
-IN = CM Voltage -VREF CM - VREF +IN +VREF CM Voltage -VREF CM - 1/2VREF -IN Differential Inputs (+IN) + (-IN) t t Single-Ended Inputs
CM + 1/2VREF
, Common-Mode Voltage (Single-Ended Mode) = IN-. 2 The maximum differential voltage between +IN and -IN of the ADS8364 is VREF. See Figures 3 and 4 for a further explanation of the common voltage range for single-ended and differential inputs.
NOTES: Common-Mode Voltage (Differential Mode) =
FIGURE 2. Using the ADS8364 in the Single-Ended and Differential Input Modes.
5 AVDD = 5V 4
Common Voltage Range (V)
5 4.55 4
Common Voltage Range (V)
AVDD = 5V 4.0
3.8
3
Single-Ended Input
2.7 2.3
3
Differential Input
2
2
1
1.2
1 0.45 0
1.0
0
-1 1.0 1.5 2.0 VREF (V) 2.5 2.6 3.0
-1 1.0 1.5 2.0 VREF (V) 2.5 2.6 3.0
FIGURE 3. Single-Ended Input: Common-Mode Voltage Range vs VREF. When the input is differential, the amplitude of the input is the difference between the +IN and -IN input, or: (+IN) - (-IN). The peak-to-peak amplitude of each input is 1/2VREF around this common voltage. However, since the inputs are 180 out-of-phase, the peak-to-peak amplitude of the differential voltage is +VREF to -VREF. The value of VREF also determines the range of the voltage that may be common to both inputs, as shown in Figure 4.
FIGURE 4. Differential Input: Common-Mode Voltage Range vs VREF. In each case, care should be taken to ensure that the output impedance of the sources driving the +IN and -IN inputs are matched. Often, a small capacitor (20pF) between the positive and negative input helps to match their impedance. Otherwise, this may result in offset error, which will change with both temperature and input voltage. The input current on the analog inputs depends on a number of factors as sample rate or input voltage. Essentially, the
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current into the ADS8364 charges the internal capacitor array during the sampling period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (25pF) to a 16-bit settling level within 3 clock cycles if the minimum acquisition time is used. When the converter goes into the hold mode, the input impedance is greater than 1G. Care must be taken regarding the absolute analog input voltage. The +IN and -IN inputs should always remain within the range of AGND - 0.3V to AVDD + 0.3V.
R1
4k 1.2k 20k Bipolar Input R2 OPA227 OPA227 1.2k -IN ADS8364 REFOUT (pin 61) 2.5V +IN
BIPOLAR INPUT 10V 5V 2.5V
R1 1k 2k 4k
R2 5k 10k 20k
TRANSITION NOISE
The transition noise of the ADS8364 itself is low, as shown in Figure 5. These histograms were generated by applying a low-noise DC input and initiating 8000 conversions. The digital output of the ADC will vary in output code due to the internal noise of the ADS8364. This is true for all 16-bit, SAR-type ADCs. Using a histogram to plot the output codes, the distribution should appear bell-shaped with the peak of the bell curve representing the nominal code for the input value. The 1, 2, and 3 distributions will represent the 68.3%, 95.5%, and 99.7%, respectively, of all codes. The transition noise can be calculated by dividing the number of codes measured by 6 and this will yield the 3 distribution, or 99.7%, of all codes. Statistically, up to three codes could fall outside the distribution when executing 1000 conversions. Remember, to achieve this low-noise performance, the peakto-peak noise of the input signal and reference must be < 50V.
FIGURE 6. Level Shift Circuit for Bipolar Input Ranges.
TIMING AND CONTROL
The ADS8364 uses an external clock (CLK, pin 28) which controls the conversion rate of the CDAC. With a 5MHz external clock, the ADC sampling rate is 250kHz which corresponds to a 4s maximum throughput time. Acquistion and conversion takes a total of 20 clock cycles.
THEORY OF OPERATION
The ADS8364 contains six 16-bit ADCs that can operate simultaneously in pairs. The three hold signals (HOLDA, HOLDB, and HOLDC) initiate the conversion on the specific channels. A simultaneous hold on all six channels can occur with all three hold signals strobe together. The converted values are saved in six registers. For each read operation, the ADS8364 outputs 16 bits of information (16 Data or 3 Channel Address, Data Valid, and some synchronization information). The Address/Mode signals (A0, A1, and A2) select how the data is read from the ADS8364. These Address/Mode signals can define a selection of a single channel, a cycle mode that cycles through all channels, or a FIFO mode that sequences the data determined by the order of the hold signals. The FIFO mode will allow the six registers to be used by a single-channel pair and, therefore, three locations for CH X0 and three locations for CH X1 can be updated before they are read from the part.
2726
1183 930 906 813 720 680
0
167 32807 32808 32809 32810 32811 Code
67 32812
0 32813
32803 32804 32805 32806
FIGURE 5. 8000 Conversion Histogram of a DC Input.
EXPLANATION OF CLOCK, RESET, FD, AND EOC PINS Clock--An external clock has to be provided for the ADS8364. The maximum clock frequency is 5MHz. The minimum clock cycle is 200ns (Timing Diagram, tC1), and the clock has to remain HIGH (Timing Diagram, tW1) or LOW for at least 60ns.
RESET--Bringing reset signal LOW will reset the ADS8364. It will clear all the output registers, stop any actual conversions, and will close the sampling switches. The reset signal has to stay LOW for at least 20ns (see Figure 7, tW4). The reset signal should be back HIGH for at least 20ns (see Figure 7, tD2), before starting the next conversion (negative hold edge).
BIPOLAR INPUTS
The differential inputs of the ADS8364 were designed to accept bipolar inputs (-VREF and +VREF) around the common-mode voltage (2.5V), which corresponds to a 0V to 5V input range with a 2.5V reference. By using a simple op amp circuit featuring four, high-precision external resistors, the ADS8364 can be configured to accept bipolar inputs. The conventional 2.5V, 5V, and 10V input ranges could be interfaced to the ADS8364 using the resistor values shown in Figure 6.
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EOC--End of conversion goes low when new data of the internal ADC is latched into the output registers, which usually happens 16.5 clock cycles after hold initiated the conversion. It remains low for half a clock cycle. If more than one channel pair is converted simultaneously, the A-channels get stored to the registers first (16.5 clock cycles after hold), followed by the B-channels one clock cycle later, and finally the C-channels at another clock cycle later. If a reading (RD and CS are LOW) is in process, then the latch process is delayed until the read operation is finished.
FD--First data or A0 data is HIGH if channel A0 is chosen to be
read next. In the FIFO mode whatever channel X0 is written to the FIFO first is latched into the A0 register. So for example, when the FIFO is empty, FD is 0. Then the first result is latched into the FIFO register A0 is, therefore, chosen to be read next, and FD rises. After the first channel is read (1-3 read cycles depending on BYTE and ADD) FD goes LOW again.
The ADS8364 can also convert one channel continuously (see Figure 8). Therefore, HOLDA and HOLDC are kept HIGH all the time. To gain acquisition time, the falling edge of HOLDB takes place just before the rising edge of clock. One conversion requires 20 clock cycles. Here, data is read after the next conversion is initiated by HOLDB. To read data from channel B, A1 is set HIGH and A2 is LOW. As A0 is LOW during the first reading (A2 A1 A0 = 010) data B0 is put to the output. Before the second RD, A0 switches HIGH (A2 A1 A0 = 011) so data from channel B1 is read, as shown in Table II. However, reading data during the conversion or on a falling hold edge might cause a loss in performance.
A2 0 0 0 0 1 1 1 A1 0 0 1 1 0 0 1 A0 0 1 0 1 0 1 0 CHANNEL TO BE READ CHA0 CHA1 CHB0 CHB1 CHC0 CHC1 Cycle mode reads registers CHA0 through CHC1 on successive transitions of the read line. 1 1 1 FIFO Mode
START OF A CONVERSION AND READING DATA
By bringing one, two, or all of the HOLDX signals LOW, the input data of the corresponding channel X is immediately placed in the hold mode (5ns). The conversion of this channel X follows with the next rising edge of clock. If it is important to detect a hold command during a certain clock-cycle, then the falling edge of the hold signal has to occur at least 10ns before the rising edge of clock, as shown in Figure 7, tD1. The hold signal can remain LOW without initiating a new conversion. The hold signal has to be HIGH for at least 15ns (as shown in Figure 7, tW2) before it is brought LOW again and hold has to stay LOW for at least 20ns (Figure 7, tW3). Once a particular hold signal goes low, further impulses of this hold signal are ignored until the conversion is finished or the part is reset. When the conversion is finished (after 16 clock cycles) the sampling switches will close and sample the selected channel. The start of the next conversion must be delayed to allow the input capacitor of the ADS8364 to be fully charged. This delay time depends on the driving amplifier, but should be at least 800ns.
TABLE II. Address Control for RD Functions.
Reading data (RD, CS )--In general, the channel/data
outputs are in tri-state. Both CS and RD have to be LOW to enable these outputs. RD and CS have to stay LOW together for at least 40ns (see Timing Characteristics, tD6) before the output data is valid. RD has to remain HIGH for at least 30ns (see Timing Diagram, tW5) before bringing it back LOW for a subsequent read command. 16.5 clock-cycles after the start of a conversion (next rising edge of clock after the falling edge of HOLDX ), the new data is latched into its output register. Even if the ADS8364 is forced to wait until the read process is finished (RD signal going HIGH) before the new data gets latched into its output
tC1 CLK tD1
tW1
HOLD A tW3
HOLD B tD2 HOLD C tW4 tW2
RESET
FIGURE 7. Start of the Conversion.
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CONVERSION CLK 1 2 16 17 18
ACQUISITION 19 20 1 2
HOLD B
EOC
CS
RD
A0
FIGURE 8. Timing of one Conversion Cycle.
CLK
16
17
18
19
20 tD1
1
2
HOLD X tACQ EOC
CS tD8 RD tD9 A0 tW7
FIGURE 9. Timing for Reading Data. register, the possibility still exists that the new data was latched to the output register just before the falling edge of RD. If a read process is initiated around 16.5 clock cycles after the conversion started, RD and CS should stay LOW for at least 50ns (see Timing Diagram, tW6) to get the new data stored to its register and switched to the output. CS being LOW tells the ADS8364 that the bus on the board is assigned to the ADS8364. If an ADC shares a bus with digital gates, there is a possibility that digital (high-frequency) noise will be coupled into the ADC. If the bus is just used by the ADS8364, CS can be hardwired to ground. Reading data at the falling edge of one of the HOLDX signals might cause noise. If BYTE is LOW, then the ADS8364 operates in the 16-bit output mode. Here, data is read between the pins DB15 and DB0. As long as ADD is LOW, with every RD-impulse, data from a new channel is brought to the output. If ADD is HIGH, and the cycle or the FIFO mode is chosen; the first output word will contain the address, while the second output word contains the 16-bit data.
ADD-Signal-In the cycle and the FIFO mode, it might be
desirable to have address information with the 16-bit output data. Therefore, ADD can be set HIGH. In this case, two (or three readings if the part is operated with byte being HIGH) RD-signals are necessary to read data of one channel, while the ADS8364 provides channel information on the first RD signal (see Table III and Table IV). The signals ADD, A0, A1, A2, RESET, HOLDA, HOLDB, and HOLDC are accessible through the data bus and control word. All these pins are in OR configuration with hardware pins. When software configuration is used, the corresponding pins must be connected to ground or the power supply. When the MSB is HIGH, the device is in the configuration mode. MSB LOW will start conversion or reset the part.
BYTE--If there is only an 8-bit bus available on a board, then BYTE can be set HIGH. (see Figure 11) In this case, the lower 8 bits can be read at the output pins D15 to D8 or D7 to D0 at the first RD signal and the higher bits after the second RD signal. If the ADS8364 is used in the cycle or the FIFO mode, then the address and a data valid information is added to the data if ADD is HIGH. In this case, the address will be read first, then the lower 8 bits, and finally the higher 8 bits.
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Binary Two's Complement BTC 0111111111111111 0111111111111110 0111111111111101 65535
65534 65533
Digital Output Code
0000000000000001 0000000000000000 1111111111111111
32769
Step
32768
32767
1000000000000010
2
1000000000000001
1 0
1000000000000000
VNFS = VCM - VREF = 0V 0.000038V 0.000076V 0.000152V 16-BIT
2.499962V
2.500038V VBPZ = 2.5V
VPFS = VCM + VREF = 5V VPFS - 1LSB = 4.999924V 4.999848V 1LSB = 76V VCM = 2.5V VREF = 2.5V
Unipolar Analog Input Voltage
Bipolar Input, Binary Two's Complement Output: (BTC) Negative Full-Scale Code = VNFS = 8000H, Vcode = VCM - VREF Bipolar Zero Code = VBPZ = 0000H, Vcode = VCM Positive Full-Scale Code = VPFS = 7FFFH, Vcode = (VCM + VREF) - 1LSB
FIGURE 10. Ideal Conversion Characteristics (Condition: Single Ended, VCM = chXX- = 2.5V, VREF = 2.5V)
CS
RD
BYTE
D7 - D0
A0 LOW
A0 HIGH
A1 LOW
A1 HIGH
B0 LOW
B0 HIGH
B1
C0
C1
A0
FIGURE 11. Reading Data in Cycling Mode.
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ADD = 0 A2 A1 A0 000 001 010 011 100 101 110 111
BYTE = 0 1st RD db15...db0 db15...db0 db15...db0 db15...db0 db15...db0 db15...db0 db15...db0 db15...db0 2nd RD no 2nd RD no 2nd RD no 2nd RD no 2nd RD no 2nd RD no 2nd RD no 2nd RD no 2nd RD 1st RD db7...db0 db7...db0 db7...db0 db7...db0 db7...db0 db7...db0 db7...db0 db7...db0
BYTE = 1 2nd RD db15...db8 db15...db8 db15...db8 db15...db8 db15...db8 db15...db8 db15...db8 db15...db8 3rd RD no 3rd RD no 3rd RD no 3rd RD no 3rd RD no 3rd RD no 3rd RD no 3rd RD no 3rd RD
If all the output registers are filled up with unread data and new data from an additional conversion has to get latched in, then the oldest data gets thrown away. If a read process is going on (RD-signal LOW) and new data has to be stored, then the ADS8364 will wait until the read process is finished (RD-signal going HIGH) before the new data gets latched into its output register. Again, with the ADD signal, it can be chosen if the address should be added to the output data. New data is always written into the next available register. At t0 (see Figure 12), the reset deletes all the existing data. At t1, the new data of the channels A0 and A1 are put into registers 0 and 1. At t2, the read process of channel A0 data is finished. Therefore, this data is dumped and A1 data is shifted to register 0. At t3, new data is available, this time from channels B0, B1, C0 and C1. This data is written into the next available registers (registers 1, 2, 3, and 4). On t4, the new read process of channel A1 data is finished. The new data of channel C0 and C1 at t5 is put on top (registers 4 and 5). In Cycle mode and in FIFO mode, the ADS8364 offers the ability to add the address of the channel to the output data. As there is just a 16-bit bus available (or 8-bit bus in the case byte is HIGH), an additional (RD-signal is necessary to get the information (see Table III and Table IV).
TABLE III. Overview of the Output Formats Depending on the Mode (Case ADD = 0). The HOLD signals will start conversion automatically on the next clock cycle. The format of the two words that can be writing to ADS8364 are shown in Table V.
GETTING DATA
Flexible output modes: (A0, A1, A2) The ADS8364 has three different output modes that are selected with A2, A1, and A0. With (A2 A1 A0) = 000 to 101, a particular channel can directly be addressed (see Table II and Figure 9). The channel address should be set at least 10ns (see Figure 9, tD9) before the falling edge of RD and should not change as long as RD is LOW. In this standard address mode, ADD will be ignored, but should be connected to either ground or supply. With (A2 A1 A0) = 110, the interface is running in a cycle mode (see Figure 11). Here, data 7 down to 0 of channel A0 is read on the first RD-signal and 15 down to 8 on the second as BYTE is HIGH. Then A1 on the second, followed by B0, B1, C0, and finally, C1 before reading A0 again. Data from channel A0 is brought to the output first after a reset-signal or after powering the part up. The third mode is a FIFO mode that is addressed with (A2 A1 A0 = 111). Data of the channel that is converted first will be read first. So, if a particular channel pair is most interesting and is converted more frequently (e.g., to get a history of a particular channel pair) then there are three output registers per channel available to store data.
ADD = 1 A2A1A0 000 001 010 011 100 101 110 111 1st RD db15...db0 db15...db0 db15...db0 db15...db0 db15...db0 db15...db0 1000 0000 0000 dv a2 a1 a0 1000 0000 0000 dv a2 a1 a0 BYTE = 0 2nd RD no 2nd RD no 2nd RD no 2nd RD no 2nd RD no 2nd RD no 2nd RD db15...db0 db15...db0
The Output Code (DB15...DB0)-In the standard address
mode (A2 A1 A0 = 000...101), the ADS8364 has a 16-bit output word on pins DB15...DB0 if BYTE = 0. If BYTE = 1 then two RD-impulses are necessary to first read the lower bits then the higher bits on either DB7...DB0 or DB15...DB8. The address of the channel (a2a1a0) and a data valid (dv) bit is added to the data if the ADS8364 is operated in the cycle or in the FIFO-mode and ADD is set HIGH. If BYTE = 0, then the data valid and the address of the channel is active during the first (RD-impulse (1000 0000 0000 dv a2 a1 a0). During the second (RD, the 16-bit data word can be read (db15...db0). If BYTE = 1, then three (RD-impulses are needed. On the first one, data valid, the three address bits and the data bits db3...db0 (dv, a2, a1, a0, db3, db2, db1, db0) are read, followed by the 8 lower bits of the 16-bit data word (db7...db0)
BYTE = 1 1st RD db7...db0 db7...db0 db7...db0 db7...db0 db7...db0 db7...db0 dv a2 a1 a0 db3 db2 db0 dv a2 a1 a0 db3 db2 db0 2nd RD db15...db8 db15...db8 db15...db8 db15...db8 db15...db8 db15...db8 db7...db0 db7...db0 3rd RD no 3rd RD no 3rd RD no 3rd RD no 3rd RD no 3rd RD no 3rd RD db15...db8 db15...db8
TABLE IV. Overview Over the Output formats Depending on the Mode in Case ADD = 1
DB7 (MSB) 1 0 DB6 X X DB5 X X DB4 X X DB3 ADD RESET DB2 A2 HOLDA DB1 A1 HOLDB DB0 (LSB) A0 HOLDC
TABLE V. Data Register Bits.
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RESET
EOC
Conversion Channel A
Conversion Channels B and C
Conversion Channel C
RD reg. 5 reg. 4 reg. 3 reg. 2 reg. 1 reg. 0 empty empty empty empty empty empty empty empty empty empty ch A1 ch A0 empty empty empty empty empty ch A1 empty ch C1 ch C0 ch B1 ch B0 ch A1 empty empty ch C1 ch C0 ch B1 ch B0 ch C1 ch C0 ch C1 ch C0 ch B1 ch B0
t0
t1
t2
t3
t4
t5
FIGURE 12. Functionality Diagram of FIFO Registers. and finally the higher 8 data bits (db15...db8). 1000 0000 0000 is added before the address in case BYTE = 0 and db3...db0 after the address if BYTE = 1. This provides the possibility to check if the counting of the RD signals inside the ADS8364 are still tracking with the external interface (see Table III and Table IV). The data valid bit is useful for the FIFO mode. Valid data can simply get read until dv turns 0. The three address bits are listed in Table VI. If the FIFO is empty, 16 zeros are put to the output.
a2 Data From Channel A0 Data From Channel A1 Data From Channel B0 Data From Channel B1 Data From Channel C0 Data From Channel C1 0 0 0 0 1 1 a1 0 0 1 1 0 0 a0 0 1 0 1 0 1
ing power supplies, nearby digital logic, or high-power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. Their error can change if the external event changes in time with respect to the CLK input. With this in mind, power to the ADS8364 should be clean and well bypassed. A 0.1F ceramic bypass capacitor should be placed as close to the device as possible. In addition, a 1F to 10F capacitor is recommended. If needed, an even larger capacitor and a 5 or 10 series resistor may be used to lowpass filter a noisy supply. On average, the ADS8364 draws very little current from an external reference as the reference voltage is internally buffered. A bypass capacitor of 0.1F and 10F are suggested when using the internal reference (tie pin 61 directly to pin 62).
GROUNDING
The AGND and DGND pins should be connected to a clean ground point. In all cases, this should be the `analog' ground. Avoid connections that are too close to the grounding point of a microcontroller or digital signal processor. If required, run a ground trace directly from the converter to the powersupply entry point. The ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry. Three signal ground pins, SGND, are the input signal grounds which are on the same potential as analog ground.
TABLE VI. Address Bit in the Output Data.
LAYOUT
For optimum performance, care should be taken with the physical layout of the ADS8364 circuitry. This is particularly true if the CLK input is approaching the maximum throughput rate. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving any single conversion for an n-bit SAR converter, there are n "windows" in which large external transient voltages can affect the conversion result. Such glitches might originate from switch-
APPLICATION INFORMATION
In Figures 13 through 18, different connection diagrams to DSPs or micro-controllers are shown.
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ADS8364 BVDD BVDD 26 30 23 55 HOLDA HOLDB FD WR ADD BYTE HOLDC A0 A1 A2 CS 56 57 58 54 53 52
3.3V DVDD PWM1 PWM2 PWM3 EA0 EA1 EA2 EA3 8:1 OE RD EOC CLK 29 27 28 51 48 ... 33 IS RE
C28xx
31
EXT_INT1 MCLKX ADC_RST (MFSX) D0 ... D15 VSS
RESET DATA [0] ... DATA [15] BGND
FIGURE 13. Typical F28xx Connection (Hardware Control).
BVDD 56 57 58 26 23 55 54 53 52
ADS8364 HOLDA HOLDB HOLDC FD ADD BYTE A0 A1 A2 CS RD WR EOC CLK 27 28 31 29 30 8:1 OE BVDD
3.3V DVDD
C28xx
A2 A1 A0 IS RE WE EXT_INT1 MCLKX
DATA [0] ... DATA [15] BGND
48 ... 33
D0 ... D15 VSS
FIGURE 14. Typical F28xx Connection (Software Control).
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ADS8364 BVDD BVDD 26 54 53 52 30 23 55 HOLDA HOLDB FD A0 A1 A2 WR ADD BYTE EOC CLK RESET DATA [0] ... DATA [15] BGND 48 ... 33 RD CS 31 29 30 27 28 51 <1 (1G32) HOLDC 56 57 58 8:1
3.3V DVDD TOUT0 A2 A1 A0 IS
C54xx
OE
I/OSTRB INT0 BCLKX1 XF D0 ... D15 VSS
FIGURE 15. Typical F28xx Connection (FIFO with Hardware Control).
ADS8364 BVDD 30 53 52 23 54 WR A1 A2 ADD A0 CS BYTE RD EOC CLK RESET DATA [0] ... DATA [15] BGND 27 28 51 48 ... 33 31 55 29
3.3V
C67xx DVDD
BVDD
HOLDA HOLDB HOLDC 56 57 58 8:1 OE
TOUT1 A2 A1 A0 IS BE0 RE INT0 TOUT0 DB_CNTL0 (ED27) D0 ... D15 VSS
FIGURE 16. Typical F28xx Connection (Cycle Mode - Hardware Control).
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BVDD 56 57 58 26 23 55 54 53 52
ADS8364 HOLDA HOLDB HOLDC FD ADD BYTE A0 A1 A2 CS RD WR EOC CLK 27 28 31 29 30 8:1 OE BVDD
3.3V DVDD
C67xx
A2 A1 A0 IS RE WE INT0 TOUT0
DATA [0] ... DATA [15] BGND
48 ... 33
D0 ... D15 VSS
FIGURE 17. Typical F67xx Connection (Software Control).
ADS8364 BVDD 30 52 54 53 23 55 29 BVDD HOLDA WR ADD A1 A2 BYTE A0 RD HOLDB HOLDC CS RESET EOC CLK DATA [0] ... DATA [7] BGND 56 57 58 31 51 27 28 48 ... 41
3.3V
MSP430x1xx DVDD TACLK (P1.0)
P1.1 P1.2 P1.3 (ADC_INT) SMCLK (P1.4) P2.0 ... P2.7 VSS
FIGURE 18. Typical MSP430x1xx Connection (Cycle Mode - Hardware Control).
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PACKAGE DRAWING
MTQF006A - JANUARY 1995 - REVISED DECEMBER 1996
PAG (S-PQFP-G64)
0,50 48 33 0,27 0,17
PLASTIC QUAD FLATPACK
0,08 M
49
32
64
17 0,13 NOM 1 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 1,05 0,95 Seating Plane Gage Plane 0,25 0,05 MIN 0- 7 0,75 0,45 16
1,20 MAX
0,08 4040282 / C 11/96
NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
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Copyright 2002, Texas Instruments Incorporated

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