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| CL-PS7111 Application Note -- AN-PS1 CL-PS7111 Evaluation Kit User Manual Portable Systems Cirrus Logic Inc. Scope and Applicability The CL-PS7111 evaluation kit (Order no. CL-PSK7111DM01) is offered by Cirrus Logic to assist system designers in building CL-PS7111-based systems and developing and debugging drivers and application programs for this highly integrated microcontroller. The evaluation kit provides software and hardware support to evaluate performance and measure power consumption under various conditions. This kit contains a reference board to be used as the starting point for new designs. A system designer can elect to use the board as the `motherboard' and simply add application-specific I/O modules to the board. For example, the designer of a two-way pager can incorporate the pager functionality as an I/O module attached to the basic board. All engineering design collateral is provided in this kit. System Requirements The preloaded debug monitor requires a PC running the symbolic debug monitor PC (DOS or Windows (R) 95). Contact ARM at www.arm.com or Cirrus Logic to order the ARM toolkit containing a C-compiler, linker, and assembler. Familiarity with the ARM tools, such as ARMSD and/or Tool 200, is required to use the evaluation board. Copyright (c) 1997 -- Cirrus Logic Inc. All rights reserved. This document describes a potential application of Cirrus Logic Inc. integrated circuits. No warranty is given for the suitability of the circuitry or program code described herein for any purpose other than demonstrating functional operation. The information contained in this document is subject to change without notice. Version 1.0 AN146REV1 APR '97 CL-PS7111 Evaluation Kit -- User Manual Table of Contents List of Figures .......................................................................................... 3 List of Tables ............................................................................................. 3 1. INTRODUCTION ........................................................................................ 4 1.1 Ordering Information ................................................................................................ 4 2. EVALUATION KIT CONTENTS ................................................................. 5 2.1 Options ..................................................................................................................... 5 3. EVALUATION BOARD ............................................................................... 6 3.1 3.2 3.2.1 3.2.2 3.2.3 3.3 3.3.1 3.3.2 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.5 3.6 3.6.1 3.6.2 3.7 3.8 3.9 3.10 3.11 3.12 Main Feature Set ...................................................................................................... 7 Board Revisions ....................................................................................................... 8 Software Revision .............................................................................................. 8 Endian Operation ............................................................................................... 8 Stuffing Options ................................................................................................. 8 Board Setup ............................................................................................................. 9 Power ................................................................................................................. 9 LCD ................................................................................................................... 9 Boot Sequence ........................................................................................................ 9 Boot Program Resize to 2 Kbytes .................................................................... 10 Boot Program File Format ............................................................................... 11 Booting with Start Up Sequence from the Serial Port ..................................... 11 Start Up Sequence Using Preinstalled Debug Monitor (DEMON) ................... 12 Configure the ARM Debugger for Windows(R) (Tool v2.1) ................................. 13 Board Layout .......................................................................................................... 14 Memory Architecture .............................................................................................. 18 Memory Map in Operating Mode ..................................................................... 19 Memory Map in Boot Mode ............................................................................. 19 I/O Port Allocation .................................................................................................. 20 Analog-to-Digital Converter .................................................................................... 21 LCD Interface ......................................................................................................... 21 J1 Connector Pinout .............................................................................................. 22 J24 Connector Pinout ............................................................................................ 23 Codec ..................................................................................................................... 23 4. DESIGN FILES ........................................................................................ 24 4.1 4.2 System Board ........................................................................................................ 24 Key Board............................................................................................................... 24 5. BOOT CODE AND DEMON FILES ......................................................... 24 6. POWER SUPPLY DESIGN ...................................................................... 25 6.1 6.2 Step-up Converter .................................................................................................. 25 Step-Down Converter ............................................................................................. 26 7. MEASURING CL-PS7111 POWER CONSUMPTION ............................. 27 2 Table of Contents APPLICATION NOTE v1.0 April 1997 CL-PS7111 Evaluation Kit -- User Manual 8. DC-DC CONVERTER .............................................................................. 28 8.1 Setup Procedure .................................................................................................... 28 8.1.1 Negative VEE .............................................................................................................................. 31 8.1.2 VPP Control ...................................................................................................... 32 9. PC Card (PCMCIA) Interface .................................................................. 33 9.1 9.1.1 9.2 9.3 9.4 9.5 9.6 PC Card Power Switches at Multiple Points ........................................................... 33 PC Card Power ................................................................................................ 33 CL-PS7111-to-CL-PS6700 Interconnect Diagram ................................................. 34 Interrupts ................................................................................................................ 34 DMA Support ......................................................................................................... 34 Power Down ........................................................................................................... 34 Clocks .................................................................................................................... 35 A. Source Address Locator ........................................................................ 36 B. Bill of Materials ....................................................................................... 37 C. Schematics ............................................................................................. 46 List of Figures Figure 3-1 3-2 8-1 8-2 9-1 Page CL-PS7111 Evaluation Board Block Diagram ............................................. 6 Null-Modem Cable ...................................................................................... 9 CL-PS7111 DC-DC Converter for Positive VEE .................................................... 29 CL-PS7111 DC-DC Converter for Negative VEE .................................................. 31 CL-PS7111-to-CL-PS6700 Interconnect Diagram .................................... 34 List of Tables Table 3-1 3-2 3-3 3-4 3-5 3-6 3-7 7-1 8-1 8-2 8-3 8-4 8-5 9-1 Page Assembly Instruction ................................................................................... 8 Boot Software Programs ........................................................................... 10 Port Allocation Pin Configuration .............................................................. 20 J2 Connector Pins ..................................................................................... 21 Compatible Panels .................................................................................... 22 J1 Connector Pins ..................................................................................... 22 J24 Pin Connections ................................................................................. 23 Typical Current Values at Various Conditiona ............................................ 27 VEE Control Circuitry ................................................................................. 28 Duty Ratio = 5 ........................................................................................... 29 Duty Ratio = 2 ........................................................................................... 30 Negative VEE Control Circuitry .................................................................. 31 DC-DC Pump Ratio = 5 ............................................................................. 32 Switch Settings .......................................................................................... 33 April 1997 APPLICATION NOTE v1.0 List of Figures 3 CL-PS7111 Evaluation Kit -- User Manual 1. INTRODUCTION The CL-PS7111 evaluation kit is targeted for system designers who are developing CL-PS7111-based platforms. This kit is also for software developers who plan to port operating systems and applications to the CL-PS7111. To use the CL-PS7111 evaluation kit, the ARM toolkit containing the C-compiler, linker and assembler, debugger, and ARM instruction set emulators is required. The CL-PS7111 evaluation kit is intended to be used with the ARM toolkit running on a PC with DOS, Windows 3.1 or Windows 95 installed. 1.1 Ordering Information The following presents part numbering ordering information: q q CL-PS7111 Evaluation Kit: CL-PS7111-DMBD01 ARM toolkit: PSKARMTOOL-01 4 INTRODUCTION APPLICATION NOTE v1.0 April 1997 CL-PS7111 Evaluation Kit -- User Manual 2. EVALUATION KIT CONTENTS The evaluation kit contains: q q CL-PS7111 evaluation board Keyboard -- X/Y key matrices LCD Panel -- 240 x 100 pixels, 3.3-V Cirrus Logic, or -- 320 x 240 pixels, 3.3-V Alps(R) Maxim(R) data sheets -- Step-up/down converter -- A/D converter Oki America(R), Inc. data sheets -- Telephone codec, MSM7702 -- Speaker amplifier, MSC1192 ARM710 core data book 9-V AC/DC adapter CL-PS7111 demonstration program disk Schematic layout disk CL-PS7111 data book 2 null-modem cables ARM(R) debug monitor preloaded in flash memory q q q q q q q q q q 2.1 Options One of the following panels can be made available upon request: q Sharp(R) LM48014F -- 480 x 320 pixels +28 V VEE Alps(R) KHABAA902A -- 320 x 240 pixels +20 V VEE q April 1997 APPLICATION NOTE v1.0 EVALUATION KIT CONTENTS 5 CL-PS7111 Evaluation Kit -- User Manual 3. EVALUATION BOARD The evaluation board is designed as a prototype with some debugging capabilities, such as test headers for logic analyzer trace, optional memory, and I/O configurations. Figure 3-1 shows the block diagram of the evaluation board. CL-PS7111 EVAL BOARD D-Bus 16/32Bit LCD 240*100 320*240 480*320 TOUCH SCREEN CL-PS7111 FLASH 4xAT29LV040A DIP FLASH 4xAm29LV800B 4MByte TQFP-208 A-Bus SPI SERIAL 4WIRE MAX148 A/D SPEAKER SERIAL 4WIRE CODEC 1xHM5116160ALTT CODEC OKI MSM7702 MICRO JEIDA 88pin DRAM MODULE 32Bit/2Banks CL-PS6700 PCMCIA TYPE I/II/III IO MODULE MODEM V.34 2 WAY PAGER SERIAL PORT ANALOG/DIG I/O RADIO I/F MAX3212 SERIAL1 RS232 SWITCH SERIAL 2 RS232 1.8 to 3V POWER SUPPLY IR MODULE CS8130M 6 to 12V Figure 3-1. CL-PS7111 Evaluation Board Block Diagram 6 EVALUATION BOARD APPLICATION NOTE v1.0 April 1997 CL-PS7111 Evaluation Kit -- User Manual 3.1 Main Feature Set The evaluation board has the following features: q Processing speed -- 18.432 MHz -- 13 MHz when using an optional oscillator Flash memory -- 1 or 2 banks of 512K x 32 bits (2 Mbyte); reprogrammable at 3 V DRAM -- 1 bank of 1 Mbit x 16 bit (2 Mbyte) JEIDA connector -- DRAM expansion to two banks of 32-bit DRAMs are possible with this connector Power -- Step-up converter from 1.8 to 4.0 to 3.3 V -- Step-down converter from 6.0 to 14 to 3.3 V -- PC card 3.3 or 5 V from VDD -- LCD bias VDD to 35 V from 3.3 V (positive or negative bias selectable) -- VPP for PC card from VDD q q q q q Asynchronous serial port (two) -- Ports programmable up to 115 kbaud Infrared -- IrDA-compliant 115 kbaud (port multiplexed with asynchronous serial port 1) Keyboard -- Keyboard matrix on daughter card (optional) PC Card -- 68-pin card connector, fully isolated, 3.3 V or 5 V cards are supported -- Supported by single-chip controller, CL-PS6700 A/D -- 10-bit A/D converter, 8 channels, MAX 148 Codec -- Telephone codec, OKI MSM7702 Speaker -- With amplifier, OKI MSC1192 LCD -- Three optional LCD connectors Expansion Connector -- 50-pin expansion connector for add-on peripherals 8-bits wide, such as UART- and SPI-compatible peripherals q q q q q q q q q Boot from serial port with 32-bit wide flash April 1997 APPLICATION NOTE v1.0 EVALUATION BOARD 7 CL-PS7111 Evaluation Kit -- User Manual The debug monitor that is preprogrammed into the flash memory requires that a PC be connected through a serial cable on serial port 2, and that the PC run the ARM symbolic debugger. Other operating systems are downloadable as described in Section 3.4 on page 9. 3.2 Board Revisions The board described in Rev 0.2 of the Evaluation Kit User's Manual is Revision A. The CL-PS7111 is on a socket and can be replaced with the current revision. A separate errata sheet is also available. Please contact Cirrus Logic for the latest silicon status. 3.2.1 Software Revision There has been a change in the ARM compiler in Toolkit v2.0 and later. Please note that assembly instruction ADR is no longer supported when addresses are defined using equates. Use the LDR instruction as shown in Table 3-1. Table 3-1. Assembly Instruction Old ADR R4, LCD address LDR New R4, = LCD address 3.2.2 Endian Operation The CL-PS7111 is a bi-endian processor however, all supplied programs operate in Little Endian mode. No hardware change is required for Big Endian mode. The byte-lane switch is performed inside the memory controller. 3.2.3 Stuffing Options A number of stuffing options are available: q Clock source -- 18 MHz from 3.6864 MHz crystal -- 13 MHz from oscillator VEE control -- Positive or negative LCD panel -- 3.3-V panel 240 x 100 -- Other panels can be connected on jumpers J2 and J15 Buzzer -- Use loud speaker instead of buzzer DRAM -- Use 32-bit wide banks as supported on the JEIDA connector q q q q Though the board could also be stuffed with one bank of 16-bit flash memory in Bank 0, the reprogramming of AMD flash must be unlocked by a proper address/data sequence cannot be performed. Use 32or 8-bit wide banks of AMD flash memory. If 16-bit wide flash must be used, then use devices that require a programming voltage, VPP . 8 April 1997 EVALUATION BOARD APPLICATION NOTE v1.0 CL-PS7111 Evaluation Kit -- User Manual 3.3 Board Setup This serial port connection is through the supplied null-modem cable to the port marked SERIAL 2 and to the PC host port COM1 or COM2. AMP 5577715-1 SUB-D FEMALE 9-PIN 3 2 6 5 4 8 7 -RxD 2 -TxD 3 -DTR 4 -GND 5 -DSR 6 -RTS 7 -CTS 8 Figure 3-2. Null-Modem Cable 3.3.1 Power Two AA batteries connected to J3 or a 9-V AC/DC adapter connected to J9 can provide power through a 1.3 mm circular connector. GND is on the center pin. When using a battery connected to J3, ensure the polarity is correct. 3.3.2 LCD Connect the provided LCD module to the 17-pin flat cable on J1. Other panels can be connected to the 11-pin connector, J3, and the 17-pin connector, J15. The pinout of these connectors are compatible with some Sharp and Alps panels, respectively. Ensure that the polarity for VEE is properly set for panels that require VEE for contrast control. Solder bridges W1, W2, W7, and W8 must be properly set, and some resistors must be properly stuffed (refer to legend included in the schmematics in Section 3.5 on page 14). 3.4 Boot Sequence The on-chip boot program can be activated by pulling MEDCHG/-BOOTEN low at power up. This allows code to be easily loaded into the flash memory. Use UART Port 1 of the CL-PS7111 to boot up. The standard setting is 9600 baud, 1 start bit, 1 stop bit, and no parity. The evaluation kit includes a modified version of the ARM debug monitor (ROMU2L) preloaded into the flash memory. The debug monitor operates from UART2. An optional add-on board can be connected to the 50-pin connector, J10. If it is necessary to operate the debug monitor from the serial port on this module to free UART2, then the program ROMDBL must be loaded into the flash memory. The on-chip boot code executes at power up when the boot is enabled. The MEDCHG/-BOOTEN pin must be low at the rising edge of -POR. An on-chip boot program code is executed as discussed in the CL-PS7111 Data Book. This code loads a 2-Kbyte file into the on-chip SRAM of the CL-PS7111, jumps to April 1997 9 APPLICATION NOTE v1.0 EVALUATION BOARD CL-PS7111 Evaluation Kit -- User Manual the beginning of the 2k block, and executes the loaded program that in turn loads a debug monitor (such as DEMONU2L) or an operating system. The loaded code is referred to as the secondary boot code. This code actually boots the operating system and programs the flash. The file size of BOOTAMD0 is exactly 2048 bytes, and it always uses UART1. This program can be customized if another interface is selected (such as the IrDA port or a PCMCIA flash card). The code is stored into the on-board flash memory beginning at memory address space 0. Once the code is successfully loaded, the system must be powered down and the boot switch (jumper) removed (the MEDCHG/-BOOTEN signal must be high). On the next power up, the program executes from memory address space 0 out of Flash Bank 0. Two separate programs are provided for Bank 0 and Bank 1. The operating system normally provides the `flashing', other than the mandatory boot block. If the DEMON is running, use the supplied program, FLASH, to erase and program individual sectors. Table 3-2. Program BOOTAMD0 BOOTAMD1 ROMU2L ROMDBL FLASH Boot Software Programs Function Initial program that downloads to SRAM, must be exactly 2 Kbytes; downloads code into Bank 0. Initial program that downloads to SRAM, must be exactly 2 Kbytes; downloads code into Bank 1. DEMON uses UART2; little endian. DEMON uses add-on module; little endian. Program executes under DEMON; erases and programs flash memory. 3.4.1 Boot Program Resize to 2 Kbytes The initial boot program that is loaded into the on-chip SRAM must be exactly 2 Kbytes. If the BOOTAMD0 program is compiled and linked, the size must be adjusted to meet this parameter. To do this, simply load the program with DEBUG into memory, adjust CRX to 800, and write back the file. The following example code shows this sequence: DEBUG BOOTAMD0 -RCX < 800 -W NOTE: The memory map of all memory selected by CS0 through CS5 (and internal CS6 and CS7 areas) is reversed: Bank 0 (CS0) is located at 0x7000 0000 during boot. 10 EVALUATION BOARD APPLICATION NOTE v1.0 April 1997 CL-PS7111 Evaluation Kit -- User Manual 3.4.2 Boot Program File Format Once BOOTAMD0 has been loaded into SRAM and given control by the boot loader. The program prompts for the dile name containing the binary. The format for this file is: q q 4 bytes - first address (Little Endian) 4 bytes - length of data in bytes (Little Endian) The following example code is a script for adding header and length information to the top of the file using DOS debug commands: e f8 00 00 00 00 00 c0 00 00 rcx c008 nroml.bin wcs:f8 q 3.4.3 Booting with Start Up Sequence from the Serial Port In this mode, the on-chip boot program loads the boot code into the on-chip SRAM from serial port 1, then loads a program (such as the debug monitor) into flash. The following is a procedure to load the boot program. 1. Install the ARM software development toolkit. 2. (DOS only) Run RECONFIG from the ARM\PC386 directory. a) Select the ARMSD setup and the little endian serial port at 9600 baud. b) Exit and save this configuration. 3. Set the BOOTEN jumper, W15. 4. Connect the PC from which to download the boot code to the serial port 1. 5. Select 9600 baud. 6. Run a terminal program, such as Winterm. 7. Power down. 8. Power up. 9. Press the WAKEUP button, S1. At this point the `<' character will have been received from serial port 1. 10. Send the file BOOTAMD0 after receiving `<'. After 2 Kbytes are sent, `>' appears on screen. The downloaded program begins executing at address 0000 0000 from the on-chip SRAM. The program also prompts that it is ready to receive data. Send the code to download (such as ROMU2L) or any other program (for example, the operating system). The binary file must contain a header, the length, the binary file, and the destination start address to be loaded. See Section 3.4.2 on page 11. April 1997 APPLICATION NOTE v1.0 EVALUATION BOARD 11 CL-PS7111 Evaluation Kit -- User Manual 11. Switch W15 to N (normal boot). 12. Power down. 13. Power up. 14. Press the WAKEUP button, S1. At this point a banner message appears followed by the ARMSD: prompt. 3.4.4 Start Up Sequence Using Preinstalled Debug Monitor (DEMON) Use the following procedure to load the start up sequence using the preinstalled debug monitor, DEMON. 1. Install the ARM software development toolkit. 2. (DOS only) Run RECONFIG from the ARM\PC386 directory. a) Select ARMSD setup and the little endian serial port at 9600 baud. A higher baud rate can be used, but ARMSD is not reliable above 9600 baud on certain host systems. b) Exit and save the configuration. 3. Connect the serial port labeled SERIAL 2 with the supplied null-modem cable to one of the PCs serial ports. 4. Connect the power supply. 5. Launch ARMSD on the PC. a) If connected to Port 1 (COM1) type: ARMSD b) If connected to Port 2 (COM2) type: ARMSD -p 2 6. Press the RESET button, S2. 7. Press the WAKEUP button, S1 If system does not wake up, press the RESET button followed by WAKEUP. Wait a few moments for the debug monitor to complete memory test and initialization. Then the initial message reporting the DRAM size (0x20 0000) and the debug monitor version appears. Ensure that the memory size is correct. If the sign-on message does not appear, but instead there is an 12 EVALUATION BOARD APPLICATION NOTE v1.0 April 1997 CL-PS7111 Evaluation Kit -- User Manual 3.4.5 Configure the ARM Debugger for Windows(R) (Tool v2.1) The ARM debugger for Windows (ADW) must be configured for remote target. Use the following procedure. 1. Choose Configure Debugger from the Option menu. The Configurre Debugger Option menu opens. 2. Click the Target button to move to the Remote Debug Interface window. 3. Click Add. 4. Select remote_d from the Target Environment window. 5. Click Configure. 6. Select the desired baud rate in the Configure window. April 1997 APPLICATION NOTE v1.0 EVALUATION BOARD 13 CL-PS7111 Evaluation Kit -- User Manual 3.5 Board Layout The following two schematic diagrams present board layout recommendations. Please contact Cirrus Logic for the latest schematic diagrams. 14 EVALUATION BOARD APPLICATION NOTE v1 0 April 1997 CL-PS7111 Evaluation Kit -- User Manual April 1997 APPLICATION NOTE v1.0 EVALUATION BOARD 15 CL-PS7111 Evaluation Kit -- User Manual 16 EVALUATION BOARD APPLICATION NOTE v1.0 April 1997 CL-PS7111 Evaluation Kit -- User Manual The following lists the reference designators used in the schematics: Designator W J S TP Part Permanent selectors, normally the solder bridges Jumper or connectors Switches Test points The following lists the reference designators for jumpers and solder bridges: Designator W1 W2 W3 W4 W6 W7 W8 W11 W12 W13 W14 W15 Function VEE voltage selection VEE voltage selection aLAW/uLAW selection PC Card data bus power selector Bank 0 select 16/32 bit VEE voltage selection VEE voltage selection Boot ROM enable for 32-pin DIP option Interrupt selection for PC Card -CAS0 -CAS1 Boot select The following lists the reference designators for connectors: Designator J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 Function 17-pin LCD connector 11-pin LCD connector Battery connector Keyboard connector Optional speaker Ear phone connector Microphone connector IR module 1.3 mm external supply connector Expansion connector 68-pin PC Card connector Serial Port 1, RS-232 levels Expansion ROM connector (not populated) Serial Port 2, TTL LCD ZIF connector for Alps panels Touch panel 88-pin JEIDA, DRAM module April 1997 APPLICATION NOTE v1.0 EVALUATION BOARD 17 CL-PS7111 Evaluation Kit -- User Manual Designator (cont.) J19 J20 J21 J22 J23 J24 J25 Function L/A control signals L/A Data[15:0] L/A Address[15:0] L/A Address[27:16] L/A Data[31:16] LCD signals header Serial Port 2, RS-232 levels The following lists the reference designators for the switches: Designator S1 S2 Function Manual wake-up User reset 3.6 Memory Architecture The memory consists of two banks of flash and one bank of 16-bit wide DRAM (each 2 Mbytes). Additional DRAM can be added on a JEIDA memory module. The boot flash can be 16-bits wide; however, 16-bit flash memory cannot be written to because of the way the AMD flash is reprogrammed by applying a sequence of memory addresses and data. An optimal configuration uses 8-bit wide memory. If 16-bit wide memory is required, use memory with VPP-enabled programming. The standby current of the complete system is determined by the DRAM current in self-refresh mode. This is why a low refresh current is important. Additional RAM can be placed on the add-on debug module using a serial EEPROM. 18 EVALUATION BOARD APPLICATION NOTE v1.0 April 1997 CL-PS7111 Evaluation Kit -- User Manual 3.6.1 Memory Map in Operating Mode Physical Address Space 0000 0000 0000 0000-001F FFFF 1000 0000-101F FFFF 0000 3000 0000 4000 3000 0000-300F FFFF 4000 0000-43FF FFFF 4400 0000-47FF FFFF 4800 0000-4BFF FFFF 6000 0000-6000 07FF 7000 0000-6000 007F 8000 0000-8000 1800 C000 0000-C001F FFFF C000 0000-C001 FFFF C002 0000-C002 7FFF C002 8008 C002 8000-C01F FFFF a b Description Starting address of debug monitor 2-Mbyte flash; 3 V Bank 0 2-Mbyte flash; 3 V Bank 1 Location of the character set Page tables External serial port (expansion space) PC Card attribute space; 8-bits wide PC Card memory space; 8/16 bits (byte/word addressable) PC Card I/O space; 8/16 bits On-chip SRAM; 2 Kbytes On-chip boot code; 128 bytes CL-PS7111 registers a 2-Mbyte DRAM LCD buffer - default address b Work area for debug monitor Applications program start address DRAM used by softwareb Refer to the CL-PS7111 Data Book for complete register descriptions. The DRAM is a 16-Mbit DRAM organized as 12 row addresses and 8 column addresses. In this non-square configuration, the memory controller splits the memory into eight 256-Kbyte segments with equal size gaps between the segments. To get a contiguous memory segment, use the MMU to map pages of physical memory into the virtual address space of the CPU. The page tables starting at location 0x4000 describe page addresses, protection status, and cacheability of individual pages. 3.6.2 Memory Map in Boot Mode The memory map is different if the system is booted when the MEDCHG signal is low. All memory spaces are selected through CS0..CS5; the on-chip memory space in address space CS7 and the SRAM at CS6 are reversed. Therefore, the boot code appears at location 0x0000 0000, while the on-chip SRAM appears at 0x1000 0000. The DRAM and on-chip registers are not remapped. April 1997 APPLICATION NOTE v1.0 EVALUATION BOARD 19 CL-PS7111 Evaluation Kit -- User Manual 3.7 I/O Port Allocation Table 3-3 shows allocation, pin configuration, and function for the I/O port. Table 3-3. Port PA[7:0] PB0 PB1 Port Allocation Pin Configuration Drive Standard Standard Standard Reset Sate Input Input Input Direction I I/O I/O Signal ROW[7:0] PB0 PB1 Description Keyboard row input pulled down by R81 resistor network. PRDY of PC Card controller CL-PS6700. TSMY drive. Volume control: PB2 Input Standard O PB2 0 = high volume 1 = low volume PC Card VPP: PB3 Input Standard O PB3 0 = enable 12 V 1 = enable 5 V PC Card power shutdown converter: PB4 Input Standard O PB4 0 = turn off PC Card power 1 = turn on PC Card power Power telephone codec MSM7702: PB5 Input Standard O PB5 0 = turn off codec 1 = turn on codec Power speaker amplifier: PB6 Input Standard O PB6 0 = turn off amplifier; digital input on 1 = turn on amplifier; digital input off Power A/D converter: PB7 Input Standard O PB7 0 = turn off A/D converter 1 = turn on A/D converter PD0 Output-low Standard O RTS Request to send output -- active-high. PC Card voltage select: PD1 Output-low Standard O DTR 0 = enable 5 V 1 = enable 3.3 V Serial port off -- active-low: PD2 a Output-low Standard O PD2 0 = disable RS-232 driver 1 = enable RS-232 driver PD3 PD[7:4 ] Output-low Output-low Standard Standard I/O O PD3 PD4..7 Expansion connector. LCD contrast control. LCD Display Signal: PE0 Input Standard O PE0 0 = disable; LCD off 1 = enable; LCD on 20 EVALUATION BOARD APPLICATION NOTE v1.0 April 1997 CL-PS7111 Evaluation Kit -- User Manual Table 3-3. Port Port Allocation Pin Configuration (cont.) Drive Direction Signal Description IR transmit enable: Reset Sate PE1 Input Standard O PE1 0 = enable 1 = disable PE2 a Input Standard O PE2 TSPX drive panel. Since the on-chip boot program expects data on serial Port 1, the RS-232 driver must be enabled. U20 is enabled by port PD2, which is an output after power up. The optimal solution is to use PB2 with a pull-up resistor so that the RS-232 driver is enabled, and use PD2 as volume control port. 3.8 Analog-to-Digital Converter A 10-bit A/D converter, MAX148, is used in the board design. This is actually a 12-bit converter and must be set up for 128-kHz ADCCLK, a frame length of 24, and unipolar input. Connect a potentiometer or a waveform generator on R47 with a maximum amplitude of 1.5 V. For further information, refer to the MAX148 data sheet. 3.9 LCD Interface There is no industry standard for an LCD panel pinout. Operating voltages, as well as interface connectors, vary from supplier to supplier. One of the more common pinouts is J2 with pin assignments, as shown in Table 3-4. Table 3-4. Pin# 1 2 3 4 5 6 7 8 9 10 11 J2 Connector Pins Symbol FRM CL1 CL2 PE0 VDD GND VEE D0 D1 D2 D3 Signal Name Frame Signal Line Clock Shift Clock LCD (on signal if high) 3.3 V Frame Signal Selectable from approximately +30 V to -30 V Data 0 Data 1 Data 2 Data 3 April 1997 APPLICATION NOTE v1.0 EVALUATION BOARD 21 CL-PS7111 Evaluation Kit -- User Manual The panels shown in Table 3-5 can be connected and are available from Cirrus Logic upon request. These two panels are 5 V and are for evaluation only. Contact your supplier for availability of 3.3-V panels. Table 3-5. Compatible Panels Supplier Sharp Sharp (minor cable adjustment required) Type LM48014F LM320081 Size 480 x 320 320 x 240 VDD 5V 5V VEE +28 V -18 V VEE can be selected and the voltage can be adjusted under software control, as described in Section 3.8. 3.10 J1 Connector Pinout A second interface connector, J1, is provided for a custom panel from Cirrus Logic. This panel is 240 x 100 pixels and operates on a single 3.3-V supply. This panel uses the M signal (AC modulation). Connect the Cirrus Logic LCD panel (240 x 100) on J1 as shown in Table 3-6. Table 3-6. Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a J1 Connector Pins Symbol VDD D0 D1 D2 D3 GND FRM GND CL1 GND CL2 GND M PE0 n/c a n/c n/c Signal Name 3.3V Data 0 Data 1 Data 2 Data 3 Ground Frame Ground Line Clock Ground Shift Clock Ground Modulation LCD On - - - `n/c' indicates a pin that is a no connect. 22 EVALUATION BOARD APPLICATION NOTE v1.0 April 1997 CL-PS7111 Evaluation Kit -- User Manual 3.11 J24 Connector Pinout The J24 connector is compatible with following Alps panels: q q q q q KHABAA902A, 320 x 240 KHABAA901A, 320 x 240 KHABFC901A, 160 x 240 KHABFA901A, 240 x 160 KHABBB904A, 480 x 320 Table 3-7. J24 Pin Connections Symbol V5 V2 VEE VDD FRM GND CL1 GND M PE0 CL2 V4 V3 D3 D2 D1 D0 Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Signal Name Bias Supply Voltage Bias Supply Voltage LCD Driver Supply Voltage Logic Supply 3.3 V Frame Signal Ground Line Clock Ground AC Signal Display on Signal (1 = on) Shift Clock Bias Supply Voltage Bias Supply Voltage Data 3 Data 2 Data 1 Data 0 3.12 Codec The schematics and bill of materials in this document shows the part number of the codec, MSM7702. The codec interface is directly compatible without interface logic. The power amplifier, MSC1192MS, must be turned off at the end of every transmission to silence the speaker and conserve power. The gain of the microphone can be adjusted by the R6, ~100-k resistor. A buzzer is optional. Since the buzzer output goes into the digital input of the power amplifier, it is not required if a speaker is present. To enable the digital input, the -STDY input of the MSC1192MS must be high. April 1997 APPLICATION NOTE v1.0 EVALUATION BOARD 23 CL-PS7111 Evaluation Kit -- User Manual 4. DESIGN FILES 4.1 System Board The schematics can be found in one of two OrCAD formats. The design database file is provided as an ASC file that can, if necessary, be converted into other formats. The following are the absolute paths of the zipped schematic files provided in this kit. Path and Filename \schematic\EVAL7111.SCH \schematic\EVAL7111.DSN \schematic\EVAL7111.LIB \schematic\EVAL7111.BOM \layout\EVAL7111.ASC \layout\BATCHL.DAT File Type and Contents Orcad 386+ format use library REF7110D.LIB Orcad Capture for Windows Format Orcad Library file Bill of Materials PADS PERFORM v.6 ASC file PADS Batch file to generate gerber files 4.2 Key Board The following are the absolute paths of the schematic files available through the Cirrus Logic BBS. Path and Filename \schematic\KEYB.SCH \schematic\KEYB.DSN \schematic\KEYB.LIB \layout\KEYB.ASC File Type and Contents Orcad 386+ format use library REFDEBUG.LIB Orcad Capture for Windows Format Orcad Library file PADS PERFORM v.6 ASC file 5. BOOT CODE AND DEMON FILES For a complete listing of files, see the README file on the BOOT floppy disk. 24 DESIGN FILES APPLICATION NOTE v1.0 April 1997 CL-PS7111 Evaluation Kit -- User Manual 6. POWER SUPPLY DESIGN The power supply design consists of a number of individual units that provide power from two AA batteries, as well as an AC/DC adapter that ranges from 6 to 12 V. Backup during sleep mode can be provided from a gold capacitor, C33, that keeps the 32-kHz oscillator active, or from a lithium battery with some minor rework required. NOTE: All power rails must be supplied with power. It is not recommended to simply provide power to the realtime clock oscillator while core and I/O are turned off. The power supply is divided into following units: q q q q q q Step-up converter Step-down converter Backup supply: gold capacitor or lithium battery PC Card supply VEE for LCD VPP for PC Card There is also a bias generator for the Alps LCD panels. This bias generator divides VEE appropriately to supply V2..V5 for the panel. The CL-PS7111 is in any of three modes: 1) Boot mode Internal boot ROM at location 0x0000 0000 loads 2 Kbytes of data from UART1 at 9600 baud. The memory is remapped. 2) Operating modes: a) Run mode: CPU on, LCD on b) Idle mode: CPU off, LCD refresh on c) Standby mode: CPU off, LCD refresh off, and DRAM in the self-refresh state 3) Test modes NOTE: There are several test modes that are described in detail in the CL-PS7111 Data Book. 6.1 Step-up Converter Connector J3, Pin Header Pin 1 Pin 2 VBATT GND Battery voltage between 2-3 V (target) Use FET U26 with low UGS (such as Si6426) The main power should be provided from two alkaline AA batteries. The supply is in the range of 2-3 V, depending on the remaining charge. The step-up converter, U24 (MAX608), can be turned off during power down only when the CL-PS7111 is in the Idle mode. April 1997 APPLICATION NOTE v1.0 POWER SUPPLY DESIGN 25 CL-PS7111 Evaluation Kit -- User Manual In Idle mode, the power required for the entire system is largely determined by the power-down current of the DRAMs, which can be put into the self-refresh state. Typically, the leakage current of the entire system is between 50-300 A. An inverted RUN signal powers up the MAX608. Note that the reference voltage is also off in Standby mode. This is because the debug UART add-on module and the associated RS-232 driver (MAX212) are still running during that time. Since the RUN signal starts just prior to the execution of the first instruction (in 18-MHz operation), it is important that no accesses to memory or I/O devices occur until full power is restored. To do this, execute out-of-cache and set up a secondary `wakeup' source after which the CPU can make memory references. In 13-MHz operation with the PLL bypassed, the wakeup time is reduced from 10 ms instead of the 250 ms required for 18-MHz operation. This allows toggling at a fast rate in and out of the Standby state. 6.2 Step-Down Converter Connector J9, 1.3 mm Circular Connector Pins 1 and 3 Pin 2 Sleeve Center VEXT GND Power from AC/DC converter (6 to 12 V) The step-down converter, LM1651, operates from anywhere from VDD to 16 V and is also referred to as the External power source. If VEXT power is on, the input, -EXTPWR, is active to the CL-PS7111. This protects the CPU from exiting the Standby state if the NPWRFL signal is active. The following sections provide a detailed description of the four pins on the CL-PS7111 that are dedicated to battery power management. MEDCHG/-BOOTEN This input detects to a switch that signals that a PC Card (or other I/O card) is being removed. This input is deglitched so that a mechanical switch can be used. When this input is low at power up, the CL-PS7111 boots up from the on-chip ROM and loads 2 Kbytes of data from UART 1 at 9600 baud. BATOK This signal is derived from a comparator that is set to switch when the main battery dies. A transition to low generates a FIQ interrupt. The O/S must ensure that the system powers down into Standby mode so as to not entirely drain the battery. Logic integrated in the CL-PS7111 prevents the system from starting up unless the power fail condition (NPWRFL not active) is removed. NEXTPWR This input must be driven when an external power supply, other than the main battery, is powering the system. Only when this input is high and NPWRFL is not active will the system exit Standby mode. This prevents the system from attempting to wake up when the main battery is dead or fatally drained. BATCHG This input, when asserted, will not generate an interrupt. It signals that there is no battery present. It can be generated by an external comparator that senses battery voltage. NPWRFL This input immediately places the system in Standby mode. It will first sense that the DRAM access is complete and placed in self-refresh mode and reset the CPU. 26 POWER SUPPLY DESIGN APPLICATION NOTE v1.0 April 1997 CL-PS7111 Evaluation Kit -- User Manual 7. MEASURING CL-PS7111 POWER CONSUMPTION The current supply of the CL-PS7111 is separated into I/O (pad), core, 32-kHz oscillator, and 3.6864-MHz PLL oscillator nodes. The current drawn by the CL-PS7111 can be observed by a mA-meter connected to L1, L4, and L5. These are usually bridged by solder bumps. No filters are required in the supply. Use the POWER program to cycle through the different power states. The mA-meter can be connected to solder pads L4 and L5 to measure the oscillator and core currents, respectively. To measure the 32-kHz oscillator current, a mA-meter is required in place of D6. C33 must be removed so as not to measure the leakage current. Ensure that the meter switch is uninterrupted when changing range. The current can change by three orders of magnitude. The current drawn depends on how individual modules are activated. Some typical values are shown in Table 7-1. The values may change depending on the programming conditions. Table 7-1. Typical Current Values at Various Conditiona Name VDDE VCORE V32K VOSC Node Name I/O Core 32-kHz oscillator 3.6864-MHz PLL oscillator Total approximate: Run <15 mA <3 mA <10 A <1.2 mA <30 mA Idle <1 mA <2 mA <10 A <1.2 mA <15 mA Standby <5 A <1 A <10 A <1 A <17 A April 1997 APPLICATION NOTE v1.0 MEASURING CL-PS7111 POWER CONSUMPTION 27 CL-PS7111 Evaluation Kit -- User Manual 8. DC-DC CONVERTER The CL-PS7111 device provides dedicated support for DC-DC conversion through two duty-cycleprogrammable 96-kHz clocks. One set of clocks can be used for keeping a constituent VEE supply voltage for the LCD panel; the second set can be used to generate the programming voltage VPP . These clocks can also be used for the voltage of the backlight. The schematic in Figure 8-1 is for positive and negative VEE control circuitry. VEE must be closely controlled over a relatively wide range to adjust for voltage and temperature variations. The reference board is designed to select positive or negative VEE through the proper setting of solder joints W1, W2, W7, and W8. The four output ports, PD[7:4] can change VEE with software control. The pump ratio duty cycle is selected so that sufficient current is provided and the inductor is not going into saturation. In the example in Table 8-1, a pump ratio of four was sufficient. Table 8-1. Resistor R75 R53 R54 R55 VEE Control Circuitry Function Pull-down resistor for positive VEE . Pull-up resistor for LM339 open-drain output. Selects a voltage at the + terminal of the comparator where the feedback output switches off (high) and turns off the Drive output. Selects the voltage level on + input of comparator to apply to VREF (1.5 V); for 28 volts, R55 = 22 k. Adjust this resistor to icrease/decrease the voltage range; a lower value increases the voltage range. This resistor network enables VEE to be programmed under software control. All outputs low indicate that VEE is at maximum. Turning on the outputs increases the voltage at the comparator, decreasing VEE . R62 to R65 8.1 Setup Procedure Assuming that the nominal VEE voltage for a given LCD is 28 V and the range is from 27-29 V do the following to ensure sufficient contrast control range: 1. Connect a load resistor at C2 to force application of a 2-5 mA current (or whatever the typical value for the panel is). 2. Program the Pump Control register to 5. 3. Set PD[7:4] to high. 4. Set R55 so that minimum VEE is 27 V. 5. Set PD[7:4] to `1111'; VEE should exceed 29 V. 28 DC-DC CONVERTER APPLICATION NOTE v1.0 April 1997 CL-PS7111 Evaluation Kit -- User Manual VDD VDD L3 47uH D12 +VEE 1N5818 TR1 C2 2.2u C78 10uF R54 330k VREF 4 GND GND 5 LM339 R55 R C44 100n 3 R65 R64 R63 R62 806k 392k 200k 100k 1 2 NPN 3 1 2 R53 100k U19 R74 76 100 DRIVE1 75 82 DRIVE0 DRIVE1 FB0 FB1 GND U13A 2 R75 100k FB1 80 GND 56 55 54 53 PD4 PD5 PD6 PD7 GND GND CL-PS7111 Figure 8-1. CL-PS7111 DC-DC Converter for Positive VEE Measured VEE values for a duty ratio of 5 are shown in Table 8-2. Table 8-2. Duty Ratio = 5 Pump Ratio 5 Port PD[7:4] [V] 0 1 2 3 4 5 6 7 30.8 29.04 27.2 25.4 23.6 21.9 20.0 18.3 [V] 31.12 29.34 27.48 25.70 24.0 22.18 20.32 18.56 April 1997 APPLICATION NOTE v1 0 DC-DC CONVERTER 29 CL-PS7111 Evaluation Kit -- User Manual Table 8-2. Duty Ratio = 5 (cont.) Pump Ratio 5 Port PD[7:4] [V] 8 9 A B C D E F 16.2 14.5 12.7 10.98 9.27 7.53 5.7 4.06 [V] 16.45 14.68 12.85 11.1 9.33 7.57 5.79 4.06 Measured VEE values for a duty ratio of 2 are shown in Table 8-3. Table 8-3. Duty Ratio = 2 Pump Ratio VEE [V] 3.74 18.92 26.18 26.83 27.06 27.19 27.28 27.34 27.39 27.44 27.48 27.51 27.53 27.54 27.58 27.59 Port PD[7:4] = 2 0 1 2 3 4 5 6 7 8 9 A B C D E F 30 DC-DC CONVERTER APPLICATION NOTE v1.0 April 1997 CL-PS7111 Evaluation Kit -- User Manual 8.1.1 Negative VEE Table 8-4 shows the resistors required for the control circuitry on negative VEE . Figure 8-2 is a sample schematic for a DC-DC converter on negative VEE . Table 8-4. Resistor R73 R53 R54 R56 Negative VEE Control Circuitry Function Pull-up resistor for negative VEE . Pull-up resistor for the LM339 open-drain output. Selects a voltage at the terminal of the comparator where the feedback output switches off (high) and turns off the Drive output. Selects the voltage level on the input of comparator to apply to VREF (1.5 V). This resistor network allows VEE to be programmed under software control. All outputs low indicate that VEE is at maximum. Turning on the outputs increases the voltage and therefore decreases VEE . R62..65 GND VDD L3 47uH D12 -VEE 1N5818 TR1 PNP R53 100k U19 R74 76 100 DRIVE1 75 82 DRIVE0 DRIVE1 FB0 FB1 C2 2.2u C78 10uF R54 330k VREF 11 13 0 VDD U13D FB1 80 GND GND 10 LM339 R56 R C44 100n 0 R65 R64 R63 R62 806k 392k 200k 100k R73 10k VDD 56 55 54 53 PD4 PD5 PD6 PD7 VDD GND CL-PS7111 Figure 8-2. CL-PS7111 DC-DC Converter for Negative VEE April 1997 31 APPLICATION NOTE v1 0 DC-DC CONVERTER CL-PS7111 Evaluation Kit -- User Manual 8.1.2 VPP Control VPP is controlled by DRIVE0. The circuitry is designed to turn on with 5 or 12 V. If PD6 is high, the transistor, TR4, turns on.This determines VPP for 12 V by switching R57 in parallel to R59. If TR4 is turned off, VPP is set to 5 V. Turning the pump ratio to 0 turns off the U21 switch, and VPP is effectively turned off. The DC-to-DC pump ratio (PR), if set to 5, yields adequate power. Table 8-5. VDD 3.6 V 3.6 V 3.6 V DC-DC Pump Ratio = 5 PR 4 5 A PB3 = 0 5.6 V 5.78 V 6.8 V PB3 = 1 12.78 V 12.98 V 14.22 V Load Resistor 1.2 k 1.2 k 1.2 k 32 DC-DC CONVERTER APPLICATION NOTE v1.0 April 1997 CL-PS7111 Evaluation Kit -- User Manual 9. PC Card (PCMCIA) Interface The PC Card interface consists of the single-chip controller, CL-PS6700, that provides a fully v2.1-compliant PC Card interface, including software-controlled DMA and mixed-voltage operation on a small-footprint package. During Sleep mode, this controller is not drawing any measurable current, while still signaling a card change condition. Two interrupts could be used going to the CL-PS7111, but for all examples in this application, only PIRQ_L is connected to -EINT1. 9.1 PC Card Power Switches at Multiple Points First, turn the power on for converter U1 and set for 5-V operation (see PB4 and PD1). Next, VPP must be set to 5 V, as controlled by the on-chip DC-DC converter. Finally, to turn on the appropriate switch or switches, the MOSFET switch, U28, must be controlled by writing the Power Management register of the CL-PS6700. Table 9-1. VPP 5V 5V 12 V 12 V Switch Settings VPC 5V 3V 5V 3V S4 0 1 0 1 S3 1 0 1 0 S2 VPC VPC VPC VPC S1 0 0 1 1 The CL-PS6700 operates on split power planes to isolate the PC Card slot from the system. There are a number of internal pull-up resistors and logic that must operate if power to the CL-PS6700 is off. This also requires that the applied VDD_HI signal is higher than the card voltage or VDD , respectively. A Schottky diode, D16, in the power path assures that the VDD_HI signal selects the higher of either the card voltage (3.3 or 5 V) or VDD . 9.1.1 PC Card Power In most applications, a 200-mA power source is sufficient to drive a PC Card. To optimize the requirement, the following exchangeable converters can be used: q q q MAX858 -- up to 50 mA at 5 V MAX856 -- up to 100 mA at 5 V MAX756 -- up to 200 mA at 5 V April 1997 APPLICATION NOTE v1.0 PC Card (PCMCIA) Interface 33 CL-PS7111 Evaluation Kit -- User Manual 9.2 CL-PS7111-to-CL-PS6700 Interconnect Diagram SYS_RES_L RESET_L EXPCLK NCS[4] WRITE PCLK PCE_L PTYPE I/O POWER = V3V-O I/O POWER = V5V-O CL-PS7111 NEINT2 PIRQ_L RUN PSLEEP_L D[15:0] MD[15:0] Figure 9-1. CL-PS7111-to-CL-PS6700 Interconnect Diagram 9.3 Interrupts The two interrupt outputs of the CL-PS6700 are open-drain and must to be pulled up. An interrupt in the CL-PS6700 can be promoted to FIQ status (that is, the status change may cause a fast interrupt or one separated out for fast interrupt response). Connect W12 to wire the FIQ output on the board to the external -EXFIQ interrupt. Since -EXFIQ can also be used by the expansion board, ensure it is being driven by an open-drain output to make the wire OR connection. 9.4 DMA Support The PDREQ_L output of the CL-PS6700 is pulled high on the board (open-drain output). If DMA is required, connect this output to an interrupt on the CL-PS7111. Then DMA can be supported by software emulation (use -EXFIQ). PDREQ_L can also be used as a GPIO. 9.5 Power Down Whenever the CL-PS7111 enters Standby mode, the CL-PS6700 enters Power-Down mode. This is because the RUN signal is connected to the PSLEEP_L input. Ensure that there are no pending transactions before the CL-PS7111 enters Standby mode and that the transaction queue in the CL-PS6700 is empty. Use any of the GPIO ports instead of RUN. CL-PS6700 PB[0] PRDY 34 PC Card (PCMCIA) Interface APPLICATION NOTE v1.0 April 1997 CL-PS7111 Evaluation Kit -- User Manual 9.6 Clocks When the CL-PS7111 is operating at 18 MHz, EXPCLK is driven out as the clock for the CL-PS6700. The clock can be disabled through the Memory Configuration register. If the CL-PS7111 is operating at 13 MHz, an external oscillator provides the clock on EXPCLK to the CL-PS6700. Since the 13-MHz clock can be disabled (through the RUN/CLKEN output during standby mode), ensure that there are no pending transactions. April 1997 APPLICATION NOTE v1.0 PC Card (PCMCIA) Interface 35 CL-PS7111 Evaluation Kit -- User Manual Appendix A A.Source Address Locator Data sheets and application notes can be downloaded from your board supplier web site. Abracon Corporation(R): www.abracon.com Accelerated Technology, Inc.(R): www.atinucleus.com Alps Electric(R): www.alps.com AMD(R): www.amd.com AMP(R): www.amp.com ARM Ltd.(R): www.arm.com Cygnus(R): www.cygnus.com Maxim(R): www.maxim-ic.com Molex(R): www.molex.com Oki America, Inc.(R): www.oki.com Temic(R): www.temic.com Supplier of crystals and oscillators Supplier of the Nucleus O/S Supplier of LCD panels and keyboards Supplier of flash memory Supplier of connectors Supplier of CPU support tools Suppler of development software tools Supplier of power ICs Supplier of connectors Supplier of codecs Supplier of Power MOSFET 36 PC Card (PCMCIA) Interface APPLICATION NOTE v1.0 April 1997 CL-PS7111 Evaluation Kit -- User Manual Appendix B B.Bill of Materials The bill of materials is in the DEB7111.BOM file. CL-PS7111 EVAL Board DEB7111.SCH Revision: B Bill of Materials Item 1 2 Revised: January 8, 1997 January 14, 1997 Quantity 1 26 Reference CH1 C1 C10 C15 C16 C17 C19 C20 C21 C29 C31 C32 C35 C40 C42 C47 C49 C58 C62 C64 C65 C67 C69 C70 C83 C84 C96 Part 100 pF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF April 1997 APPLICATION NOTE v1.0 PC Card (PCMCIA) Interface 37 CL-PS7111 Evaluation Kit -- User Manual CL-PS7111 EVAL Board DEB7111.SCH Revision: B Bill of Materials (cont.) Item 3 Revised: January 8, 1997 January 14, 1997 Quantity 4 Reference C2 C3 C61 C82 Part 2.2 F 2.2 F 2.2 F 2.2 F 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 47 pF 47 pF 47 pF 47 pF 1 nF 1 nF 1 nF 4 25 C4 C5 C6 C7 C8 C9 C11 C12 C13 C14 C22 C23 C24 C30 C38 C39 C43 C44 C45 C48 C63 C66 C68 C73 C79 5 4 C18 C60 C93 C94 6 13 C25 C26 C27 38 PC Card (PCMCIA) Interface APPLICATION NOTE v1.0 April 1997 CL-PS7111 Evaluation Kit -- User Manual CL-PS7111 EVAL Board DEB7111.SCH Revision: B Bill of Materials (cont.) Item Quantity Reference C28 C36 C50 C51 6 (cont.) C52 C53 C54 C55 C56 C57 7 8 9 1 2 4 C33 C34 C87 C37 C41 C74 C75 10 11 12 1 2 3 C59 C72 C71 C76 C77 C81 13 14 15 16 17 18 2 2 2 2 1 4 C80 C78 C86 C85 C88 C89 C90 C91 C92 C97 C98 C99 C100 Revised: January 8, 1997 January 14, 1997 Part 1 nF 1 nF 1 nF 1 nF 1 nF 1 nF 1 nF 1 nF 1 nF 1 nF 0.22 F 1 F 1 F 47 F 47 F 47 F 47 F 15 pF 0.33 F 0.33 F 33 F 33 F 33 F 4.7 F 4.7 F 0.47 F 0.47 F 0.1 F 0.1 F 3.3 F 3.3 F 1 F/16 V 4.7 F/35 V 4.7 F/35 V 4.7 F/35 V 4.7 F/35 V April 1997 APPLICATION NOTE v1.0 PC Card (PCMCIA) Interface 39 CL-PS7111 Evaluation Kit -- User Manual CL-PS7111 EVAL Board DEB7111.SCH Revision: B Bill of Materials (cont.) Item 19 20 Revised: January 8, 1997 January 14, 1997 Quantity 1 4 Reference D2 D3 D4 D5 D7 Part MAX809R BAV70 BAV70 BAV70 BAV70 1N5817 1N5817 1N5817 1N5817 1N5817 1N4148 1N4148 14 V 1N5818 BAT54C ZIF17 ZIF17 ZIF11 HDR2 HDR25 JMP2 JMP2 JMP2 JMP2 JMP2 JMP2 JMP2 JMP2 PHONOSW TFDS3000 CONAC HDR25X2 PCMCIA68 AMP557908-1 AMP557908-1 SM30 21 5 D6 D10 D13 D14 D15 22 23 24 25 26 27 28 29 30 2 1 1 1 2 1 1 1 8 D8 D9 D11 D12 D16 J1 J15 J2 J3 J4 W3 J5 W7 J7 W8 W11 W12 W15 31 32 33 34 35 36 37 1 1 1 1 1 2 1 J6 J8 J9 J10 J11 J12 J25 J13 40 PC Card (PCMCIA) Interface APPLICATION NOTE v1.0 April 1997 CL-PS7111 Evaluation Kit -- User Manual CL-PS7111 EVAL Board DEB7111.SCH Revision: B Bill of Materials (cont.) Item 38 39 40 41 42 Revised: January 8, 1997 January 14, 1997 Quantity 1 1 1 1 5 Reference J14 J16 J17 J18 J19 J20 J21 J22 J23 Part HDR3 4HEADER JEIDA88 HDR2x2 HPPOD20 HPPOD20 HPPOD20 HPPOD20 HPPOD20 HDR17 SPEAKER BUZZER FERRITE FERRITE FERRITE FERRITE 47 H 47 H 47 H 22 H 22 H 15 H 1 k 1 k 1 k 1 k 1 k 5 100 k 100 k 100 k 100 k 100 k 100 k 100 k 100 k 43 44 45 46 1 1 1 4 J24 LS1 LS2 L1 L4 L5 L10 47 3 L2 L3 L7 48 49 50 2 1 5 L8 L6 L9 R1 R36 R96 R97 R98 51 52 1 24 R2 R3 R9 R11 R12 R13 R14 R16 R25 April 1997 APPLICATION NOTE v1.0 PC Card (PCMCIA) Interface 41 CL-PS7111 Evaluation Kit -- User Manual CL-PS7111 EVAL Board DEB7111.SCH Revision: B Bill of Materials (cont.) Item Quantity Reference R34 R35 R39 R41 52 (cont.) R48 R50 R51 R52 R53 R56 R59 R60 R62 R67 R68 R71 53 16 R4 R7 R21 R24 R27 R29 R43 R44 R45 R69 R73 R75 R89 R90 R91 R95 54 55 2 4 R57 R6 R8 R33 Revised: January 8, 1997 January 14, 1997 Part 100 k 100 k 100 k 100 k 100 k 100 k 100 k 100 k 100 k 100 k 100 k 100 k 100 k 100 k 100 k 100 k 10 k 10 k 10 k 10 k 10 k 10 k 10 k 10 k 10 k 10 k 10 k 10 k 10 k 10 k 10 k 10 k 47 k 47 k 10 10 42 PC Card (PCMCIA) Interface APPLICATION NOTE v1.0 April 1997 CL-PS7111 Evaluation Kit -- User Manual CL-PS7111 EVAL Board DEB7111.SCH Revision: B Bill of Materials (cont.) Item Quantity Reference R87 R92 56 57 1 1 4 R10 R70 R15 R28 R30 R31 58 59 60 61 62 63 2 1 1 2 1 5 R17 R19 R18 R20 R22 R72 R23 R26 R32 R40 R42 R49 64 4 R37 R61 R74 R94 65 66 67 68 69 70 71 72 73 1 1 1 1 1 1 1 1 7 R38 R47 R54 R55 R58 R63 R64 R65 R76 R77 R78 R80 Revised: January 8, 1997 January 14, 1997 Part 10 10 140 k 120 k 2.2 k 2.2 k 2.2 k 2.2 k 144 144 18 k 33 15 k 15 k 7.5 k 390 k 390 k 390 k 390 k 390 k 100 100 100 100 470 k 500 k 270 k 22 k 240 k 200 k 392 k 806 k 100 k x 8 100 k x 8 100 k x 8 100 k x 8 April 1997 APPLICATION NOTE v1.0 PC Card (PCMCIA) Interface 43 CL-PS7111 Evaluation Kit -- User Manual CL-PS7111 EVAL Board DEB7111.SCH Revision: B Bill of Materials (cont.) Item Quantity Reference R81 R82 R83 74 75 76 77 78 79 80 81 1 1 1 2 1 2 51 4 R84 R85 R93 R99 R105 R104 S2 S1 TP1 TR1 TR2 TR3 TR4 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 1 1 1 2 1 1 1 1 2 2 1 1 1 1 1 1 1 TR5 U1 U2 U5 U11 U8 U9 U12 U13 U14 U18 U19 U31 U20 U21 U22 U23 U24 U26 U27 Revised: January 8, 1997 January 14, 1997 Part 100 k x 8 100 k x 8 100 k x 8 0.1 0.05 150 9 k 9 k 4.7 k SWSPST SWSPST NTP FMMT4124 FMMT4124 FMMT4124 FMMT4124 FMMT4124 MAX756CSA HM51W16160ALTT-7 29LV800BE 29LV800BE MSM7702-01MS MAX148BCAP MSC1192MS-K LM339MX 29LV800BF 29LV800BF CL-PS7111 CL-PS7111 MAX3212CAI SI4412DY SI4431DY MAX1651CSA MAX608ESA SI6426DQ CL-PS6700 44 PC Card (PCMCIA) Interface APPLICATION NOTE v1.0 April 1997 CL-PS7111 Evaluation Kit -- User Manual CL-PS7111 EVAL Board DEB7111.SCH Revision: B Bill of Materials (cont.) Item 99 100 101 102 Revised: January 8, 1997 January 14, 1997 Quantity 1 1 1 4 Reference U28 U29 U30 U32 U33 U34 U35 Part SI9712DY 13 MHz LM324 AT29LV040 AT29LV040 AT29LV040 AT29LV040 JMP3 JMP3 JMP3 JMP3 3.6864 MHz 3.6864 MHz 32.768 kHz 32.768 kHz 103 4 W1 W2 W4 W6 104 105 2 2 X1 X6 X2 X5 April 1997 APPLICATION NOTE v1.0 PC Card (PCMCIA) Interface 45 CL-PS7111 Evaluation Kit -- User Manual Appendix C C.Schematics Please contact Cirrus Logic for the latest CL-PS7111 schematic diagrams. 46 PC Card (PCMCIA) Interface APPLICATION NOTE v1.0 April 1997 CL-PS7111 Evaluation Kit -- User Manual Notes April 1997 APPLICATION NOTE v1.0 PC Card (PCMCIA) Interface 47 CL-PS7111 Application Note -- AN-PS1 v1.0 Direct Sales Offices Domestic N. CALIFORNIA Fremont TEL: 510/623-8300 FAX: 510/252-6020 S. CALIFORNIA Westlake Village TEL: 805/371-5860 FAX: 805/371-5861 NORTHWESTERN AREA Portland, OR TEL: 503/620-5547 FAX: 503/620-5665 SOUTH CENTRAL AREA Austin, TX TEL: 512/255-0080 FAX: 512/255-0733 Houston, TX TEL: 281/257-2525 FAX: 281/257-2555 NORTHEASTERN AREA Andover, MA TEL: 978/794-9992 FAX: 978/794-9998 SOUTHEASTERN AREA Raleigh, NC TEL: 919/859-5210 FAX: 919/859-5334 Boca Raton, FL TEL: 561/395-1613 FAX: 561/395-1373 International CHINA Beijing TEL: 86/10-6428-0783 FAX: 86/10-6428-0786 FRANCE Paris TEL: 33/1-48-12-2812 FAX: 33/1-48-12-2810 GERMANY Herrsching TEL: 49/81-52-92460 FAX: 49/81-52-924699 HONG KONG Tsimshatsui TEL: 852/2376-0801 FAX: 852/2375-1202 JAPAN Tokyo TEL: 81/3-3340-9111 FAX: 81/3-3340-9120 KOREA Seoul TEL: 82/2-565-8561 FAX: 82/2-565-8565 SINGAPORE TEL: 65/743-4111 FAX: 65/742-4111 TAIWAN Taipei TEL: 886/2-2718-4533 FAX: 886/2-2718-4526 UNITED KINGDOM London, England TEL: 44/01628-472211 FAX: 44/01628-486114 High-Value Systems in Silicon Cirrus Logic is a premier supplier of advanced integrated circuits that combine mixed-signal processing, precision analog techniques, embedded processors, and application-specific algorithms into system-on-a-chip solutions for existing and emerging growth markets. Enhanced by strong systems expertise in selected markets, the company's products add high value to major brands worldwide in magnetic and optical storage, networking communications, consumer/professional audio, video, and imaging, and ultra-precision data acquisition. Cirrus Logic's manufacturing strategy ensures maximum product quality and availability, as well as access to world-class processing technologies through joint ventures with IBM(R) and Lucent Technologies(R). Contact one of our systems and applications specialists to see how your company can benefit from the high value Cirrus Logic adds to its customers' products. Copyright (c) 1997 Cirrus Logic, Inc. All rights reserved. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, or trade secrets. Cirrus Logic, and Crystal are trademarks of Cirrus Logic, Inc., which may be registered in some jurisdictions. Other trademarks in this document belong to their respective companies. CRUS and Cirrus Logic International, Ltd. are trade names of Cirrus Logic, Inc. Cirrus Logic, Inc. 3100 West Warren Ave., Fremont, CA 94538 TEL: 510/623-8300 FAX: 510/252-6020 Publications Ordering: 800/359-6414 (USA) or 510/249-4200 Worldwide Web: http://www.cirrus.com 456700-001 |
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