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| ICs for TV AN2526FH Automotive LCD color TV signal processor IC Overview The AN2526FH is an IC optimized for the automotive TV, incorporating a synchronous stabilizing circuit into the LCD signal processor IC. In response to the demand for a compact and low cost set product, it is available not only for the three-wire serial control but also for the I2C bus control. 12.000.20 10.000.20 48 49 33 32 Unit: mm 64 17 1 0.50 16 +0.10 Features * Volume-less thanks to built-in I2C * High performance synchronous stabilizing circuit built-in * Analog OSD * PWM circuit built in (Duty variable) * Difference from AN2526NFH Unlike the AN2526NFH, it controls a synchronous system gain at no signal input, thus causing no screen abnormalities like shaking sideways. (It is suited for the set featuring in no signal input mode.) (1.25) 0.100.10 0.18-0.05 +0.1 0.15-0.05 1.950.20 (1.25) 10.000.20 12.000.20 (1.00) Seating plane 0 to 10 0.500.20 QFP064-P-1010 Note) The package of this product will be changed to lead-free type (QFP064-P-1010A). See the new package dimensions section later of this datasheet. Applications * Automotive TV Publication date: December 2002 SDB00050BEB 1 0.47 F 0.022 F VCC1 1 000 pF 100 k 100 k VCC1 2 PONR 510 k GND2 BUSCH 510 k 330 pF SCLCK VSS 3.3 k 10 k S-data AN2526FH Composite signal 470 1.0 F Clamp 2.2 F 82 k PWM POL DAC mon. NRGB 15 F 180 k 1 000 pF Shift res. 48 DEC Sync. sepa. Logic Reg. DAC Logic Logic PWM 200 k 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1. Composite signal input LD VCO DAC 49 HD VD 31 V-C/D ACC det. HH-KIL Logic f-det. Line I-det. PAL 1/2 BGP Tint Tint-ctl. Demod. LPF AVE det. Delay Int./Ext. SW Delay POL Amp. to 4 Gene. CLP VCOM adj. CW/SW 1/n Logic Logic COMON voltage Sync.DRP PH-CMP BUSCH 32 0.1 F 330 pF 82 k 50 LATCH 0.1 F Application Circuit Examples 51 29 28 27 26 25 24 23 22 White peak ctl. GCA Matrix CLMP Color-ctl. Contrast ctl. Int./Ext. SW Contrast Gamma ctl. 0.02 F HPF ACC amp. 30 C-sync. Field Test CLK TMODE VCOM 2.2 F 52 Logic 0.1 F 1 M 0.02 F 53 Kill det. 54 APC det. 55 SDB00050BEB GCA Det. 1 F 5.1 k NTSC 3.58 MHz PAL 4.43 MHz 0.1 F 56 VXO 1 57 47 H 58 CLMP (BGP) R-out 2.2 F Trap GND 3 NTSC 39 pF PAL 27 pF 59 GCA GND1 21 Gamma 4.7 F 60 YAP ctl. VCC1 50 kB R-Y out 61 20 19 Bright Bright-ctl. WB-ctl. 0.01 F 15 F VCC2 47 H (7.5 V) G-out 18 17 2.2 F B-Y out 62 R-Y in 63 GCA ctl. B-Y in 2 3 4 5 6 7 64 B-out VREF 10 11 12 13 14 15 16 1 1 F 1 F 1 F 8 9 VCC1 (5.0 V) 47 H 15 F YS B-in 1 R-in 2 G-in 1 BLAK G-in 2 R-in 1 B-in 2 Dec. B-out Dec. G-out Dec. R-out 15 F * C coupling input in an analog OSD mode. * Connect to GND in case of no use in a digital OSD mode. 0.47 F 0.022 F VCC1 1 000 pF 100 k 100 k VCC1 PONR 510 k GND2 BUSCH 510 k 330 pF SCLCK VSS 3.3 k 10 k S-data Lumi. + Sync. 470 1.0 F signal Clamp 2.2 F 82 k PWM POL DAC mon. NRGB 15 F 180 k 1 000 pF Shift res. 48 DEC Sync. sepa. Logic Reg. DAC Logic Logic PWM 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 200 k 2. Component signal input LD VCO DAC 49 31 V-C/D ACC det. HH-KIL Sync.DRP PH-CMP Logic f-det. Line I-det. PAL 1/2 BGP Tint Tint-ctl. Demod. LPF AVE det. Delay Int./Ext. SW GCA Delay POL Amp. 1 BUSCH 32 HD VD 0.1 F 330 pF 82 k 50 LATCH Chroma signal 0.1 F 51 0.02 F 1/n HPF ACC amp. 30 C-sync. 29 Logic Logic VCOM adj. COMON voltage 52 Logic Field 28 27 26 25 24 23 22 2.2 F 2.2 F 0.1 F 1 M 0.02 F CW/SW CLP 53 Kill det. Test CLK TMODE VCOM Application Circuit Examples (continued) 54 APC det. 55 to 4 Gene. SDB00050BEB White peak ctl. GCA Matrix CLMP Color-ctl. Contrast ctl. Int./Ext. SW Contrast Gamma ctl. GCA VREF Det. 1 F 5.1 k NTSC 3.58 MHz PAL 4.43 MHz 0.1 F 56 VXO 57 58 CLMP (BGP) R-out Trap GND 3 59 GND1 21 Gamma 4.7 F 60 YAP ctl. VCC1 50 kB R-Y out 61 20 19 Bright Bright-ctl. WB-ctl. 0.01 F 15 F VCC2 47 H (7.5 V) G-out 18 17 2.2 F B-Y out 62 R-Y in 63 GCA ctl. B-Y in 2 3 4 5 6 64 B-out 10 11 12 13 14 15 16 1 1 F 1 F 1 F 7 8 9 AN2526FH VCC1 (5.0 V) 47 H 15 F YS B-in 1 R-in 2 G-in 1 BLAK G-in 2 R-in 1 B-in 2 Dec. B-out Dec. G-out Dec. R-out 15 F 3 * C coupling input in an analog OSD mode. * Connect to GND in case of no use in a digital OSD mode. 4 0.47 F 0.022 F VCC1 1 000 pF 100 k 100 k VCC1 PONR 510 k GND2 AN2526FH BUSCH 510 k 330 pF SCLCK VSS 3.3 k 10 k S-data Composite 470 1.0 F signal Clamp 2.2 F 82 k PWM DAC mon. NRGB 15 F POL 180 k 1 000 pF Shift res. 48 DEC Sync. sepa. Logic Reg. DAC Logic Logic PWM 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 200 k 3. Analog RGB signal input LD VCO DAC 49 31 V-C/D ACC det. HH-KIL Logic f-det. Line I-det. PAL 1/2 BGP CW/SW Tint-ctl. Demod. LPF AVE det. Delay Int./Ext. SW Delay POL Amp. CLP VCOM adj. 1/n Logic Logic COMON voltage Sync.DRP PH-CMP BUSCH 32 HD VD 330 pF 82 k 50 LATCH 51 29 28 27 26 25 24 23 22 White peak ctl. GCA Matrix CLMP Color-ctl. Contrast ctl. Int./Ext. SW Contrast Gamma ctl. HPF ACC amp. 30 C-sync. Field Test CLK TMODE VCOM 2.2 F 52 Logic 53 Kill det. Application Circuit Examples (continued) 54 APC det. Tint 55 56 VXO 1 to 4 Gene. SDB00050BEB GCA Det. 57 58 CLMP (BGP) R-out 2.2 F Trap GND 3 59 GCA GND1 21 Gamma 60 YAP ctl. VCC1 50 kB 61 20 19 Bright Bright-ctl. WB-ctl. 0.01 F 15 F VCC2 47 H (7.5 V) G-out 18 17 2.2 F 62 63 GCA ctl. 64 B-out VREF 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 47 H 15 F 4.7 F 4.7 F 4.7 F YS BLAK G-in 2 R-in 2 B-in 2 15 F B-in 1 G-in 1 R-in 1 * C coupling input in an analog OSD mode. * Connect to GND in case of no use in a digital OSD mode. VCC1 (5.0 V) AN2526FH Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Description VCC1 (5.0 V) Reference voltage pin R-ch. clamp detection pin G-ch. clamp detection pin B-ch. clamp detection pin R-ch. decoder output pin G-ch. decoder output pin B-ch. decoder output pin R-ch. analog signal input pin G-ch. analog signal input pin B-ch. analog signal input pin R-ch. analog/character signal input pin G-ch. analog/character signal input pin B-ch. analog/character signal input pin Black level indication control signal input pin Character picking up pulse input pin B-ch. output pin B-ch. output DC feedback detection pin G-ch. output pin VCC2 (7.5 V) Drive output reference potential input pin GND 1 G-ch. output DC feedback detection pin R-ch. output pin R-ch. output DC feedback detection pin Common reverse signal output pin Testing pulse input pin Testing clock input pin Field identification signal output pin Composite synchronous signal output pin Vertical synchronous signal output pin Horizontal synchronous signal output pin Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Description PWM output pin Power-on reset detection pin Vertical synchronous signal input pin 1H reverse signal input pin Clock-system GND (VSS) Clamp pulse input pin DAC monitor pin Clock-system power supply (3.0 V) GND 2 Analog imposing control signal input pin AFC loop filter connecting pin VCO frequency adjustment pin Synchronous signal input pin Serial/I2C bus switching pin Serial data shift clock input pin Serial data input pin Serial data write pulse input pin ACC detection pin ACC input pin Horizontal clock detection pin Chrominance killer detection pin APC detection pin VXO input pin VXO output pin Y-system clamp detection pin Chrominance signal trap filter connection pin GND 3 Luminance signal input pin R-Y output pin B-Y output pin R-Y input pin B-Y input pin SDB00050BEB 5 AN2526FH Absolute Maximum Ratings Parameter Supply voltage Symbol VCC1 VCC2 Supply current Power dissipation *2 *1 Rating 5.5 8.5 423 -30 to +85 -55 to +150 Unit V ICC PD Topr Tstg *1 mA mW C C Operating ambient temperature Storage temperature Note) *1: Except for the operating ambient temperature and storage temperature, all ratings are for Ta = 25C. *2: The power dissipation shown is the value in free air for Topr = 85C. Recommended Operating Range Parameter Supply voltage Symbol VCC1 VCC2 Range 4.7 to 5.3 7.0 to 8.0 Unit V Electrical Characteristics at Ta = 25C Parameter DC VCC1-system current consumption VCC2-system current consumption Pin 2 voltage Pin 40 voltage Chrominance system R-Y standard gain R-Y/G-Y relative gain B-Y standard gain B-Y/G-Y relative gain High-level APC pull-in Low-level APC pull-in ACC output characteristic 1 ACC output characteristic 2 Chrominance killer characteristic 1 Chrominance killer characteristic 2 GRY GRYGY GBY GBYGY APH APL GACC1 GACC2 VKILL1 VKILL2 SG3 (Yy = -17 dB, Ys = 0 V[p-p], NTSC), ch.1 = "C0" SG3 (Yy = -17 dB, Ys = 0 V[p-p], NTSC), ch.1 = "C0" SG3 (Yy = -17 dB, Ys = 0 V[p-p], NTSC), ch.1 = "C0" SG3 (Yy = -17 dB, Ys = 0 V[p-p], NTSC), ch.1 = "C0" SG5 (4.43 MHz + 520 Hz, PAL) SG5 (4.43 MHz - 520 Hz, PAL) SG5 (0 dB, 6 dB, NTSC), ch.1 = "80" SG5 (0 dB, 6 dB, NTSC), ch.1 = "80" SG5 (-30 dB, NTSC) ch.1 = "80", ch.2 = "80", ch.5 = "FF" SG5 (-50 dB, NTSC) ch.1 = "80", ch.2 = "80", ch.5 = "FF" 9.5 -8.0 9.5 -20.5 500 -540 -1.0 -1.0 400 14.5 -4.0 14.5 -12.5 540 -500 1.0 1.0 dB dB dB dB Hz Hz dB dB mV[p-p] ITOTAL1 ITOTAL2 V2 V40 29 6.0 1.8 2.7 43 14.0 2.2 3.3 mA mA V V Symbol Conditions Min Typ Max Unit 600 mV[p-p] 6 SDB00050BEB AN2526FH Electrical Characteristics at Ta = 25C (continued) Parameter Y-system Sharpness control characteristic Sharpness frequency characteristic 1 R-ch. contrast adjustment range 1 GSH fSH1 CTRR1 SG1 (2 MHz, NTSC) ch.1 = "80", ch.9 = "80"/"FF" SG1 (100 kHz/2 MHz, NTSC) ch.1 = "80" SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment ch.15 = "C0"/"FF" SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment ch.15 = "C0"/"FF" SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment ch.15 = "C0"/"FF" SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment ch.15 = "C0"/"80" SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment ch.15 = "C0"/"80" SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment ch.15 = "C0"/"80" 1.0 3.5 1.5 dB dB dB Symbol Conditions Min Typ Max Unit G-ch. contrast adjustment range 1 CTRG1 1.5 dB B-ch. contrast adjustment range 1 CTRB1 1.5 dB R-ch. contrast adjustment range 2 CTRR2 -5.2 dB G-ch. contrast adjustment range 2 CTRG2 -5.2 dB B-ch. contrast adjustment range 2 CTRB2 -5.2 dB R-ch. pedestal amplitude minimum VPEDRmin SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment, ch.8 = "FF" ch.15 = "C0" 2.0 V[p-p] G-ch. pedestal amplitude minimum VPEDGmin SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment, ch.8 = "FF" ch.15 = "C0" B-ch. pedestal amplitude minimum VPEDBmin SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment, ch.8 = "FF" ch.15 = "C0" 2.0 V[p-p] 2.0 V[p-p] SDB00050BEB 7 AN2526FH Electrical Characteristics at Ta = 25C (continued) Parameter Y-system (continued) R-ch. pedestal amplitude maximum VPEDRmax SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment, ch.8 = "00" ch.15 = "C0" G-ch. pedestal amplitude maximum VPEDGmax SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment, ch.8 = "00" ch.15 = "C0" B-ch. pedestal amplitude maximum VPEDBmax SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12/13/14 = "FF" ch.8/10/11 adjustment, ch.8 = "00" ch.15 = "C0" G-ch. output DC voltage VGDC SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11 adjustment, ch.15 = "C0" 3.0 V[p-p] Symbol Conditions Min Typ Max Unit 3.0 V[p-p] 3.0 V[p-p] 2.2 2.5 V[p-p] R-ch. gamma characteristic 1 GGAMR1 SG3 (NTSC), ch.1 = "E0", ch.2 = "40" -8.5 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment SG3 (NTSC), ch.1 = "E0", ch.2 = "40" -8.5 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment SG3 (NTSC), ch.1 = "E0", ch.2 = "40" -8.5 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment SG3 (NTSC), ch.1 = "E0", ch.4 = "40" -8.2 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment ch.13 = "80"/"FF" SG3 (NTSC), ch.1 = "E0", ch.4 = "40" -8.2 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment ch.13 = "80"/"FF" SG3 (NTSC), ch.1 = "E0", ch.4 = "40" -8.2 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment ch.13 = "80"/"FF" SG3 (NTSC), ch.1 = "E0", ch.2 = "40" -3.5 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment ch.13 = "80"/"60" -3.5 dB G-ch. gamma characteristic 1 GGAMG1 -3.5 dB B-ch. gamma characteristic 1 GGAMB1 -3.5 dB R-ch. gamma characteristic 2 GGAMR2 dB G-ch. gamma characteristic 2 GGAMG2 dB B-ch. gamma characteristic 2 GGAMB2 dB R-ch. gamma characteristic 3 GGAMR3 0.5 dB 8 SDB00050BEB AN2526FH Electrical Characteristics at Ta = 25C (continued) Parameter Y-system (continued) G-ch. gamma characteristic 3 GGAMG3 SG3 (NTSC), ch.1 = "E0", ch.2 = "40" -3.5 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment ch.13 = "80"/"60" SG3 (NTSC), ch.1 = "E0", ch.2 = "40" -3.5 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment ch.13 = "80"/"60" SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "00", ch.14 = "40" ch.8/10/11/15 adjustment ch.15 = "FF" SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "00", ch.14 = "40" ch.8/10/11/15 adjustment ch.15 = "FF" SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "00", ch.14 = "40" ch.8/10/11/15 adjustment ch.15 = "FF" SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment ch.15 = "FF" SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment ch.15 = "FF" 0.5 dB Symbol Conditions Min Typ Max Unit B-ch. gamma characteristic 3 GGAMB3 0.5 dB R-ch. white limiter low-level VWRRL 3.0 V[p-p] G-ch. white limiter low-level VWRGL 3.0 V[p-p] B-ch. white limiter low-level VWRBL 3.0 V[p-p] R-ch. white limiter high-level VWRRH 3.2 V[p-p] G-ch. white limiter high-level VWRGH 3.2 V[p-p] B-ch. white limiter high-level VWRBH SG3 (NTSC), ch.1 = "E0", ch.2 = "40" 3.2 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment ch.15 = "FF" SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.7 = "80", ch.12 = "FF" ch.14 = "40", ch.8/10/11/15 adjustment ch.8 = "00" SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.7 = "80", ch.12 = "FF" ch.14 = "40", ch.8/10/11/15 adjustment ch.8 = "00" 3.0 V[p-p] R-ch. black limiter low-level VBRRL V G-ch. black limiter low-level VBRGL 3.0 V SDB00050BEB 9 AN2526FH Electrical Characteristics at Ta = 25C (continued) Parameter Y-system (continued) B-ch. black limiter low-level VBRBL SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.7 = "80", ch.12 = "FF" ch.14 = "40", ch.8/10/11/15 adjustment ch.8 = "00" SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF" ch.8/10/11/15 adjustment, ch.7 = "FF" ch.8 = "00", ch.14 = "40" SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF" ch.8/10/11/15 adjustment, ch.7 = "FF" ch.8 = "00", ch.14 = "40" SG3 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF" ch.8/10/11/15 adjustment, ch.7 = "FF" ch.8 = "00", ch.14 = "40" SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = 1 V SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = 1 V SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = 1 V SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = 4 V SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = 4 V SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = 4 V 3.0 V Symbol Conditions Min Typ Max Unit R-ch. black limiter high-level VBRRH 1.2 V G-ch. black limiter high-level VBRGH 1.2 V B-ch. black limiter high-level VBRBH 1.2 V R-ch. YS threshold 1 VtYSR1 0.8 V[p-p] G-ch. YS threshold 1 VtYSG1 0.8 V[p-p] B-ch. YS threshold 1 VtYSB1 0.8 V[p-p] R-ch. YS threshold 2 VtYSR2 0.5 V[p-p] G-ch. YS threshold 2 VtYSG2 0.5 V[p-p] B-ch. YS threshold 2 VtYSB2 0.5 V[p-p] R-ch. black level CHRRB SG2 (NTSC), ch.1 = "E0", ch.2 = "40" - 0.6 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = SG7 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" - 0.6 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = SG7 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" - 0.6 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = SG7 SDB00050BEB 0.6 V G-ch. black level CHRGB 0.6 V B-ch. black level CHRBB 0.6 V 10 AN2526FH Electrical Characteristics at Ta = 25C (continued) Parameter Y-system (continued) R-ch. black level width WCHRRB SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 2.25 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = SG7 WCHRGB SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 2.25 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = SG7 WCHRBB SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 2.25 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 16 = SG7 VtCHR1 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 12 = 1 V SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 13 = 1 V SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 14 = 1 V SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 12 = 4 V SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 13 = 4 V SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 14 = 4 V SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 12 = SG7 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 13 = SG7 SG2 (NTSC), ch.1 = "E0", ch.2 = "40" ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 14 = SG7 1.5 3.75 s Symbol Conditions Min Typ Max Unit G-ch. black level width 3.75 s B-ch. black level width 3.75 s R-ch. CHR threshold 1 V[p-p] G-ch. CHR threshold 1 VtCHG1 1.5 V[p-p] B-ch. CHR threshold 1 VtCHB1 1.5 V[p-p] R-ch. CHR threshold 2 VtCHR2 3.0 V[p-p] G-ch. CHR threshold 2 VtCHG2 3.0 V[p-p] B-ch. CHR threshold 2 VtCHB2 3.0 V[p-p] R-ch. white level CHRRW 2.0 V[p-p] G-ch. white level CHRGW 2.0 V[p-p] B-ch. white level CHRBW 2.0 V[p-p] R-ch. white level width WCHRRW SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 2.25 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 12 = SG7 WCHRGW SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 2.25 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 13 = SG7 3.75 s G-ch. white level width 3.75 s SDB00050BEB 11 AN2526FH Electrical Characteristics at Ta = 25C (continued) Parameter Y-system (continued) B-ch. white level width WCHRBW SG2 (NTSC), ch.1 = "E0", ch.2 = "40" 2.25 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, Pin 14 = SG7 VRGB2R SG2 (NTSC), ch.1 = "A0" - 0.45 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, ch.3 = "40" ch.6 = "40", Pin 42 = 4 V SG2 (NTSC), ch.1 = "A0" - 0.45 ch.5 = "80", ch.12 = "FF", ch.14 = "40" ch.8/10/11/15 adjustment, ch.3 = "40" ch.6 = "40", Pin 42 = 4 V SG2 (NTSC) SG2 (NTSC) SG2 (NTSC) 4.0 4.86 4.0 4.0 4.0 3.8 3.75 s Symbol Conditions Min Typ Max Unit R-ch. RGB2 relative amplitude 0.45 V[p-p] B-ch. RGB2 relative amplitude VRGB2B 0.45 V[p-p] Synchronous system Horizontal sync. pulse low-level Horizontal sync. pulse amplitude Horizontal sync. pulse width Vertical sync. pulse low-level Vertical sync. pulse amplitude Horizontal sync. separation pulse high-level Horizontal sync. separation pulse amplitude Horizontal sync. separation pulse width VHDL VHD tHD VVDL VVD VHSSH VHSS tHSS 0.4 6.86 0.4 5.8 V V[p-p] s V V[p-p] V V[p-p] s 12 SDB00050BEB AN2526FH Electrical Characteristics at Ta = 25C (continued) * Testing signal waveform Signal name Signal waveform SG1 (Sine wave video signal) YV = 200 mV[p-p] YY = 100 mV[p-p] YS = 300 mV[p-p] SG2 (White signal) YY = 700 mV[p-p] YS = 300 mV[p-p] SG3 (10-step wave) YY = 700 mV[p-p] YS = 300 mV[p-p] SG5 (Color bar chrominance signal) Burst amplitude = 300 mV[p-p] Chrominance amplitude = 600 mV[p-p] Burst, chrominance frequency NTSC = 3.579 545 MHz PAL = 4.433 619 MHz 3.0 V 3 s SG7 (Character pulse) GND 1H SDB00050BEB 13 AN2526FH Terminal Equivalent Circuits Pin No. 1 Equivalent circuit Description VCC1: 5.0 V-system power supply pin Supply current 40 mA typ. Voltage * Waveform 2 60 Pin 1 VCC1 VREF: Reference voltage output pin 2.0 V typ. 2 1 k 26 k 200 3 1 k 3 500 30 k Pin 59 GND R-ch. det.: R-ch. clamping capacitor coupling pin Pin 1 1 k VCC1 HSS Pin 22 GND 4 1 k 4 500 Pin 1 1 k VCC1 G-ch. det.: G-ch. clamping capacitor coupling pin HSS Pin 22 GND 5 1 k 5 500 Pin 1 1 k VCC1 B-ch. det.: B-ch. clamping capacitor coupling pin HSS Pin 22 GND 14 SDB00050BEB AN2526FH Terminal Equivalent Circuits (continued) Pin No. 6 Equivalent circuit Description Voltage * Waveform Dec.R-out: Output pin of R signal demodulated from video signal Pin 1 VCC1 6 150 150 Pin 22 GND 7 Pin 1 VCC1 Dec.G-out: Output pin of G signal demodulated from video signal 7 150 150 Pin 22 GND 8 Pin 1 VCC1 Dec.B-out: Output pin of B signal demodulated from video signal 8 150 150 Pin 22 GND 9 Pin 1 VCC1 R-in 1: Analog R signal input Analog R signal 0.7 V[p-p] typ. 9 BGP 5 k Pin 2 VREF Pin 22 GND SDB00050BEB 15 AN2526FH Terminal Equivalent Circuits (continued) Pin No. 10 Equivalent circuit Pin 1 VCC1 Description G-in 1: Analog G signal input Voltage * Waveform Analog G signal 0.7 V[p-p] typ. 10 BGP 5 k Pin 2 VREF 11 Pin 1 VCC1 Pin 22 GND B-in 1: Analog B signal input Analog B signal 0.7 V[p-p] typ. 11 BGP 5 k Pin 2 VREF 12 Pin 1 VCC1 Pin 22 GND R-in 2: Character insertion signal input for R-ch., supporting analog and digital OSD. Analog OSD 0.7 V[p-p] typ. Digital OSD 12 BGP 5 k VCC1 GND Pin 2 VREF Pin 22 GND 13 Pin 1 VCC1 G-in 2: Character insertion signal input for G-ch., supporting analog and digital OSD. Analog OSD 0.7 V[p-p] typ. Digital OSD 13 BGP 5 k VCC1 GND Pin 2 VREF Pin 22 GND 16 SDB00050BEB AN2526FH Terminal Equivalent Circuits (continued) Pin No. 14 Equivalent circuit Pin 1 VCC1 Description B-in 2: Character insertion signal input for B-ch., supporting analog and digital OSD. Voltage * Waveform Analog OSD 0.7 V[p-p] typ. Digital OSD 14 BGP 5 k VCC1 GND Pin 2 VREF Pin 22 GND 15 15 5 k 49.3 k VSS BLK: Black level indication control signal input pin VCC1 GND 16 16 5 k 49.3 k VSS YS: Character picking up signal input VCC1 GND 17 100 k 200 Pin 18 Pin 20 VCC2 26 k B-out: B signal output pin 17 2 k Pin 22 GND 18 100 k Pin 17 Pin 20 VCC2 18 2 k B-ch.AVE det.: B-ch. output DC feedback detection pin 8 k Pin 22 GND SDB00050BEB 17 AN2526FH Terminal Equivalent Circuits (continued) Pin No. 19 Equivalent circuit 100 k 200 Pin 18 Description G-out: G signal output pin Voltage * Waveform Pin 20 VCC2 26 k 19 2 k Pin 22 GND 20 VCC2: 7.5 V system power supply Supply current 12 mA typ. Pin 20 VCC2 200 k 21 2 k 200 k 8 k Pin 22 GND 21 AVE : R,G,B output DC reference voltage pin 22 23 GND 2: Drive circuits system GND 100 k 23 Pin 17 Pin 20 VCC2 2 k G-ch.AVE det.: G-ch. output DC feedback detection pin 8 k Pin 22 GND Pin 20 VCC2 R-out: R signal output pin 24 100 k 200 Pin 18 26 k 24 2 k Pin 22 GND 18 SDB00050BEB AN2526FH Terminal Equivalent Circuits (continued) Pin No. 25 Equivalent circuit Description Voltage * Waveform 100 k 25 Pin 17 Pin 20 VCC2 2 k R-ch.AVE det.: R-ch. output DC feedback detection pin 8 k Pin 22 GND 26 200 Pin 19 VCC2 Common out: Voltage output pin for common. Output impedance; Approx. 150 ch.3 15 k 26 100 k ch.3 Pin 22 GND 27 Pin 40 VDD 27 5 k 44.8 k Pin 37 VSS Test mode: Logic test mode start signal input pin; "Open" or "GND" normally High or Low 28 5 k 44.8 k Pin 40 VDD 28 Test CLK: Logic test pulse input pin; "Open" or "GND" normally High or Low Pin 37 VSS 29 Pin 1 VCC1 29 Pin 40 VDD Field Pin 37 VSS Field: Field identifying signal output pin Output waveform VCC1 0V SDB00050BEB 19 AN2526FH Terminal Equivalent Circuits (continued) Pin No. 30 Equivalent circuit Pin 1 VCC1 30 Pin 40 VDD HSS Pin 37 VSS 31 Pin 1 VCC1 31 Pin 40 VDD VD Pin 37 VSS 32 Pin 1 VCC1 32 Pin 40 VDD HD Pin 37 VSS 33 Pin 1 VCC1 33 Pin 40 VDD PWM Pin 37 VSS 34 5 k 500 Pin 1 VCC1 100 k 0V 0V 0V 0V Description HSS: Composite synchronous signal output pin Voltage * Waveform Output waveform VCC1 VD: Vertical synchronous signal output pin Output waveform VCC1 HD: Horizontal synchronous signal output pin Output waveform VCC1 PWM: PWM signal output pin Output waveform VCC1 RST: Capacitor coupling pin for power-on reset 34 50 k Pin 37 VSS 20 SDB00050BEB AN2526FH Terminal Equivalent Circuits (continued) Pin No. 35 Equivalent circuit Description Voltage * Waveform High or Low VDB in: Vertical synchronous pulse input pin Pin 40 VDD 35 5 k 50.2 k Pin 37 VSS 36 Pin 40 VDD 36 5 k 50.2 k Pin 37 VSS Ext. pol.: 1H reverse signal input pin High or Low 37 38 5 k 50.2 k Pin 40 VDD 38 VSS : MOS system GND Clamp in: Clamp pulse input pin Valid only in the external clamp mode. Positive polarity input. High or Low Pin 37 VSS 39 1.5 pF Pin 1 VCC1 DAC mon.: DAC DC voltage output pin DC 200 39 2 k 25 k 20 k Pin 59 GND VDD: Capacitor connection pin for MOS part power supply. 3.0 V typ. GND 3: Pulse system GND Pin 40 VDD 42 5 k 53.8 k Pin 37 VSS 40 41 42 High or Low PRGB: Analog OSD signal input Mode start-up signal input pin Valid only in the analog OSD mode High = Analog OSD start up SDB00050BEB 21 AN2526FH Terminal Equivalent Circuits (continued) Pin No. 43 2 k Equivalent circuit Pin 1 VCC1 Description AFC det.: AFC filter connection pin Input impedance; 100 k or more Voltage * Waveform 1H 43 1 k 2 k 44 1 k Pin 59 GND 10 k 5 pF Pin 1 VCC1 10 k H fO: VCO oscillation frequency adjusting resistor connection pin 44 2 k Pin 59 GND 45 8.4 k Pin 1 VCC1 45 Pin 2 VREF HSS in: H-sync. input pin Separates a sync signal from luminance signal (video signal) Input signal example: Video signal 20 k 46 4 k 50 k 20 k Pin 59 GND Pin 40 VDD 46 Pin 37 VSS Bus-ch: Switching pin for serial threewire control/I2C bus control High = I2C bus Open or Low = Serial threewire control DAC: Serial clock input pin High or Low 47 4 k 50 k Pin 40 VDD 47 Pin 37 VSS 22 SDB00050BEB AN2526FH Terminal Equivalent Circuits (continued) Pin No. 48 Equivalent circuit Description DAT: Serial data input pin Voltage * Waveform 50 4 k 48 Pin 40 VDD 500 ACK Pin 37 VSS 49 4 k 50 k Pin 59 GND Pin 48 VDD 49 Pin 41 VSS LEN: Load pulse input pin, also works as the slave address conversion pin in the I2C bus mode. High = "88" Low = "8A" ACC det.: ACC capacitor connecting pin, adjusting the amplitude of a burst signal automatically High or Low 50 1 k 2 k 50 5 k 5 k 1 k Pin 1 VCC1 1 k 1 k 51 Pin 59 GND Pin 1 VCC1 C in: Input signal example: Chrominance signal signal inVideo signal put pin Input chrominance signal (video signal) 51 50 k Pin 59 GND 52 200 Pin 1 VCC1 L.det.: Capacitor coupling pin for the horizontal unlock detecting circuit 60 52 60 10 k 12 k Pin 59 GND SDB00050BEB 23 AN2526FH Terminal Equivalent Circuits (continued) Pin No. 53 72 k 53 1.5 k Equivalent circuit Pin 1 VCC1 Description Kill det.: Killer capacitor coupling pin. To prevent degradation of image in a small amplitude of a burst signal, this pin stops a chrominance signal and the mode changes to black and white mode. Voltage * Waveform 90 k 54 Pin 1 VCC1 1 k 1 k 31 k Pin 59 GND APC det.: APC capacitor coupling pin. 41 k Matching the phase of a crystal oscillation to that of burst signal. 5 k 5 k 54 50 k 2 k Pin 59 GND 100 k 2 k 1 k 50 k 45 k 55 26 k Pin 1 VCC1 VXOI : Crystal oscillator connecting pin The pair with pin 56 NTSC 3.58 MHz PAL 4.43 MHz 6 k 55 5 k 15 pF 26 k Pin 59 GND Pin 1 VCC1 VXOO: Crystal oscillator connecting pin The pair with pin 55 Output impedance; Approximately 100 NTSC 3.58 MHz PAL 4.43 MHz 400 56 500 56 500 Pin 59 GND 24 SDB00050BEB AN2526FH Terminal Equivalent Circuits (continued) Pin No. 57 Equivalent circuit Description Voltage * Waveform Y-det.: Capacitor coupling pin for luminance signal clamping 1 k Pin 1 1 k VCC1 57 2 k Pin 59 GND 58 Pin 1 VCC1 2 k 58 1 k 2 k 2 k 50 60 Trap: Trap connecting pin Trapping a chrominance signal by connecting external inductor and capacitor. Not necessary in case that an input signal is a component. Pin 59 GND 59 GND 3: GND for chrominance and luminance signal process blocks Pin 1 VCC1 60 20 k 50 2 k 2 k 1 k 2 k Y-in: Luminance signal input pin Input luminance signal (video signal) Input signal example: Video signal 60 58 Pin 59 GND 61 1 k Pin 1 VCC1 R-Y out: R-Y signal output pin, demodulated from a video signal R-Y signal 61 1 k Pin 59 GND SDB00050BEB 1H 25 AN2526FH Terminal Equivalent Circuits (continued) Pin No. 62 1 k Equivalent circuit Pin 1 VCC1 Description B-Y out: B-Y signal output pin, demodulated from a video signal Voltage * Waveform B-Y signal 62 1H 1 k Pin 59 GND 63 5 k 5 k Pin 1 VCC1 R-Y in: R-Y signal input pin in a color difference mode and in standard PAL. R-Y signal 2 k 63 5 k Pin 2 VREF 17.5 k 1H 5 k 5 k Pin 59 GND Pin 1 VCC1 64 5 k 5 k B-Y in: B-Y signal input pin in a color difference mode and in standard PAL. B-Y signal 2 k 64 5 k Pin 2 VREF 17.5 k 1H 5 k 5 k Pin 59 GND Usage Notes * Since the following pins are low in a static electricity breakdown level, be cautious on use. Pin 27 breakdown level C = 200 pF + 200 V to 210 V Pin 35 breakdown level C = 200 pF + 180 V to 190 V * Evaluated throughly on the application of this device in PAL. 26 SDB00050BEB AN2526FH Technical Data 1. Serial interface description 1) Serial data control In addition to its serial control by the conventional three-wire method, the AN2526FH can be controlled by the I2C bus. The transmission method is selected by the voltage to be applied to Pin 46. Three-wire control mode: Pin 46 = Low (connect to GND) I2C bus mode: Pin 46 = High (Pin 41: connect to VDD ) It is recommended that the serial data is transferred during a vertical blanking period. 2) Three-wire control mode A serial data is of three-line system communicating three kinds of signals of data, shift clock and load pulse independently. The data to be communicated is made up by 12 bits in total of address (4 bits) and data (8 bits). The DAC is composed of four blocks of serial-parallel conversion, address decoder, data latch and ladder resistors, enabling to control 16 channels in total. Further, the mode setting such as the input signal switching is done by a serial data to reduce the pin count. (1) Serial data format D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Address block (2) Serial data input timing chart Pin 48 S-data Pin 47 SCLK Pin 49 LD D11 D10 Data block D2 D1 D0 Timing chart expanded diagram tCKH tcf Pin 47 SCLK tCKL Pin 48 S-data Pin 49 LD tDCH tCHD tCHL tcr tLDC tLDH SDB00050BEB 27 AN2526FH Technical Data (continued) 1. Serial interface description (continued) 2) Three-wire control mode (continued) (2) Serial data input timing chart (continued) Parameter Clock low-level pulse width Clock high-level pulse width Clock rise time Clock fall time Data setup time Data hold time Load setup time Load hold time Load high-level pulse width (3) Mode setting channel bits table D11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D10 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D9 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D8 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Selection-ch. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 EVR control function Vertical sync. signal output position Horizontal sync. signal output position PWM duty Common pulse amplitude Y-gain Color gain Hue Black-limiter level Brightness Y-aperture gain R-ch. sub-brightness B-ch. sub-brightness White peak limiter level Gamma-1 Knee level Gamma-2 Knee level RGB contrast Number of bits 3 5 6 7 8 7 7 8 8 8 8 8 8 8 8 7 Symbol tCKL tCKH tcr tcf tDCH tCHD tCHL tLDC tLDH Min 500 500 30 60 200 100 500 Max 20 20 Unit ns ns ns ns ns ns ns ns ns A variety of mode-settings for the channels for 8 bits or less is made by using the data of the data block. The contents of each mode setting are shown next. 28 SDB00050BEB AN2526FH Technical Data (continued) 1. Serial interface description (continued) 2) Three-wire control mode (continued) (3) Mode setting channel bits table (continued) * ch.0: Vertical sync. output position adjustment D11 D10 D9 D8 D7 0 0 0 0 0 1 D6 0 1 D5 D4 to D3 D2 D1 D0 EXCHF FIXHD BOSC Hor. PLL start position adjustment 0 1 Automatic switching 263H/313H fixed (NTSC/PAL) HD/VD output timing is serially variable HD/VD output timing fixed Odd number field: Advanced phase Even number field: Advanced phase Composite sync. signal odd number field Pin 33 input Pin 31 output odd number field FIXHD = "0" Pin 31 output odd number field FIXHD = "1" 3 8H 2H to 9H(D0 to D2) Composite sync. signal even number field Pin 31 output EXCHF = "1" FIXHD = "0" Pin 31 output EXCHF = "1" FIXHD = "1" Pin 31 output EXCHF = "0" FIXHD = "0" 3 8H 1.5H to 8.5H(D0 to D2) 8H 2.5H to 9.5H (D0 to D2) The above timing chart indicates (D2,D1,D0) = "101". For (D2,D1,D0) = "000", the pin 31 output width is 9H. Pin 31 output EXCHF = "0" FIXHD = "1" 3 The pin 31 timing is synchronous with the pin 33 input timing. The above timing chart is just for reference. SDB00050BEB 29 AN2526FH Technical Data (continued) 1. Serial interface description (continued) 2) Three-wire control mode (continued) (3) Mode setting channel bits table (continued) * ch.0: (continued) Composite sync. signal odd number field Pin 33 input 6H to 9H (D3 to D4) Odd number field Composite sync. signal even number field 5.5H to 8.5H (D3 to D4) EXCHF = "1" Horizontal PLL off 6.5H to 9.5H (D3 to D4) EXCHF = "0" Horizontal PLL off Horizontal PLL on The above timing chart indicates (D4,D3) = "01". PLL stop line number: 254-line (NTSC) 302-line (PAL) Horizontal PLL on Horizontal PLL off Horizontal PLL on 0-line 1 2 3 * ch.1: Horizontal sync. output position adjustment D11 D10 D9 D8 D7 V Mode 1 0 0 0 0 1 PAL NTSC D6 YUV 0 1 D5 RGB 0 1 D4 D3 D2 D1 D0 Video signal input display mode Analog RGB input display mode Chrominance signal input mode Color-difference signal input mode Composite sync. signal input (video signal) Sync. signal separation delay time (Approximately 1 s) Pin 30 Composite sync. signal output Pin 32 Horizontal sync. signal output (D4,D3,D2,D1,D0) = (00000) Pin 32 Horizontal sync. signal output (D4,D3,D2,D1,D0) = (11111) Pin 32 Horizontal sync. signal output ch.0 (D6) = "1" 27fy 32fy 31fy 32fy 1 (NTSC/PAL) 347fh fh: Horizontal sync. frequency 1fy = 30 SDB00050BEB AN2526FH Technical Data (continued) 1. Serial interface description (continued) 2) Three-wire control mode (continued) (3) Mode setting channel bits table (continued) * ch.1: Horizontal sync. output position adjustment (continued) The delay time of pin 30 output to video signal is likely to vary according to an external constant connected to pin 45. For an external constant, the characteristics in weak electric field must be evaluated adequately. Though the horizontal sync. signal output adjustment range is designed by referring to the center of pin 30 output pulse, there would be some error according to VCO free-run frequency. * ch.2: PWM duty adjustment D11 D10 D9 D8 D7 D6 P mode YC mode 0 1 0 0 0 1 0 1 D5 D4 D3 D2 D1 D0 Composite input mode Component input mode Standard PAL mode Quasi PAL/NTSC mode 0 to 58H fh : (NTSC/PAL) 58 Note that adjustment characteristics come to discontinuation around max. duty. (D5,D4,D3,D2,D1,D0) = (000000): tw = 1H = (000001): tw = 3H = (000010): tw = 4H = (110110): tw = 56H = (110111): tw = 56H = (111000): tw = 0H = (111001): tw = 58H * ch.3: Common pulse amplitude adjustment D11 1 D10 1 D9 0 D8 0 D7 OSD 0 1 * ch.5: Color gain adjustment D11 1 D10 0 D9 1 D8 0 D7 HTS 0 1 D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 Analog OSD signal input mode Digital OSD signal input mode 1H reverse inhibit mode 1H reverse mode SDB00050BEB 31 AN2526FH Technical Data (continued) 1. Serial interface description (continued) 2) Three-wire control mode (continued) (3) Mode setting channel bits table (continued) * ch.6: Hue adjustment D11 0 D10 1 D9 1 D8 0 D7 CP 0 1 * ch.9: Y-aperture gain adjustment D11 1 D10 0 D9 0 D8 1 D7 D6 D5 D4 D3 D2 D1 D0 00h, 01h: Test mode D6 D5 D4 D3 D2 D1 D0 External clamp pulse input mode Internal clamp (pedestal) mode * ch.15: RGB contrast adjustment D11 1 D10 1 D9 1 D8 1 D7 POL mode 0 1 D6 D5 D4 D3 D2 D1 D0 Internal POL 1H reverse mode External POL 1H reverse mode 3) I2C bus control mode A serial data is capable of transferring 9-bit unit of 8-bit transfer data and 1-bit answering data using two kinds of signal lines of data and shift clock. When a slave address after setting a start condition matches the address on the IC side, you can receive the data to be transmitted from then. Once the stop condition is set up, the next transmitting data will be ignored until the start condition is set up. There are two kinds of transfer mode: an auto-increment mode which does not transmit subaddress, and data upgrade mode which transmits sub-address + data by 2 bytes. The typical models of communication sequence are shown below: (1) Start condition When the S-data changes from high level to low level at SCLK = high level, a data receiving mode becomes available. (2) Slave address transfer The slave address of the AN2526FH is 88h at pin 49 = high level and 8Ah at pin 49 = low level. When you use the slave address at 88h, 10h and 11h are prohibited on the application. When you use the slave address at 8Ah, 14h and 15h are prohibited on the application. Pin 48 S-data 1 Pin 47 SCLK Subaddress transfer Start condition Acknowledge bit 2 3 4 5 6 7 8 9 1 2 32 SDB00050BEB AN2526FH Technical Data (continued) 1. Serial interface description (continued) 3) I2C bus control mode (continued) (3) Subaddress transfer When a data transfer mode bit is 0, all the serial data columns transferred until a stop condition is set is regarded as the data block. Pin 48 S-data 8 Pin 47 SCLK Slave Address transfer Data transfer mode bit "1": Data update mode "0": Auto increment mode Data transfer Acknowledge bit 9 D7 1 D6 2 D5 3 D4 4 D3 5 D2 6 D1 7 D0 8 9 1 2 (4) Data transfer Pin 48 S-data 8 Pin 47 SCLK Acknowledge bit At auto increment mode: Data transfer At data update mode: Subaddress transfer 9 D7 1 D6 2 D5 3 D4 4 D3 5 D2 6 D1 7 D0 8 9 1 2 (5) Stop condition When S-data changes from low level to high level at SCLK = high level, data reception is halted. (6) Pulse timing Timing chart expanded diagram Pin 48 S-data tBUF tLOW Pin 47 SCLK tSUSTO tHDSTA tr tHIGH tHDDAT tf tSUDAT SDB00050BEB 33 AN2526FH Technical Data (continued) 1. Serial interface description (continued) 3) I2C bus control mode (continued) (6) Pulse timing (continued) Parameter SCLK clock frequency Bus free-time for stop condition and start condition Hold time start condition SCLK clock low-state hold time SCLK clock high-state hold time Data hold time Data setup time S-data, SCLK signal rise time S-data, SCLK signal fall time Stop condition setup time (7) Mode setting channel bits table D7 D6 to D4 D3 0 0 0 0 0 0 0 Mode Don't Care 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Selection channel 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 EVR control function Vertical sync. signal output position Horizontal sync. signal output position PWM duty Common pulse amplitude Y-gain Color gain Hue Black-limiter level Brightness Y-aperture gain R-ch. sub-brightness B-ch. sub-brightness White peak limiter Gamma-1 Knee level Gamma-2 Knee level RGB contrast Number of bits 3 5 6 7 8 7 7 8 8 8 8 8 8 8 8 7 Symbol tSCL tBUF tHDSTA tLOW tHIGH tHDDAT tSUDAT tr tf tSUSTO Min 0 1.3 0.6 1.3 0.6 0 100 0.6 Typ Max 400 300 300 Unit kHz s s s s s ns ns ns s In case that the channels have 8 bits or less of data bits number, the data in the data block is used to set various modes. The content of each mode setting is same as three-wire control mode 34 SDB00050BEB AN2526FH Technical Data (continued) 2. Recommended Operating Conditions Parameter Composite video input signal (Sync. chip - white) Y-input signal voltage (Pedestal - white) C-input signal voltage (Burst signal amplitude) MOS input signal low-level voltage MOS input signal high-level voltage Synchronous signal input (Pedestal - sync. chip) Serial data transfer frequency Analog RGB input signal (Pedestal - white) Symbol YIN YIN CIN VMOSL VMOSH HSync fSD RGBIN Min 0.9 0.6 200 0 4.2 0.2 0.6 Typ 1.0 0.7 300 0.3 0.7 Max 1.1 0.8 400 0.8 * 0.4 1.0 0.8 Unit V[p-p] V[p-p] mV[p-p] V V V[p-p] MHz V[p-p] Note) *: Set it lower than VCC1 (Pin 1 voltage). 3. Power dissipation of package QFP064-P-1010 PD T a 1.600 1.576 1.400 Mounted on standard board (glass epoxy: 75 x 75 x t0.8 mm3) Rth(j-a) = 79.3C/W 1.200 Power dissipation PD (W) 1.000 0.814 0.800 0.600 Independent IC without a heat sink Rth(j-a) = 153.5C/W 0.400 0.200 0.000 0 25 50 75 100 125 150 Ambient temperature Ta (C) SDB00050BEB 35 AN2526FH New Package Dimensions (Unit: mm) * QFP064-P-1010A (Lead-free package) 12.000.20 10.000.20 48 49 33 32 (1.25) 10.000.20 12.000.20 0.100.10 1.950.20 64 1 0.50 17 16 0.180.05 (1.25) 0.10 M 0.10 Seating plane (1.00) 0.150.05 0 to 10 0.500.20 36 SDB00050BEB Request for your special attention and precautions in using the technical information and semiconductors described in this material (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuits examples of the products. It neither warrants non-infringement of intellectual property right or any other rights owned by our company or a third party, nor grants any license. (3) We are not liable for the infringement of rights owned by a third party arising out of the use of the product or technologies as described in this material. (4) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (5) The products and product specifications described in this material are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (6) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage, and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (7) When using products for which damp-proof packing is required, observe the conditions (including shelf life and amount of time let standing of unsealed items) agreed upon when specification sheets are individually exchanged. (8) This material may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd. 2002 JUL |
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