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| AN45 Application Note CDB5504 CAPTURE INTERFACE By John Lis INTRODUCTION The CDB5504 evaluation board requires a simple modification to interface with the CAPTURE board. The CAPTURE board requires an SCLK input signal to collect data. However, the SCLK pin on the CS5504 is a digital input only. For the CDB5504 to interface with the CAPTURE board, an SCLK signal needs to be created. One possible solution is to derive the SCLK from the XOUT signal. The frequency of the XOUT pin is within the specifications for the SCLK signal and the serial port can accept a continuous clock. The CAPTURE board is designed to ignore extra clock signals on the SCLK line when using a continuous serial clock. Using XOUT as the SCLK input signal is a simple modification of the evaluation board. It is easy to implement, requiring no extra components. The following steps describe the modifications. The source of the SCLK signal is the XOUT pin on the CS5504. Install a jumper on the CS5504 from U1-6 to U1-18. (Make sure that adjustments are made for the CAB5504 adapter board. U1-18 translates to U1-21 on the bottom of the evaluation board.) The 100 k resistor R25 needs to be removed to reduce the load upon XOUT. Next the 74HC125 buffer needs to be modified. U3-3 is isolated from the circuit, so there aren't two devices driving the SCLK node. Finally U3-8 is isolated, allowing U3B to be active and able to drive the SCLK output signal to the CAPTURE board. Figure 1 is a schematic for the modified evaluation board. The following check list summarizes the modifications. q q q q REMOVE R25 JUMPER U1-6 to U1-18 ISOLATE U3-3 ISOLATE U3-8 Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com Copyright (c) Cirrus Logic, Inc. 1998 (All Rights Reserved) FEB `98 AN45REV1 1 2 +5V C2 D1 + 6.8V 10 F GND + C3 D2 6.8V -5V 10 F C4 0.1 F C5 0.1 F +5 C9 0.1 F + External VREF _ 402 AIN2R28 100k AIN2+ R29 100k AIN1R30 100k AIN1+ R31 100k 402 R6 402 R5 402 R4 R7 2 4 MODIFICATIONS TO THE CDB5504 FOR INTERFACING TO CDBCAPTURE +5 CAL R22 10 R9 +5 +5 AGND DGND R27 1K R26 1K C19 10nF C20 10nF C7 0.1 F 14 VA+ 10 17 VD+ CAL 4 C17 TP10 12 13 3 VREF+ VREFCONV TP9 CS 2 TP8 6 TP7 10 TP11 11 TP12 R23 100k R24 100k U2E 12 SDATA 14 U2F 8 15 SCLKO U2D 9 U2C 7 0.1 F 1 2 4 U2B 5 VD+ R18 A0 R19 100k 47k VD+ R20 100k U2A 3 47k CS VD+ R17 VD+ CONV VD+ C10 0.1 F + C16 10 F +5 +5 DRDY SCLK C11 0.01 F R10 20k R11 100k J2 CAL SDATA 1A -5 1B 6 R8 C8 25k 0.1 F 2A 2B 3A 3B LT1019 -2.5 V 5 A0 1 A1 U1 CS5504 DRDY TP3 11 TP4 9 AIN2+ TP5 10 TP6 8 AIN1+ AIN1AIN2SDATA 18 20 DRDY 19 TP13 C12 0.01 F C13 0.01 F C14 C15 TP15 0.01 F 0.01 F R3 50 VA- XIN 15 5 5 U3B 6 0.1 F VD+ R25 4 100k VD+ 14 2 C18 U3A R1 3 R16 100k TP14 1 100k 7 12 11 BP/UP U3D 13 7 VD+ R21 U3C 47k 8 9 10 SCLK XOUT DGND 16 6 Y1 32.768 kHz SCLKI BP/UP J1 U2 74HC4050 U3 74HC125 S2 A1 A0 CONV BP/UP CLKIN R2 200 -5 C1 0.1 F Note: Remove R25 Isolate U3-3 Isolate U3-8 Jumper U1-6 to U1-18 AN45REV1 AN45 Figure 1. Schematic of CDB5504 Modified for the CAPTURE Interface * Notes * |
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