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ICs for TV
AN5693K
Luminance, chroma and sync. signals processing IC (with built-in I2Cbus interface) for PAL/NTSC color-TV
Unit : mm
I Overview
The AN5693K is an IC that processes PAL-and NTSC-compatible video,chroma,RGB and sync. signals.
1
52
* Built-in I2C-bus control interface. * SECAM-compatible together with the AN5637 SECAM signal processing IC.
I Applications
* TV (Multi-system compatible)
26 13.70.3
27 (0.7) 3.850.3 (3.3)
47.70.3
I Features
0.25 -0.05
3 to 15 (15.24)
+0.2
SDIP052-P-0600A Note) The package of this product will be changed to lead-free type (SDIP052-P-0600F). See the new package dimensions section later of this datasheet.
1.778
0.50.1 1.00.25
Publication date: December 2001
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2
Video Out Hor. VCO Video In 50/60Hz Det. Out AFC1 AFC2 V-Out SECAM FBP In GND(VCJ) N.C. Y In H-Out -(B-Y)Out X-ray 43 48 47 46 45 44 42 41 40 Ver. Clamp 32 BL Det. 30 Hor. Sync. In 34 Ver. Sync. In 33 VCC3(VCJ) 35 5V C In 36 VCC2 39 38 37 31 29 28 27 Ver. out Hor. sync. sep. LPF Trap Ver. sync. sep. *6-bit Sharpness *7-bit HVBLK APC ACC det. 1H FF System SW PAL BPF NTSC BPF Chroma SW *1-bit Y clamp DAC SW out out B drive cut off I2C bus interface *7-bit *9-bit *7-bit
Ext. Ext. Ext. DAC1 DAC2 DAC3
AN5693K
SCP
I Block Diagram
-(R-Y)Out
-(B-Y)In Shut down HVCO CV clamp *1-bit *4-bit Hor. HBLK SCP reg. Video adjust BGP Hor. lock det. AFC1 *4-bit AFC2 Hor. count down 50/60Hz detect *1-bit B-Y demod Ver. count down *2-bit (50/60Hz) Killer ident Y contrast Black expansion
49
Saturation
Chroma contrast
-(R-Y)In 52
51
50
*1-bit PN/S SW
*7-bit
R-Y demod +/-
G-Y
*8-bit
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Brightness Tint *7-bit CW generate ACC amp.
B-Y clamp
*1-bit (Service)
G-Y clamp R drive cut off G cut off (8-bit)
R-Y clamp *1-bit *Drive 8-bit Chroma *Cut off 9-bit YS VCO pulse 10 11 12 13 5 6 7 8 9
14
16
17
18
19
20
21
22
23
24
25
26
15
1 YS APC Killer Out Spot Killer VCO 4.43MHz VCO 3.58MHz
2
3
4
R-In
B-In
SCL
G-In
ACL
SDA
Killer
B-Out
G-Out R-Out
VCC1 9V
R-Clamp
B-Clamp
G-Clamp
Lock Det.
Ext. DAC1
Ext. DAC2
Ext. DAC3
GND(RGB)
GND(Ext. DAC)
AN5693K
I Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Description (R-Y)Clamp (G-Y)Clamp (B-Y)Clamp Killer Filter Killer Output Chroma APC Filter Chroma VCO 4.43 MHz Chroma VCO 3.58 MHz Spot Killer YS Input(Fast Blanking) External R Input External G Input External B Input VCC1 R Output G Output B Output Hor. Lock Detect GND(RGB/I2C/DAC) ACL SDA SCL GND(EXT DAC) External DAC 1 DC External DAC 2 DC External DAC 3 DC Pin No. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 N.C. Video Level Adjust Input Video Level Adjust Output Black Level Det/Blank Off SW Y Input Ver. Sync. Clamp Ver. Sync. Input Hor. Sync. Input VCC3(Chroma/Jungle/DAC) Chroma Input/Black Exp. Start GND(Video/Chroma/Jungle) FBP Input VCC2(Hor. Stability Supply) Hor. AFC 2 Filter Hor. AFC 1 Filter Hor. VCO(32 fH) X-Ray Protection Input Hor.Pulse Output Ver. 50/60 Hz Detect Output Ver. Pulse Output SECAM Interface/CW Output -(B-Y)Output -(R-Y)Output Sandcastle Pulse Output -(B-Y)Input -(R-Y)Input Description
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AN5693K
I Absolute Maximum Ratings
Parameter Power supply voltage Symbol VCC ICC VCC1(14) VCC3(35) Power supply current I14 I35 I39 Power dissipation
*2 *1
Rating 10.5 6.0 77 119 27 1 372 -20 to +70 -55 to +150
Unit V
mA
PD Topr Tstg
*1
mW C C
Operating ambient temperature Storage temperature
Note) *1: Except for the operating ambient temperature, and storage temperature, all ratings are for Ta = 25C. *2: The power dissipation shown is the value for Ta = 70C. (Refer to "Technical Information")
I Recommended Operating Range
Parameter Operating supply voltage range Symbol VCC1 VCC3 Operating supply pin voltage V5 V9 V10 V11 V12 V13 V21 V22 V24 V25 V36 V38 V43 V45 V47 Range 8.1 to 9.9 4.5 to 5.5 0 to 6 0 to V14 0 to 6 0 to 6 0 to 6 0 to 6 0 to 6 0 to 6 0 to V14 0 to V14 0 to V14 0 to V47 0 to 2 0 to 6 0 to V14 V Unit V
Note) Do not apply external currents or voltage to any pins not specifically mentioned. For ciicuit currents, '+' denotes current flowing into the IC, and '-' denotes current flowing out of the IC.
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AN5693K
I Recommended Operating Range
Parameter Operating supply circuit current Symbol I39 I15 I16 I17 I28 I29 I33 I34 I44 I46 I47 Range 10 to 25 - 6.0 to + 0.6 - 6.0 to + 0.6 - 6.0 to + 0.6 - 0.3 to + 0.1 - 2.4 to + 0.8 - 0.8 to + 0.1 - 0.8 to + 0.1 - 6.4 to + 0.1 - 0.8 to + 0.1 - 0.3 to + 0.1 Unit mA
Note) Do not apply external currents or voltage to any pins not specifically mentioned. For ciicuit currents, '+' denotes current flowing into the IC, and '-' denotes current flowing out of the IC.
I Electrical Characteristics at Ta = 25C
Parameter Power supply Supply current 1 Supply current 2 Steady state supply voltage Steady state supply Current Steady state supply input resistance Interface Video adjust gain Video adjust output resistance VPO RO29 DC measurement 20 log DC measurement output (0A = F8) output (0A = 08) 5 70 3.10 2.10 7.8 0.1 6 120 3.40 2.40 8.1 0.8 7 170 3.70 2.70 8.7 1.0 dB V V V V Symbol DAC data is standard. I14 I35 V39 I39 R39 Current when V14 = 9 V Current when V35 = 5 V When pin 39 current I = 15 mA, pin 39 voltage Current when V39 = 5 V DC measurement input resistance when I39 = 10 mA to 25 mA 38 48 5.8 2 1 48 60 6.5 5 5 58 72 7.2 7 10 mA mA V mA Conditions Min Typ Max Unit
External DAC 1 DC voltage VEXT1max Pin 24 DC voltage when DAC 0C = 00 (max.) DC measurement External DAC 1 DC voltage VEXT1min Pin 24 DC voltage when DAC 0C = 7F (min.) DC measurement External DAC 2 DC voltage VEXT2max Pin 25 DC voltage DAC 0B = 00, 04D7 = 0 (max.) DC measurement External DAC 2 DC voltage VEXT2min Pin 25 DC voltage DAC 0B = FF, 04D7 = 1 (min.) DC measurement
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AN5693K
I Electrical Characteristics at Ta = 25C (continued)
Parameter Interface (continued) External DAC 3 DC voltage VEXT3max Pin 26 DC voltage when DAC 0D = 7F (max.) DC measurement External DAC 3 DC voltage VEXT3min Pin 26 DC voltage when DAC 0D = 00 (min.) DC measurement External DAC 1 maximum output current External DAC 3 maximum output current Video signal processing Video output (typ.) Video output (max.) Video output (min.) Contrast variable range Video frequency characteristics Sharpness variable range Pedestal level (typ.) Pedestal variable range IEXT1max IEXT3max Pin 24 DC current when DAC 0C = 7F DC measurement Pin 26 DC current when DAC 0D = 7F DC measurement DAC 03 = 40(typ.),(Contrast) DAC 03 = 7F(max.),(Contrast) DAC 03 = 00(min.),(Contrast) f = 0.2 MHz as reference to -3 dB. DAC 0E D1 = 1,DAC 04 = 00(Sharp) 5.50 0.90 200 1.0 6.00 1.00 6.50 1.15 V V A mA Symbol Conditions Min Typ Max Unit
Input: 0.6 VPP (VWB = 0.42 V0P stair-step) at G-out VYO VYOmax VYOmin fYC 1.65 3.60 0.07 20 5.5 9 1.9 2.0 8 3.2 2.1 0.3 0.5 9 2.10 4.50 0.25 25 6.8 13 2.5 2.6 11 3.7 2.7 0.5 1.0 100 2.55 5.35 0.50 33 17 3.1 3.2 14 4.2 3.2 0.9 1.5 110 VPP VPP VPP dB MHz dB V V mV/step V V/V V V %
YCmax/min DAC 03 = 7F,DAC 03 = 00
YSmax/min f = 3.8 MHz,DAC 0E D1 = 1 Sharp : (04 3F)/(04 00) VPED VPED DAC 02 = 80(typ.),(Brightness) Difference between DAC 02 = 00 & FF (Brightness) Average variable range of DAC 02 = 60 & A0 Pin 31 clamp voltage When V20 = 3.0 V-3.5 V 2 times of Y-out increase Reduse pin 30 voltage; the voltage when blanking is off Blanking pulse DC voltage. APL : 10% to 90%,TDC (AC - DC) 100% TDC AC DC measurement IC : internal sink current ACL pin 20 voltage reduces from 5 V until output is lesser by 10%
Brightness control sensitivity VBRT Video input clamp voltage ACL sensitivity VYCLP ACL
Blanking off threshold voltage VBOFF Blanking level DC transmission quantity VYBL TDC
Video input clamp current ACL start point
IYCLP VACL
8 3.4
13 3.7
18 4.0
A V
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AN5693K
I Electrical Characteristics at Ta = 25C (continued)
Parameter Color signal processing Symbol Conditions Min Typ Max Unit All tests on: Burst 300 mVPP (PAL), typ.: B-out Input: Color bar DAC 00 = 40(typ.), DAC 03 = 40(typ.) Input: Color bar DAC 00 = 7F, DAC 03 = 40 Input: Color bar DAC 00 = 00, DAC 03 =40 Input: Rainbow Burst increase from 300 mVPP 600 mVPP ACC.characteristics 2 NTSC tint centre NTSC tint adjustable range 1 NTSC tint adjustable range 2 Demodulation output ratio (R) PAL,NTSC Demodulation output ratio (G) PAL,NTSC Color difference output angle (R) PAL,NTSC Color difference output angle (G) PAL,NTSC Color killer tolerance (PAL) ACC2 C 1 2 R/B G/B R G VKILLP Input: Rainbow Burst decrease from 300 mVPP 60 mVPP Difference -13 between DAC 01 = 40 & when tint is centre Input: Rainbow, DAC 01 = 7F(Tint) Input: Rainbow, DAC 01 = 00(Tint) Input: Rainbow Ratio of R-out/B-out Input: Rainbow Ratio of G-out/B-out Input: Rainbow Input: Rainbow Input: Color bar, 0 dB = 300 mVPP Attenuate input level Input: Color bar, 0 dB = 300 mVPP Attenuate input level Input: Color bar High side pull-in range Input: Color bar Low side pull-in range Voltage at pin 5 when chroma signal is inputed VKBW Voltage at pin 5 when no chroma signal is inputed 0 0.1 0.5 V 30 -65 0.71 0.31 78 224 -57 -57 450 4.5 0 50 -50 0.83 0.37 90 236 -44 -44 900 13 65 -30 0.95 0.43 102 248 -34 -34 Step Deg Deg Times Times Deg Deg dB dB Hz Hz V 0.7 1.0 1.1 Times 2.6 2.3 0 20 0.9 3.3 3.0 25 1.0 4.0 100 33 1.2 VPP VOP mVPP dB Times
Color difference output (typ.) VCOtyp Color difference output (max.) VCOmax Color difference output (min.) VCOmin
Chroma contrast variable range CCmax/min DAC 00 = 40,DAC 03 = 7F,DAC 03 = 00 ACC.characteristics 1 ACC1
Color killer tolerance (NTSC) VKILLN APC pull-in range (H) PAL,NTSC APC pull-in range (L) PAL,NTSC Color killer detector output voltage (Color) Color killer detector output voltage (B/W) fCPH fCPL VKC
-900 - 450 5.0
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AN5693K
I Electrical Characteristics at Ta = 25C (continued)
Parameter Symbol Conditions Min Typ Max Unit Color signal processing (continued) Demodulation output-(B-Y) PAL,NTSC Demodulation output-(R-Y) PAL,NTSC Demodulation output angle B PAL,NTSC Demodulation output angle R PAL,NTSC CW output level(4.43 MHz) CW output level(3.58 MHz) SECAM output CW period SECAM detector current VDB VDR RDB RDR VCWP VCWN TCW ISECAM All tests on: Burst 300 mVPP (PAL), typ.: B-out Input: Color bar (NTSC: Adjust to tint centre)Measure pin 48 Input: Color bar (NTSC: Adjust to tint centre)Measure pin 49 Input: Rainbow Phase difference of B-Y axis Input: Rainbow Phase difference of B-Y and R-Y axis AC component at pin 47 when VCO is at 4.43 MHz AC component at pin 47 when VCO is at 3.58 MHz 555 430 -5 85 250 695 540 0 90 300 0 1.41 100 1.30 4.6 480 835 650 5 95 350 50 1.51 150 1.65 5.1 570 mVPP mVPP Deg Deg mVPP mVPP ms s V V
Period of CW is outputed when in SECAM 1.31 Minimum current from pin 47 when SECAM is detected PAL/NTSC output DC voltage at pin 47 SECAM output DC voltage at pin 47 50 0.80 4.1 390
PAL/NTSC output DC voltage V47PN SECAM output DC voltage Demodulation output impedance (PAL/NTSC) -(R-Y), -(B-Y) Demodulation output impedance (SECAM) -(R-Y), -(B-Y) RGB processing V47S
RO48,49PN Pin impadance of pin 48, pin 49 in PAL/ NTSC mode RO48,49S Pin impadance of pin 48, pin 49 in SECAM mode
100
k
DAC data standard VIPL VBL GYC TCONT GDV R,G,B out pedestal difference voltage DAC 02 = 40 to C0 (Brightness). Ratio of variable level R,B out output ratio with G-out DAC 03 = 20 to 60 ratio (contrast) of gain R,B out AC adj. amount Driver DAC 08 = 00 to FF Driver DAC 09 = 00 to FF 0 0.9 0.8 0.9 5.3 1.0 1.0 1.0 6.3 0.3 1.1 1.2 1.1 7.3 V Times Times Times Times dB
Pedestal difference voltage Brightness voltage tracking Video voltage gain ratio Video voltage gain tracking Driver control characteristics
Cut-off control characteristics VCUTOFF R,G,B output DC cut off DAC range from min.to max. YS threshold voltage VYS Smallest level when YS is on
1.9 0.7
2.4 1.0
2.9 1.3
V V
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AN5693K
I Electrical Characteristics at Ta = 25C (continued)
Parameter Symbol DAC data standard VEPL YS is on YS is on Internal-External Input 3 VPP, DAC 03 = 7F(Contrast) Input 3 VPP, DAC 03 = 7F(Contrast) 1.7 0 50 4.3 - 0.6 10 8 2.3 200 5.4 0 13 12 2.9 250 400 6.5 + 0.6 16 V mV mV VPP V dB MHz Conditions Min Typ Max Unit RGB processing (continued) External RGB DC Voltage
External RGB pedestal VEPL difference voltage(R/B)(G/B) Internal/External pedestal difference voltage VPL/IE
External RGB output Voltage VERGB External RGB output difference voltage External RGB contrast control characteristics External RGB frequency characteristics VERGB
ECmax/min DAC 03 = 7F, DAC 03 = 00 fRGBC Input 0.2 VPP, DC = 1 V
Synchronizing signal processing Horizontal output free run frequency Horizontal output pulse duty Horizontal output pull-in range Vertical free run frequency (PAL) Vertical free run frequency (NTSC) Vertical output pulse width NTSC,PAL Vertical pull-in range (PAL) Vertical pull-in range (NTSC) Horizontal output voltage (H) Horizontal output voltage (L) Vertical output voltage (H) Vertical output voltage (L) Screen centre variable range fHO HO fHP fVO-P fVO-N VO fVPP fVPN V44H V44L V46H V46L THC No input signal The frequency at pin 44 Horizontal output pulse's high level's duty 15.33 15.63 15.93 31 37 43 52 62 11 54 64 3.8 0.3 4.5 0.3 4.4 kHz % Hz Hz Hz 1/fH Hz Hz V V V V s
Horizontal sync. sep. freq. pull-in approach- 500 650 ing 15.625 kHz Forced 50 Hz mode, DAC 0E-D2 = 1 D3 = 0, No sync.signal input Forced 60 Hz mode, DAC 0E-D2 = 1 D3 = 1, No sync.signal input Hor. & Ver.sync. condition,the pulse width at pin 46 fH = 15.625 kHz, Forced 50 Hz mode fH = 15.75 kHz, Forced 60 Hz mode Horizontal output pulse's high level's DC voltage Horizontal output pulse's low level's DC voltage Vertical output pulse's high level's DC voltage Vertical output pulse's low level's DC voltage Variable amount of phase between HSYNC & HOUT DAC 0A = 80 to 8F 48 58 9 46 56 3.2 0 3.9 0 2.6 50 60 10 3.5 4.2 3.2
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AN5693K
I Electrical Characteristics at Ta = 25C (continued)
Parameter Symbol Conditions Min Typ Max Unit Synchronizing signal processing (continued) Shut down operating Vertical frequency detection operation (50 Hz) Vertical frequency detection operation (60 Hz) Sync. separation input clamp voltage (Vertical) Sync. separation input clamp voltage (Horizontal) Horizontal output start voltage I2C interface Sinking current at ACK SCL,SDA signal input high level SCL,SDA signal input low level Input possible maximum frequency * Reference data for design
Note) The characteristic listed below are theoretical values based on the IC design and are not guaranteed.
V43L f50 f60 V33 V34 VfHS
Pin 43 minimum voltage when H-out does 0.60 not appear Vertical input freq.when the DC level at pin 45 = "L"(< 0.5 V) Vertical input freq. when the DC level at pin 45 = "H"(> 4.5 V) V33 clamp voltage V34 clamp voltage Minimum V38 when horizontal output is above 1 VPP, fo > 10 kHz 47 57 1.0 1.0 3.4
0.68 1.3 1.3 4.2
0.76 55 63 1.6 1.6 5.0
V Hz Hz V V V
IACK VIHI VILO fImax
When ACK, pin21 pin current with 2.2 k pull-up to 5 V
1.8 3.1 0 100
2.5
5.0 5.0 0.9
mA V V Kbit/s
Parameter Video signal processing Y signal delay time Black level correction 1 Black level correction 2 Black level correction 3 Contrast variation with sharpness Brightness variation with sharpness
Symbol
Conditions
Min
Typ
Max
Unit
Input: 0.6 VPP (VWB = 0.42 V0P stair-step) at G-out tDL VBLC1 VBLC2 VBLC3 VCS VBS Measure output's delay time with input (PAL = 4.43 MHz) 620 690 0 800 300 0 0 760 +100 1100 500 +300 +250 ns mV mV mV mV mV
All black input. Find the diff.of G-out when -100 pin 30 is 9 V & open All black input. Find the diff.of G-out when 500 pin 30 is 3 V & 9 V Input: About 20 IRE the diff.of G-out when pin 30 is open & 9 V Y-out output level difference when sharpness = max. to min. Pedestal DC level difference when sharpness = max. to min. 100 -300 -250
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AN5693K
I Electrical Characteristics at Ta = 25C (continued)
* Reference data for design (continued)
Note) The characteristic listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol
Conditions Contrast DAC 03 = 40 Measure at video input Pin31 Contrast DAC 03 = 7 F Start point when V36 = 4.5 V Trap on/off ratio Trap on/off When chroma input is 4.43 MHz, trap centre frequency from 4.43 M
Min
Typ
Max 47 +1 580 +70 5 6.3 200 10 30
Unit
Video signal processing (continued) Y input dynamic range Y S/N ratio Black level expansion start point Trap on/off gain difference VImax SNY VBLS GTRAP fTRAP
Input: 0.6 VPP (VWB = 0.42 V0P stair-step) at G-out 1.0 51 37 -1 480 -70 26 26 3 4.7 0 0 -10 1.7 56 42 0 530 0 30 30 5.5 100 5 10 VPP dB IRE dB ns kHz dB dB MHz MHz mV/V % ns
Trap on/off delay time variation tTRAP Trap frequency tolerance Trap attenuation 4.43 MHz Trap attenuation 3.58 MHz Trap automatic adjustment range Trap set frequency Video signal output VCC variation Video signal output temperature VY/T variation PAL/NTSC delay time difference Color signal processing Demodulation output residue carrier tP/N
ATTTRAPP When chroma input is 4.43 MHz, 4.43 MHz component attenuation ATTTRAPN When chroma input is 3.58 MHz, 3.58 MHz component attenuation fTRAP fST VY/V VCO frequency of fTRAP 70 kHz DAC 0 E-D6 = 1 Trap's frequency VCC1 = 9 V ( 10%) Ta = -20C to +70C Trap on(NTSC-PAL)
All tests on: Burst 300 mVPP(PAL)standard is B-out VCAR1 Pin 48, pin 49 output's 2nd harmonics Pin 15, pin 16, pin 17 output's 2nd harmonics Compare with standard f = 4.433619 MHz Compare with standard f = 3.579545 MHz VCC1 = 9 V ( 10%) VCC3 = 5 V ( 10%) Tint change when fC = -300 Hz to +300 Hz 0 0 -300 -300 -300 0 0 0 0 2 30 50 +300 +300 +300 5 mV mV Hz Hz Hz deg 100 Hz
Color difference output residue VCAR2 carrier VCO free run frequency (PAL) VCO free run frequency (NTSC) VCO VCC variation Phase hold characteristic (PAL) fCP fCN fC VCC P
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AN5693K
I Electrical Characteristics at Ta = 25C (continued)
* Reference data for design (continued)
Note) The characteristic listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol N RP/N VPAL fCC BPFP BPFN VC/V VC/T VBC VBC
Conditions
Min
Typ
Max
Unit
Color signal processing (continued) Phase hold characteristic (NTSC) Color difference output PAL/NTSC ratio Line crawling Color difference output frequency characteristics Chroma BPF characteristics (PAL) Chroma BPF characteristics (NTSC) Color difference output VCC variation Color difference output Temperature variation Color variation to brightness variation Color to brightness variation voltage RGB processing (C-Y)/Y ratio C-Y,Y delay difference YS switching speed Exeternal RGB input dynamic range RC/Y tC/Y fYS VDEXT
All tests on: Burst 300 mVPP(PAL)standard is B-out Tint change when fC = -300 Hz to +300 Hz R out PAL/R out NTSC Pin49: -(R-Y)out every 1 H output difference in voltage Bandwidth when gain reduces by 3 dB f = 4.43 MHz -2.00 MHz output level difference f = 3.58 MHz to2.00 MHz output level difference VCC1 = 9 V ( 10%) VCC3 = 5 V ( 10%) Temperature: -20C to +70C When color: max.to min. the difference in pedestal DC RGB output variation voltage difference 0 20 mV 0 0.8 0 - 250 2 1.0 1.0 32 22 10 10 0 5 1.2 50 15 15 + 250 deg 100 Hz Times mV MHz dB dB % % mV
Input: Color bar. B-out, contrast: typ. Color: DAC 00 = 60 Input: Color bar, B-out Green = magenta delay External input 3 V output level when at -3 dB frequency DAC 03 = 7 F(Contrast : max.) f = 1 MHz 1 VPP The crosstalk level when YS = 5 V Voltage at pin 9 from V9 = 9 V reduces until spot killer is on When contrast is max.to min., the diff. in pedestal DC
0.9 -100 7 2.0 7.4 -250
1.2 0 11 2.5 -60 7.8 0
1.5 +100 3.2 -50 8.2 +250
VOP VPP ns MHz VOP dB V mV
Internal/External RGB crosstalk CTRGB Spot killer operation Contrast variation to brightness variation VSPK VBAC
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AN5693K
I Electrical Characteristics at Ta = 25C (continued)
* Reference data for design (continued)
Note) The characteristic listed below are theoretical values based on the IC design and are not guaranteed.
Parameter
Symbol VBAC VCBW VPL/V VPL/T VPD2
Conditions
Min
Typ 0 200 -2.2 2.7
Max
Unit
RGB processing (continued) Contrast to brightness variation voltage RGB output color/BW DC difference voltage Pedestal level VCC variation Pedestal level temperature variation Pedestal level 2 RGB output variation voltage difference Difference in pedestal voltage between burst on/off Pedestal level change when VCC1 = 9 V ( 10%) Pedestal level change when temperature is -20C +70C The pedestal level when G cutoff DAC 05 = 18 0 - 60 0 -2.6 2.1 20 + 60 400 mV mV mV/V
-1.8 mV/C 3.3 V
Synchoronizing signal processing Lock detector output voltage Lock detector charging current FBP input slice level (RGB) FBP input slice level (AFC2) Horizontal AFC Horizontal VCO- curve Burst gate pulse position NTSC,PAL VLD ILD VFBP VFBPH H H PBGP Pin18 DC voltage when horizonal AFC is locked DC measurement Minimum voltage at which blacking of RGB outputs happens Minimum voltage at which AFC 2 operates Calculate from AFC current DC measurement Slope of curve near to f = 15.7 kHz When hor. AFC is on, hor. sync. rising edge to the BGP rising edge When hor. AFC is on, BGP's pulse width When hor. AFC is on, BGP's pulse width Pin50 DC voltage during BGP period Pin50 DC voltage during H-blanking period 5.7 0.6 0.40 1.5 30 1.4 0.2 3.4 2.5 4.5 2.1 6.3 0.8 0.75 1.9 37 1.9 0.4 4.0 3.0 4.7 2.4 2.4 1.41 1.11 6.9 1.1 1.10 2.3 44 2.4 0.6 4.6 3.5 4.9 2.7 2.7 1.51 1.21 19 V mA V V A/s Hz/mV s s s V V V ms ms s
Burst gate pulse width (PAL) WBGPP Burst gate pulse width (NTSC) WBGPN Burst gate pulse output voltage Horizontal blanking pulse output voltage Vertical blanking pulse output voltage Vertical blanking pulse width (PAL) Vertical blanking pulse width (NTSC) FBP allowable range VBGP VHBLK VVBLK WVP WVN TFBP
Pin50 DC voltage during V-blanking period 2.1 Pulse width when fH = 15.625 kHz Pulse width when fH = 15.73 kHz delay from hor. output rising edge to FBP centre 1.31 1.01 12
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AN5693K
I Electrical Characteristics at Ta = 25C (continued)
* Reference data for design (continued)
Note) The characteristic listed below are theoretical values based on the IC design and are not guaranteed.
Parameter I2C interface
Symbol
Conditions 1 LSB = {Data(max.)-Data(00)}/15(4-bit), 63(6-bit), 127(7-bit) 1 LSB = {Data(FF)-Data(00)}/255(8-bit) The overlap between the two 8-bit sections of R,B cutoff & AFT
Min
Typ 1.0 1.0 32
Max 1.0 0.35 3.5 1.9 1.9 37
Unit s s s s s s s s s s s s LSB Step LSB Step Step
Bus free before start Start condition set-up time Start condition hold time "L" period SCL, SDA "H" period SCL Rise time SCL,SDA Fall time SCL,SDA Data set-up time (Write) Data hold time (Write) Acknowledge set-up time Acknowledge hold time Stop condition set-up time DAC 4,6,7-bit DAC DNLE 8-bit DAC DNLE Cut off DAC overlap
tBUF tSU,STA tHD,STA tLOW tHIGH tr tf tSU,DAT tHD,DAT tSU,ACK tHD,ACK tSU,STO L4,6,7 L8 Step
4.0 4.0 4.0 4.0 4.0 0.25 0 0 4.0
0.1 0.1 27
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AN5693K
I Electrical Characteristics at Ta = 25 C (continued)
* Description of test circuits and test methods 1.Input signal (1) Video (2) Chroma : 10 stairs waveform 0.6 VPP(VBW = 0.42 VOP) : Color bar signal : Burst level 300 mVPP
Rainbow signal : Burst level 300 mVPP (3) Synchronous : Horizontal, vertical synchronous signal input are 1.5 VPP to 2.5 VPP 2.I2C bus condition : (PAL) Sub address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E Data(H) 40 40 80 40 80 00 00 00 80 80 88 01 40 40 01 Control Color Tint Brightness Contrast Sharpness Cutoff R,B Cutoff G Driver R,B Video output Hor.centre External DAC 2 External DAC 1 External DAC 3 Data(H) 00 = 40 01 = 40 02 = 80 03 = 40 04 = 00 05, 07 = 00 06 = 00 08, 09 = 80 0A(upper byte) = 8* 0A(lower byte) = *8 0B = 01 (04-D7=1) 0C = 40 0D = 40
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AN5693K
I Pin Equivalent Circuit
Pin No. 1 2 3
C-Y 300 300
Equivalent circuit
9V (VCC1) Pin 1,2,3 0.068 F
Function Pin1 : Color Difference Clamp Pin(R-Y) Pin2 : Color Difference Clamp Pin(G-Y) Pin3 : Color Difference Clamp Pin(B-Y) * Input from Pin51, 52, the color difference signals are clamped according to brightness control voltage
Status DC about 7 V
CCP 150 A
Brightness control
* The clamp pulse uses internal clamp pulse
5V (VCC3)
4
Killer Filter Pin : * Killer detection circuit's filter pin (operate during BGP period) * Below 2.8 V, killer is on(no color output)
DC about 3.3 V
Killer det. circuit
3.3 V 1V 137 k 4 270 2.5 V 1.0 M 0.47 F 9 V (VCC1)
BGP
2.8 V 100 A
5
5 V (-com. VCC) 33 k to -com. 5 Floating resistor
Killer Output Pin : * Killer detection circuits output pin * Pin5 pull-up resistor, 33 k, is connected Killer On Off to MICOM's VCC.
DC Killer on 0.2 V Killer off 5V
175
40 A 10 k
6
5V (VCC3)
APC Filter Pin : * APC detector circuit's filter pin (operate during BGP period) * As external resistor, R, becomes larger,
DC about 2.5 V
0.022 F
APC det. circuit
3.3 V 1V
40 k SW
6 2.2 F
detection sensitivity becomes larger (pull in becomes easier. Interference by noise becomes easier)
curve fC
2.5 V 7.5 k R BGP 270 max. 1mA VCO circuit
V6
* During SECAM mode, the 40 k is shorted to stop APC circuit's operation 16
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AN5693K
I Pin Equivalent Circuit (continued)
Pin No. 7 8 Equivalent circuit Function Pin7 : Chroma Oscillator Pin(4.43 MHz) Status AC f = fC about 0.3 VPP
IP2 100 A
IP1 500 A
4.43 MHz 7 DC 2.7 V C7 12 pF DC 2.7 V 3.58 MHz 8 C8 15 pF
Pin8 : Chroma Osicillator Pin(3.58 MHz) * At chroma oscillator pin, either 4.43 MHz or 3.58 MHz oscillation takes place * Oscillation frequency switching is done by I2C bus, 0E-D0 bit * When 0E-D0 =1, IP1, IP2 is on. 3.58 MHz is oscillating * The PCB layout pattern between the pin and the resonator must be as short as possible Spot Killer Pin : * When the set is power off, it is used for discharging the electric charge from
IN2 100 A 100 A
IN1
500 A C7, C8 have temperature characteristics(N750)
VCC1
9
9V (VCC1) 10 k To RGB output circuit 1.7 k 9
DC about 9 V
1 F 100 k
CRT quicky * When VCC1 reduces, RGB output pin's DC voltage rise YS Input Pin : * The fast blanking pulse input pin is for the OSD * Above 1 VOP is on AC (Pulse)
10
50 A From -com.
9V (VCC1) To RGB output circuit
10
2.7 k 30 k 100 A 1V
11 12 13 50 A 9V (VCC1) To RGB output circuit Pin 11,12,13 2.7 k
Pin11 : External R Input Pin Pin12 : External G Input Pin Pin13 : External B Input Pin * The external input pins are for the OSD * The output level changes linearly with the input level
AC (Pulse)
Contrast max. Output Contrast min. 2.5V (max.) Input * The Input's limiting voltage changes according to the contrast control level
From -com.
30 k
VREF
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17
AN5693K
I Pin Equivalent Circuit (continued)
Pin No. 14 Equivalent circuit Function VCC1 (typ. 9 V) : * IF circuit * Video circuit * RGB circuit 15 16 17 130 A 100 9V (VCC1) Pin15 : R out Pin Pin16 : G out Pin Pin17 : B out Pin * BLK level about 0.9 V * Black(pedestal)level about 2.2 V * If Pin30(Black level detection output pin)is 0 V, blanking is removed. Horizontal Synchronous Detection Output Pin :
(VCC2) 10 k 800 A I1 800 A I2 50 A 12 k 12 k 2.8 V To chroma circuit 5V (VCC3)
Status DC 9V
AC
Pin 15 16 17 50
C out 500 A
18
DC When synchronising about VCC2-VSAT When synchronising comes off about 0.3 V
* The phase between horizontal synchronous signal and horizontal output pulse is detected * When synchronising comes off, Pin18 voltage goes low * When not synchronising,color control is minimum,and chroma output disappears * In the case where Pin18 voltage is used by MICOM, impedance has to be taken care(Zo 1 M is required)
18 ZO 0.022 F
Pin 44 H-out
10 k
1 M
Pin 34 H-sync. in * H sync. period, Pin44 level is "H" : I1 on "L" : I2 on
19
GND : * RGB circuit * DAC I2C circuit * IF circuit
18
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AN5693K
I Pin Equivalent Circuit (continued)
Pin No. 20 Equivalent circuit Function Status DC about 3V
5.9 V 60 k 60 k 6.9 k 2.3 V 7.1 k Contrast control 7.1 k 6.9 k
9V (VCC1) To contrast circuit 2.1 V 6.9 k 3.5 V
ACL Pin : * When Pin20 DC voltage is externally decreased, contrast is limited
20 4.7 F
2.3 V 1V 100 A 100 A 100 A
21
5V (VCC3) 100 k Data 1 k 21 From -com. ACK 30 k 50 A 100 k 1.7 V
I2C BUS DATA Input Pin :
AC (Pulse)
To logic circuit 30 k I2C BUS CLOCK Input Pin :
22
5V (VCC3) 100 k Clock 1 k 22 From -com. 30 k 50 A 100 k 1.7 V To logic circuit 30 k
AC (Pulse)
23 24 100 A
GND : * External DAC circuit 5V External DAC 1 Pin : * External DAC 1 voltage is adjustable by using I2C bus 150 40 k
DC
24
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19
AN5693K
I Pin Equivalent Circuit (continued)
Pin No. 25
1.1 k 1.1 k
Equivalent circuit
9V (VCC1) 9V
Function External DAC 2 Pin : * External DAC 2 voltage is adjustable by using I2C bus through the change in DAC output current
Status DC
25 370 max. 350 A
To tuner
370
40 k
26
500
9V (VCC1)
External DAC 3 Pin : * External DAC 3 voltage is adjustable by using I2C bus
DC
10 30 k
Ext. DAC 26
56.25 k
27 28
9V (VCC1) Int. video
N.C. Pin Video Input Pin : * From VIF IC, the detected signal's (internal video signal)input pin * Input by DC cut * Standard input 1 VPP(max.1.5 VPP) 28
AC 1 VPP (composite)
50 A
2.35 V
680 k
10 F
DC level about 1.6 V
29 75 A
9V (VCC1)
Video Output Pin : * Adjustable to 2 VPP by I2C bus (use 0A upper 4-bit)
AC 1.75 VPP
29 800 A
20
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AN5693K
I Pin Equivalent Circuit (continued)
Pin No. 30 Equivalent circuit Function Status DC abuot 5.1 V
-Y 10 k 5.1 V
80 A
9V (VCC1)
Black level detecion output pin blanking off switch pin :
5 V * For black expansion circuit's black (VCC3) level detection output filter pin 80 k 75 k 10 k
* For removing the blanking period and holding the darkest Y level * By changing the external resistor, R, the black level expansion sensitivity can be changed. When R is bigger, area of response is smaller * To stop black expansion circuit, set Pin30 voltage to about VCC(9 V) * If Pin30 voltage is GND, blanking is off.(Black expansion is also off) Video Input Pin : AC 0.6 VPP
9V (VCC1) 50 A
100 A
To black expansion circuit To 30 blanking circuit 180 k R 4.7 F
31
47 k 4.3 V 31 10 A 1.8 k 43 k
* Video signal input pin (Composite video also allowable) * Standard input 0.6 VPP * Sync. top is clamped to 3.5 V * Video signal is inputed to low impedance inputs
32
5V (VCC3) 3 k 4.3 V 16 k 4 k R2 220 R1 200 680 k To ver. 270 count down 50 k
Vertical Synchronous Signal Clamp Pin : * This is the peak clamp pin for vertical synchronous signal separation * The integration of the vertical synchronous signal is determined by the internal time constant, but the external time constant, R1, C1, is chosen according to the required trigger timing * Using R1 > 200 k * R2 is the resistor which is used to control the emitter current
AC f = fV
32 C1 2.2 F
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21
AN5693K
I Pin Equivalent Circuit (continued)
Pin No. 33 34 Equivalent circuit Function Pin33 : Vertical Sync. Separation Input Pin Status AC 2 VPP
16 k 16 k 2 VPP
5V (VCC3) 16 k
Pin34 : Horizontal Sync. Separation Input Pin * Pin33, 34 internal circuits are similar
RV 560 1 F RH 270 CH 1200 pF
* Usually, vertical synchronous threshold To H sync. is deeper than horizontal synchronous' sep. threshold. Thus RV > RH To V sync. sep. * RH and CH determine cutoff frequency at about 500 kHz * R big, threshold becomes deeper
CV 680 pF 34 0.1 F
33
1.3 V 20 A 20 A
(Sync. compression is weaker). R small, threshold becomes shallower (fluctuation becomes weaker due to vertical sag) Sync. top is clamped at 1.3 V
35 36
Chroma signal 1000 pF 9V 10 k 36 10 k 100 A
5V (VCC3) To Chroma amp. 50 A 9V (VCC1) To black level expansion 25 A
VCC3 (typ.5V) : * For chroma and jungle circuit Chroma Signal Input Pin Black Expansion Starting Point Adjustment Pin : * Pin36 is chroma signal input pin and external DC voltage is applied to adjust the starting point of black expansion
DC 5V AC + DC Burst typ. 300 mVPP DC typ. 4.5 V
12.5 pF 15 k 2.5 V
37 38
GND : * For video,chroma and jungle circuit
DC 0V AC FBP
100 A 50 A 100 A
5V (VCC3) 50 A
FBP Input Pin : * The FBP input pin is for horizontal blanking and AFC circuit * Threshold level for HBLK : 0.7 V
1.9 V 24 k To 0.7 V 60 k 50 A
22
AFC To HBLK
AFC : 1.9 V * External DC 1.3 V must be applied to become all blanking
40 k
40 k
38
* Input voltage below 0 V is prohibited
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AN5693K
I Pin Equivalent Circuit (continued)
Pin No. 39 Equivalent circuit Function Horizontal Steady State Supply Pin : * Steady state supply is used by horizontal Status DC 6.5 V
I51 typ. 15 mA
VCC2 39
To hor. OSC
circuit startup. Internal voltage regulating circuit is present
V39 6.5 V
47 F
Voltage regulating circuit
I39
40 (VCC2) 2 k 2 k 1.9 V AFC2 det. circuit I From 40 DAC (hor. 1 k position) 0.022 F To hor. out V52
Horizontal AFC 2 Filter Pin : * FBP and IC internal pulse phase difference is compared. At Pin40, a capacitor is connected for charging and discharging this current * The current from the picture centre position adjustment DAC establishes 3.3 V 50 A DC by chaging and discharging current * Time difference from Hout to FBP-in depends on V40 which changes the slice level of internal sawtooth waveform Horizontal AFC 1 Filter Pin : (VCC2) 4.3 V R1 27 k AFC1 det. circuit 41 1.5V Hor. sync. 1000 A C2 10 F R2 2.2 k C1 0.018 F 200 A Hor. OSC 27 k * Horizontal synchrous signal and IC internal pulse phase difference is compared. At Pin41, a capacitor is connected for charging and discharging current * R1, R2, C1, C2, are lag-lead filter used by AFC 1
DC 1.5 V to 3.5 V
1 k
max. 500 A 41
DC typ. 4.3 V
Horizontal curve fH
V41
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23
AN5693K
I Pin Equivalent Circuit (continued)
Pin No. 42 Equivalent circuit
(VCC2)
Function Horizontal Oscillator Pin : * Oscillates by 32 x fH = 500 kHz ceramic resonator
22 k
Status AC f = 32 fH (about 500 kHz)
* Horizontal and vertical pulses are made by the IC internal count down circuit
42 100 A 200 A N750 220 pF
300 80 A 10 k 10 k Temperature characteristics present for N750
43
(VCC2) 40 k 4.3 V 20 k 20 k 3V To count down 20 k
Over Voltage Protection Input Pin : * Input pin is used by X-ray protector circuit for over voltage * By internal logic circuit, when H out pulse is low, shut down starts (Prevent damaging the horizontal drive transistor)
DC usually 0V
43
44
(VCC2) 4.3 V 19 k 50 44 3.5 V 10 k 0V Hor. out 40 k
Horizontal Pulse Output Pin : * Duty is about 37 %
AC (Pulse)
45
+5V(-com VCC) 33 k 45
5V (VCC3) 100 k
Vertical Frequency Detection Output Pin : * The output of the result of the internal counter of the vertical synchronous signal period * fV = 60 Hz : V45 is "H" = 50 Hz : V45 is "L"
DC 0V or 5V
To -com
24
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AN5693K
I Pin Equivalent Circuit (continued)
Pin No. 46
5V (VCC3) 50 k 46 4.2 V 0V 43 k
Equivalent circuit
Function Vertical Pulse Output Pin : * Nagative polarity pulse width is 10H
Status AC (Pulse)
47
56.2 k fC
12 k
13.7 k 61.5 k 200 A
9 V SECAM Interface Pin : (V ) 50 A 12 k CC1 * The input and output pin for the interfacing with the SECAM IC To * When above 100 A current is drawn SECAM from Pin47, system becomes SECAM IC mode 47 50 k 100 A
* When in non-SECAM, DC 4.6 V + AC 300 mVPP * When in non-SECAM, DC 1.3 V + AC 300 mVPP : 4.43 MHz or 0 mVPP : 3.58 MHz 5V (VCC3) Pin48 : -(B-Y)Output Pin Pin49 : -(R-Y)Output Pin * when in SECAM, output circuit is off - (B-Y) and output impedance is high impedance 48 * The outputs to 1 HDL - (R-Y) 49
AD + DC AC 300 mVPP or 0 mVPP DC 4.6 V or 1.3 V AC -(B-Y)
SECAM
48 49 100 A
SECAM SECAM det. circuit
100 A
100 A
AC -(R-Y)
SECAM 0V SECAM 2.5 k 1.5 k
To IHDL DC level 1.5 k about 2.5 V
SDB00022BEB
25
AN5693K
I Pin Equivalent Circuit (continued)
Pin No. 50 Equivalent circuit Function Status AC (Pulse)
4.7 V 2.4 V
45 k
5V (VCC3) 15 k
Sandcastle Pulse Output Pin : * Sandcastle pulse is outputed to1 HDL and SECAM IC
50 42 k H+V BLK
75 k
BGP
44 k
51 52
9V (VCC1) From 1HDL Pin51 52 4V 100 A
Pin51 : -(B-Y)Input Pin Pin52 : -(R-Y)Input Pin * From 1 HDL, color difference signal outputs are inputed to these pins
AC -(B-Y)
To * These pins are clamped at 4.7 V pedestal color level from the clamp circuit circuit * The input levels at Pin51, 20 are about
2 times the output amplitude of Pin48, 49 respectively
AC -(R-Y)
DC level 4.7 V
25 A
BGP 50 A
200 A 50 A
26
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AN5693K
I Application Circuit Example
Video In
75 10 F 68 0k
(Notes) *1=TS116M20 *2=TS816M32 *3=TAFCSB500F48
27 28 29 30
26 25 24 23 22 21 20 19
4.7 F 10 F 10 F 10 F
1 M
BL Det.
Video Out
180 k 2.2 k 1 k 2 k
150 k 150 k
4.7 F
GND(Ext. DAC)
4.7 k
4321
Y-In
680 k 10 F
31 32 33 34
SCL SDA ACL
1 M 4.7 k
Ver. Clamp
2.2 F 220 1 F 560 270 680 pF 0.1 F 120 0pF 47 F 1 000 pF 10 k 10 k
GND
18
VCC3
35 17 36 37
0.022 F
10 k
B
12345
C-In GND
16
1.5 k
G R VCC1 9 V B G R YS Spot Killer
AN5693K
FBP In VCC2
180
3.3 k
38 39 40 41 42
15 14 13 12 11 10 9 8 7 6
1.5 k
1.5 k
47 F 0.022 F 2.2 k 10 F
6.8 k
AFC2 AFC1
0.018 F
47 F
2.2 k
HOSC
*3
220 pF (N750)
X-ray 43
10 k
54321 123
H-Out 50/60 Hz V-Out
33 k
44 45 46 47
*2 15 pF
(N750)
3.58 MHz
12 pF
*1
(N750)
4.43 MHz
15 k
33 pF
IC 402
(8 V)
1 2
16
0.022 F
CW
IC 401
2.2 F
15 k
APC
15 22 H 14 13 12 11 10 9
1 2 3
16 15 0.01 F 14
0.01 F
48
5 4 3 2 1
0.022 F 33 k 0.47 F 0.068 F 1 M 0.068 F 0.068 F
SECAM DECODER
0.022 F 47 F
51
3 4 5 6 7
1HDL
AN78M05
4 5 6 7 8
13
-(B-Y) Out 49 -(R-Y) Out 50 SCP
Killer
O
1234567
VCC3 5 V
47 F
12 0.1 F 11 10 9
0.1 F
1 F
51
B
G
0.1 F 0.22 F
8
-(B-Y) In 52 -(R-Y) In
G R
VCC1 9 V
O 1 2 I
I
47 F G 100 F
AN78M09
SDB00022BEB
27
AN5693K
I Technical Information
* Package Allowable Loss PD T a
3 000 2 800 2 600 2 400 Without external Heat-sink Rthj = 54 C/W PD = 2 315 mW(25 C)
Power dissipation (mW)
2 200 2 000 1 800 1 600 1 400 1 200 1 000 800 600 400 200 0 0 25 50
75
100
125
150
Ambient temperature, Ta (C)
* Outline of major blocks * Video (1) Y delay line built-in : total delay time is approximately 690 ns. (2) Sharpness control is by using delay line aperture control. (contour emphasis type) Together with black level extention circuit, high quality picture is achieved. (3) Chroma trap is built-in : Trap frequency is synchronised with the chroma VCO frequency at 4.43 MHz/3.58 MHz automatically. By I2C bus, the trap can be forced to by-pass. In SECAM mode, about 4.43 MHz free run frequency is obtained. When in black & white(B/W)mode(killer"On"), the trap is automatically by-passed. (4) Pedestal clamp filter is built-in. (5) Service switch : (Y contrast min., Vertical output stop). Can be switched by I2C bus. (6) Chart showing the modes of the trap : System(fC) 4.43 MHz(PAL) Color or B/W Color B/W 3.58 MHz(NTSC) Color B/W SECAM Color B/W Forced manual mode by I2C bus Trap Status 4.43 MHz 4.43 MHz free-run 3.58 MHz 3.58 MHz free-run 4.43 MHz free-run 4.43 MHz free-run About 5.5 MHz No trap point
Forced through mode by I2C bus
* Chroma (1) Using base-band 1H delay line(external 1HDL IC required), adjustment free is achieved. (2) BPF(4.43 MHz/3.58 MHz), ACC filters are built-in, thus external components are reduced. (3) By changing the following mode using the I2C bus : 1. PAL/NTSC 2. 4.43 MHz/3.58 MHz 3. Forced PN/Forced SECAM and together with the SECAM IC for automatic SECAM detection, multi-system application is possible. 28
SDB00022BEB
AN5693K
I Technical Information (continued)
* Outline of major blocks (continued) * Chroma (continued) (4) Killer output pin is available for system identification by MICOM. (Killer"On" 0 V : Either color signal is not properly detected due to wrong system settig, or the color signal field strength is too weak. Killer"Off" 5 V : Color signal is properly detected.) When killer is on, according to the MICOM control sequence,the mode and VCO frequency will be switched by means of the I2C bus. (5) During SECAM, the color difference output pins are put into high impedance. (6) AN5344(color-compensation IC)and other types of feature IC can be connected because color difference input pins are available. (7) It is possible for South American set application. (three-normal system : NTSC M,PAL M,PAL N).
7 8 47
VCC1 SW
Note) For PAL M, crystal MEIDEN 3575 & C = 18 pF are used. For PAL N, crystal MEIDEN 3012-M & C = 22 pF are used. In order to extend downwards the curve, a capacitor of 2 pF to 4 pF is added between Pin7 and GND.
(8) PAL/NTSC, SECAM interface(Pin 47) Input Signal 4.43 MHz 3.58 MHz SECAM *1 B/W
*2
DC about 1.3 V about 1.3 V about 4.6 V about 1.3 V
fC 4.43 MHz X 4.43MHz
AC Level 300 mVPP X 300 mVPP 300 mVPP
Note) *1 : 4.43 MHz AC component is output during vertical retrace period, is as shown below. V-sync.
Input
about DC 4.6 V
300 mVPP Pin47
V blank (RGB out)
Note) *2 : Eventhough the MICOM switches the VCO between 4.43MHz and 3.58MHz, only the 4.43 MHz CW will be outputed at periodic intervals as shown below.
about DC 1.3 V about 80 ms
SDB00022BEB
300 mVPP Pin47
29
AN5693K
I Technical Information (continued)
* Outline of major blocks (continued) * RGB (1) OSD is made up of 3 colors of RGB, by using simple analog input, of which input at 0 V is fixed at the pedestal level.(The input dynamic range is controllable by contrast) (2) White balance(drive, cutoff)adjustment is implemented by I2C bus. (3) Spot killer is built-in : When power supply is off, R, G, B, output levels increase, the residue spot that is visible on the CRT is eliminated. * Jungle (1) 2-pin are used for synchronous inputs(Horizontal, Vertical)to improve the synchronisation characteristics of horizontal and vertical synchronisation. (2) The horizontal circuit is based on countdown method using a 32 fH ceramic oscillator. AFC circuit is employing the doubler method. (3) The vertical circuit is employing the trigger method's countdown circuit, thereby resulting in no adjustment and stable vertical synchronisation. The pulse output will not be interfered by interlace which is caused by pattern layout. (4) Vertical frequency identification circuit is built-in : the output of 50/60 Hz identification is determined according to the vertical synchronous frequency.(60 Hz "H") Below 45 Hz and above 65 Hz, the previous state is hold. After 3 consecutive vertical period, if 60 or 50 Hz is identifield, the initial output will be changed.
Input frequency Hold Idetification output voltage 50Hz (Low) 60Hz (High) 45 55 65 Hold
(5) Horizontal lock detection circuit and X-ray protection circuit(Shut down method)are built-in. (6) Picture centre position is adjustable by I2C bus.(1.6 s) (7) In the case of blue back in a weak field, the vertical trigger can be in off mode(I2C bus). Thus a stable picture is maintained. * I2C Bus (1) There are 15 built-in DAC controls and 13 built-in switches to reduce adjustment for set maker. (2) Auto-increment function present : * Sub address 0*: Auto-increment mode (When the data is sent in consecutive order, the sub-address will be changed in consecutive order, as data is inputed) * Sub address 8*: Data refresh mode (When the data is sent consecutively, it is sent to the same sub-address) (3) I2C Bus Protocol * Slave address : 10001010(8AH) * Format(Usual) S Slave address 0 A Sub address A Data byte A P
Start condition
Write Acknowledge bit
Stop condition
* Auto-increment mode/Data refresh mode
S Slave address 0 A Sub address A Data 1 A Data 2 A Data n A P
(4) Because DAC initial condition is not guaranteed, during power on, it is necessary to input the required standard data. 30
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AN5693K
I Technical Information (continued)
* Outline of major blocks (continued) * I2C Bus Addressing
Sub Address 00 (40H) 01 (40H) 02 (80H) 03 (40H) 04 (A0H) 05 (80H) 06 (40H) 07 (80H) 08 (80H) 09 (80H) 0A (88H) 0B (01H) 0C (40H) 0D (40H) 0E (01H)
Data Byte D7 P/N (0P) PN/S (0PN) D6 D5 D4 D3 Color Tint Brightness SSW (0Off) Ext. DAC2 (1typ.) Contrast Sharpness Cutoff R Cutoff G Cutoff B Drive R Drive B Video adjust External DAC2 SECAM Enable (0 enable) External DAC1 External DAC3 Ver. trig Cut off Auto trap Cut off stop B R (0 auto) (0 typ.) (0 typ.) (0 normal) Ver. OSC (0 50) Chroma Chroma Ver. trap VCO Auto trap (0 auto) (0 normal) (1 4.43) H center D2 D1 D0
Note) Items in the brackets are initial conditions.
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AN5693K
I Technical Information (continued)
* Outline of major blocks (continued) * I2C Bus Control Contents 1. For the Control information, for all sub-address, when data goes up, output increases. (Example : Contrast 00 contrast min., 7F contrast max., Brightness 00 pedestal low, FF pedestal high) 2. Other control supplementary (1) 00 : Color When Color data is 00, chroma output is completely cutoff so that color is off. (2) 01 : Tint When tint data is 00, the skin color approaches red.When tint data is 7F, the skin color approaches green. (3) 05, 06, 07(8-bit)and 0ED4, 0ED5(1-bit) : cutoff R, G, B The cutoff controllable range has increased resolution with 1 extra bit and is segmented into 2 sub-section, each section is variable by 8-bit DAC. (Cutoff G is 1 section of 8-bit DAC, that has the same variable range as R, B) Example : Case of R cutoff Output G cutoff overlap by about1/8 R cutoff
0E-D4 : 0 05 : 00
1 FF00
FF
(4) 08, 09 : Drive R, B 8-bit DAC 1 section(no switching of sub-section). (5) 0A : Video Adjust Data 0* composite video min. F* composite video max. This control is used to adjust the composite video level. (6) 0A : Horizontal Centre Data *0 picture moves left. *F picture moves right. (7) 0B : External DAC2 and 04 D7 External DAC2 has 8-bits DAC of 2 sections adjustment. Data 01 DC voltage shifts down. Data FF DC voltage shifts up. (8) 0C : External DAC1 Data 00 DC voltage shifts down. Data 7F DC voltage shifts up. (9) 0D : External DAC3 Data 00 DC voltage shifts down. Data 7F DC voltage shifts up.
32
SDB00022BEB
AN5693K
I Technical Information (continued)
* Outline of major blocks (continued) * Switch Operation Data Bit 00-D7 SW Contents PAL/NTSC mode switch (0 PAL) (1 NTSC) * * * * * Detail Contents Choroma signal delay line correction(PAL : short) BGP width change(PAL : wide) CW switch to killer(PAL : 90/270 deg) Tint operation change(PAL : Tint off) Ident operation change(PAL : Operating)
01-D7
PAL, NTSC/SECAM mode switch (0 normal detection mode) (1 forced SECAM mode)
* Demodulator Output mode switch In forced SECAM, color difference pin(48, 49) become high impedence. * When in Service mode(1 H line white balance adjust) Vertical output pulse stop(DC about 4.3 V) Y output off, Chroma output present
03-D7
SSW(Service switch) (0 normal) (1 Service mode) Not used External DAC2 (0 no offset) (1 offset) SECAM enable switch (0 normal) (1 forced disable SECAM) Not used Chroma VCO switch (0 3.58 MHz) (1 4.43 MHz) Chroma trap switch (0 Trap present) (1 Through) Vertical auto switch (0 Auto switch) (1 Manual switch) Vertical oscillator switch (0 50 Hz) (1 60 Hz) Cutoff R (0 no offset) (1 offset) Cutoff B (0 no offset) (1 offset)
04-D6 04-D7
* For External DAC2 2 section adjustment
0C-D7
* SECAM error detection prevention switch 1 non-SECAM,SECAM detection input condition (Pin47)will not be received
0D-D7 0E-D0
* Chroma oscillator circuit switch (video circuit trap frequency also switch) * Video circuit's chroma trap switch (Y signal phase shift when through) * Vertical frequency detection circuit switch Auto switch : Auto detection mode by internal counter Manual switch : Depending on 0E-D3 data to force into 50 or 60 Hz mode. * Vertical frequency switch Only effective if 0E-D2 data is 1 * Used to switch the cutoff R between 2 section
0E-D1
0E-D2
0E-D3
0E-D4
0E-D5
* Used to switch the cutoff B between 2 section
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33
AN5693K
I Technical Information (continued)
* Outline of major blocks (continued) * Switch Operation (continued) Data Bit 0E-D6 SW Contents Trap auto switch (0 Auto switch) (1 frequency fixed) Vertical trigger stop switch (0 normal) (1 trigger off) Detail Contents * Auto switch : Moves with chroma oscillating frequency. Frequency fixed : fixed at about 5.7 MHz * Switch for prevention of vertical trigger input 1 trigger input off. In blue back etc., vertical dancing due to any noise is prevented.
0E-D7
I New Package Dimensions (Unit: mm)
* SDIP052-P-0600F (Lead-free package)
47.700.30 52 27
0.70 min. 3.300.30
3.850.30
1
26
13.700.20
(1.625)
1.778
0.500.10 1.000.10
15.24
Seating plane 3 to 15
0.25 -0.05
+0.10
34
SDB00022BEB
Request for your special attention and precautions in using the technical information and semiconductors described in this material
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuit examples of the products. It does not constitute the warranting of industrial property, the granting of relative rights, or the granting of any license. (3) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (4) The products and product specifications described in this material are subject to change without notice for reasons of modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, redundant design is recommended, so that such equipment may not violate relevant laws or regulations because of the function of our products. (6) When using products for which dry packing is required, observe the conditions (including shelf life and after-unpacking standby time) agreed upon when specification sheets are individually exchanged. (7) No part of this material may be reprinted or reproduced by any means without written permission from our company.
Please read the following notes before using the datasheets
A. These materials are intended as a reference to assist customers with the selection of Panasonic semiconductor products best suited to their applications. Due to modification or other reasons, any information contained in this material, such as available product types, technical data, and so on, is subject to change without notice. Customers are advised to contact our semiconductor sales office and obtain the latest information before starting precise technical research and/or purchasing activities. B. Panasonic is endeavoring to continually improve the quality and reliability of these materials but there is always the possibility that further rectifications will be required in the future. Therefore, Panasonic will not assume any liability for any damages arising from any errors etc. that may appear in this material. C. These materials are solely intended for a customer's individual use. Therefore, without the prior written approval of Panasonic, any other use such as reproducing, selling, or distributing this material to a third party, via the Internet or in any other way, is prohibited.
2001 MAR

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