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Microcontrollers ApNote AP0820
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8-Bit C500 Family The CAN Controller in the C515C
The Controller Area Network (CAN) module which has been implemented in the Siemens C515C microcontroller allows communication between several stations (CAN nodes). This document describes the CAN functionality, the initialisation and the use of the CAN module. Furthermore, examples concerning interrupt generation and error handling will be given. Author : Dr. Jens Barrenscheen / HL MC PD Microcontroller Product Definition
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8-Bit C500 Family The CAN Controller in the C515C
Contents 1 2 3 4 5 6 7 A B C
Page
Principle of this CAN application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 CAN Initialisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Definition of a Message Object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Sending a Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Busoff State and CAN Re-Initialisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CANREG.H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INTC515C.H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REGC515C.H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 17 17
AP0820 ApNote - Revision History Actual Revision : 12.96 Page of Page of actual Rev. prev.Rel. Previous Revision : none (Original Version) Subjects (changes since last release)
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1
Principle of this CAN application
The on-chip CAN-controller provides all features of FULL-CAN controllers, such as message management and acceptance filtering (by input masks) in order to minimise CPU load. The BASICCAN functionality with only one message object (nr. 15) is available, too. This device supports the standard CAN protocol (specification 2.0 A, 11 bit identifier), as well as the extended CAN protocol (specification 2.0 B active, 29 bit identifier). All CAN nodes are connected in parallel to the two-wire CAN-bus (CAN_H and CAN_L). The C515C is connected to an external CAN-bus transceiver by the signal TxDC and RxDC, the principle is shown in figure 1.
C515C with on-chip CAN controller
P4.6 TxDC P4.7 RxDC
CAN node A
CAN transceiver
CAN_H CAN_L
CAN node B
CAN node n
Figure 1 : Connection of the Siemens C515C microcontroller to the CAN bus Fifteen different message objects can be used independently by the Siemens C515C microcontroller. Each one has its own specific identifier; two message objects with identical identifiers are not allowed ! Two different types of objects can be defined, transmit objects and receive objects. Transmit objects contain data with the data length programmable from 1 to 8 bytes. They are transmitted as soon as the CAN bus is idle after setting of the corresponding transmit request flag. Receive objects are used to store data of incoming transmit objects with matching identifier. A transmission request concerning receive objects causes the transmission of a remote frame in order to request data transfer from another CAN node with identical identifier.
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CAN Initialisation
The initialisation of the CAN module can be made as follows: All CAN registers are located in the onchip XRAM memory, from address F700H up to F7FFH. An access to this special memory space requires the modification of register XPAGE to the value of F7H. Furthermore, bits XMAP0 and XMAP1 in register SYSCON must be forced to "0". The initialisation of the CAN controller begins with setting the bits CCE and INIT in the Control Register CR (F700H) to "1". This instruction (CCE=1) enables the modification of the CAN Bit Timing Registers BTR0, located at F704H, and BTR1 at F705H in order to program the desired bit timing and baudrate. Bit CCE should be reset to "0" after the access to these registers to avoid erroneous modification of the internal timing. The following values have been tested: Table 1 : Programming of the CAN Bit Timing Registers Baudrate BTR0 BTR1 125 kBaud C4H 49H 250 kBaud C1H 6BH 500 kBaud C0H 6BH 1 MBaud 80H 25H
This description only focuses on the application of complete message identifiers where no masking is done. Therefore, the Global Mask Registers GMS0, GMS1, UGML0, UGML1, LGML0 and LGML1 (F709H .. F70BH) contain the value of FFH. The CAN controller provides three different types of interrupt sources: - status interrupts - error interrupts - message specific interrupts The first type is generated by a status change of the CAN module, which is indicated in the CAN Status Register SR (F701H). This can be a successful transmission (TXOK is set) or reception (RXOK is set) of any message object, or the occurrence of an error (see LEC bitfield). These interrupt sources can be enabled by setting bit SIE in the CAN Control Register CR, which is located at address F700H. The second type are error interrupts, which can be enabled by the bit EIE. They are generated after the change of the flags EWRN or BOFF in the CAN Status Register. Interrupts of the third type are generated by each message object after successful transmission or reception. This function can be enabled by setting to 1" bits TXIE and/or RXIE in the lowbyte of the corresponding CAN Message Control Register MCR0_n (F7n0h), with n being the number of the corresponding message object (1..15). Bit IE in the CAN Control Register globally enables (IE=1) or disables all interrupt sources of the CAN module. The internal structure of the C515C requires setting bits ECAN (register IEN2) and EAL (register IEN0) to 1" in order to service an interrupt request. Before the end of the CAN initialisation sequence where bit INIT is reset to 0", all message objects must be completely initialised or declared as not valid (MSGVAL="0" in the corresponding CAN Message Control Register) in order to avoid erroneous data transfers.
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This structure leads to the following CAN initialisation procedure :
unsigned char IE = 1; // all CAN interrupts enabled unsigned char SIE = 0; // status interrupts disabled unsigned char EIE = 0; // error interrupts disabled //.............................................................. void can_init (void) {SYSCON &= 0xFC; // XMAP0=0, XMAP1=0 XPAGE = 0xF7; // CAN memory space in XRAM GMS0 UGML0 LGML0 UMLM0 LMLM0 CR = BTR0 CR = SR = = = = = = 0xFF; 0xFF; 0xFF; 0xFF; 0xFF; GMS1 UGML1 LGML1 UMLM1 LMLM1 = = = = = 0xFF; 0xFF; 0xFF; 0xFF; 0xFF; // global mask short // global mask long // last message mask // // // // INIT=1 and CCE=1 (enable access baudrate) access bit timing registers: 10 MHz,250 kBaud CCE=0 (disable access baudrate) clear TXOK and RXOK
0x41; = 0xC1; 0x01; 0xE7;
BTR1 = 0x6B;
MCR0_1 = 0x55; ... MCR0_15 = 0x55; IEN2 = 2; CR = 0; if ( IE) CR |= 0x02; if (SIE) CR |= 0x04; if (EIE) CR |= 0x08; }
// message 1 not valid // ... // message 15 not valid // // // // // enable INIT=0 enable enable enable CAN interrupt (ECAN=1) global can_int can_status_int can_error_int
3
Definition of a Message Object
The complete definition of a message object includes the determination of its identifier in the corresponding CAN Arbitration Registers UAR0_n, UAR1_n, LAR0_n and LAR1_n (F7n2H..F7n5H). In the case of transmit objects, the desired data bytes have to be written to the addresses from F7n7H (DB0_n) up to F7nEH (DB7_n) in the message object. The interrupt enable bits TXIE and RXIE are application specific and can be set in the corresponding CAN Message Control Register. They enable the interrupt generation on a successful message transfer. Furthermore, the remaining flags INTPND and RMTPND are set to 0" to get defined starting conditions. In order to avoid a CAN action on a message object which is currently accessed by the CPU, bit CPUUPD has to be set to "1" before the CPU works on the data of this message object. The CAN Message Configuration Register MCFG_n is located at address F7n6. It is used to define the character of the message object, such as the direction of the data transfer by bit DIR, or the data length by bit field DLC. Receive objects (DIR is set to "0") contain no direct data, so their data length is 0. The data length of transmit objects (DIR is set to "1") can be defined from 1 to 8 bytes. Furthermore, bit XTD determines whether an extended identifier of 29 bits (XTD="1"), or a standard identifier of 11 bits (XTD="0") is used (see table 2). After the last CPU access, the bit CPUUPD has to be cleared, as well as the bit NEWDAT. This bit is set after a CAN action on these data. Then the message object can be declared valid by setting to "1" bit MSGVAL, because the CAN module only works on valid message objects.
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Table 2 : Programming of the Message Configuration Register Object 1 2 7 11 Direction transmit receive transmit receive Data length 1 0 8 0 Protocol standard standard extended extended Address F716H F726H F776H F7B6H Value 18H 00H 8CH 04H
Table 3 : Impact of bit DIR Transmission of this message object generates ... Bit DIR ="0" Receive Object (receives data frames, transmits remote frames) ... a remote frame. The corresponding data frame is stored in this MO on reception. If a data frame with If a remote frame with matching identifier is matching identifier is received ... received ... ... the data frame is stored. ... the remote frame is NOT answered.
Bit DIR ="1" ... a data frame. Transmit Object (transmits data frames, receives remote frames)
... the data frame is NOT stored.
... the remote frame is answered by the corresponding data frame
A message object initialisation procedure (objects 1 and 2, as given in the example) can be programmed as follows:
//.............................................................. // definition message 1, standard transmission frame void def_1 (void) {MCR1_1 = 0xFB; // CPUUPD=1 UAR0_1 = 0x11; UAR1_1 = 0x20;// identifier 00010001 001 MCFG_1 = 0x18; // frame definition DB0_1 = 0x5A; // data byte 0 : 5Ah MCR0_1 = 0xA5; // MSGVAL=1, TXIE=1, RXIE=0, INTPND=0 MCR1_1 = 0x55; // RMTPND=0, TXRQ=0, CPUUPD=0, NEWDAT=0 } //.............................................................. // definition message 2, standard remote frame void def_2 (void) {MCR1_2 = 0xFB; // CPUUPD=1 UAR0_2 = 0x22; UAR1_2 = 0x20;// identifier 00100010 001 MCFG_2 = 0x00; // frame definition MCR0_2 = 0xA9; // MSGVAL=1, TXIE=1, RXIE=1, INTPND=0 MCR1_2 = 0x55; // RMTPND=0, TXRQ=0, CPUUPD=0, NEWDAT=0 }
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Interrupt Handling
As many different interrupt sources can generate only one global CAN interrupt request, their internal structure must be taken into account in the interrupt service procedure. The INTID code in the CAN Interrupt Register IR (F702H) indicates which source has activated the request. The status interrupt (if enabled by SIE) and the error interrupt (if enabled by EIE) cause the interrupt with the highest priority, which is indicated by the INTID value of "1". In the case of a status change due to a successful message transfer, one of the flags TXOK or RXOK in the CAN Status Register is set to "1". An erroneous message transfer is indicated by the LEC bit field. In the case of an error interrupt, at least one of the error flags EWRN and BOFF has changed. The CAN Status Register must be read in the interrupt service procedure in order to identify the interrupt source and to reset the pending interrupt request! The flags in this register must then all be cleared by software. An INTID code of "2..16" indicates a message specific transmit (if TXIE="1") or receive (if RXIE="1") interrupt. A successful message transfer sets the corresponding bit INTPND to "1", which must be cleared by software to reset this interrupt request. The priority of the internal CAN interrupt sources decreases with an increasing INTID code. This structure must also be taken into account for the identification of the interrupt source. For example, a successful transmission of only one message object can cause two independent interrupt requests if bit SIE and the corresponding bit TXIE have been set to "1". While the status interrupt (highest priority) is serviced and bit INTPND of this message object is not cleared, the message interrupt stays still pending. This will generate a second interrupt request (message specific) due to the same action. Only an INTID code of "0" indicates that all requested interrupts have been correctly serviced. A standard CAN interrupt procedure can be programmed as follows:
//.............................................................. // CAN interrupt void int_can (void) interrupt CANI {unsigned char status, intreg; while (intreg = IR) {status = SR; SR = 0; // read and reset CAN status switch (intreg) {case 1: // status and error interrupt if (SIE) // status interrupts {if (status & 0x08) {...}// transmit interrupt if (status & 0x10) {...}// receive interrupt if (status & 0x07) {...}// erroneous transfer } if (EIE) // error interrupts {if (status & 0x40) {...}// EWRN has changed if (status & 0x80) {...}// BUSOFF has changed } break; case 3: // message 1 interrupt MCR0_1 = 0xFD; // reset INTPND if (status & 0x08) {...} // transmit interrupt if (status & 0x10) {...} // receive interrupt break; case 4: // message 2 interrupt MCR0_2 = 0xFD; // reset INTPND if (status & 0x08) {...}// transmit interrupt if (status & 0x10) {...}// receive interrupt break; }}}
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Sending a Message
A valid message object can be sent by the CAN controller by setting bit TXRQ in the corresponding CAN Message Control Register. This can be done in the following way:
//.............................................................. void send_1 (void) // transmit message object 1 { MCR1_1 = 0xEF; } void send_2 (void) { MCR1_2 = 0xEF; } // transmit message object 2
At the end of each transferred message (transmit or remote frame), the receiving CAN nodes on the bus answer with a dominant ("0") acknowledge signal (Ack) to indicate successful message transfer. After the transmission of a remote frame from node A, node B (transmission object with matching identifier) answers by sending the requested data frame. These actions can generate status interrupts concerning flags TXOK and RXOK, as shown in figure 2 for node A.
Figure 2 : Successful transmission of a remote frame (50s/div)
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If several TXRQ bits are activated at the same time, the CAN controller starts sending the object with the highest priority (lowest number). A transmission request is only serviced if the corresponding message object is valid (MSGVAL="1") and not currently accessed by the CPU (CPUUPD="0"). In the case of bit TXRQ being set to 1" while the bit CPUUPD is still 1", the transmission request is taken into account after bit CPUUPD has been cleared and therefore need not to be repeated by the CPU. 6 Error Handling
After the detection of a transfer error, the sending CAN node immediately (one bit time) stops the transmission of the current message object and sends an error frame consisting of 6 dominant bits. They are detected by all other nodes, which then answer by the emission of another 6 dominant bits. After this sequence, the bus remains at logic "1" level for 11 bits, before the CAN controller automatically restarts the transmission of the disturbed message object. An example of a short disturbance with only one erroneous bit is shown in fig. 3. In this case, the error counter of the sending CAN node is incremented by 8. It is decremented by 1 after each successful message transfer. An interrupt can be generated by each transfer error if bit SIE has been set to "1". The code in the LEC bitfield contains information about the error type. In the given example (see figure 3), a status interrupt is generated due to a Bit1Error. The status interrupt which is shown in figure 3 is generated after the successful message transfer and the TxOK bit has been tested.
Figure 3 : Status interrupt generation due to a Bit1Error (50s/div)
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Busoff State and CAN Re-Initialisation
Each transfer error causes the incrementation of one of the two error counters (transmit error counter and receive error counter). In the case of longer disturbances, they are also incremented each time a sequence of 8 erroneous bits occurs. When one of the counter reaches the value of 96, the bit EWRN is set to "1". If more errors occur and one error counter reaches 255, the CAN controller stops all actions on the bus and goes into the busoff state. This is indicated by the BOFF flag changing to "1", which is shown figure 4.
EWRN
BOFF status interrupts
Figure 4 : EWRN, BOFF and CAN Re-Initialisation (5ms/div)
An error interrupt is generated if the bit EIE is set and either EWRN or BOFF change the status. The re-initialisation of the CAN module to ensure its normal functionality can be achieved by clearing bit INIT, which is set automatically when entering busoff state. During busoff recovery the LEC bitfield contains the code representing a Bit0Error each time a sequence of 11 recessive bits has been monitored. As this code can generate a status interrupt, the SIE bit should be cleared in the busoff state in order to avoid higher CPU load. The end of the busoff state can be detected by using error interrupts (EIE="1") and the bit SIE can then be set to the desired interrupt mode.
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Figure 5 : Message transfer just before busoff state (200s/div)
If the CAN controller stops all actions on the bus and goes busoff, the disturbed message can not be repeated immediately, see fig. 5. After successful busoff recovery (started by resetting bit INIT), it is automatically repeated without involving the CPU if the corresponding bit TxRQ remains set, see figure 6. This functionality avoids the loss of messages due to temporary transfer errors. If the automatic repetition of the last erroneous message after busoff recovery is not desired, it can be disabled by resetting the corresponding bit TxRQ by software.
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Figure 6 : Automatic message repetition after busoff state (200s/div)
The Siemens C515C microcontroller with on-chip CAN module provides all features of a FULL-CAN controller. This includes the use of up to 15 independent message objects with standard or extended identifiers, which can be transferred with a maximal baudrate of 1 MBaud. Thanks to the multitude of different CAN interrupt sources, all information which are necessary for normal data transfer and error handling are directly available. For these reasons, the C515C can easily be used for data transfer and treatment in CAN bus systems.
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Appendix A CANREG.H
extern unsigned char pdata canreg[256]; /****************************/ /* CAN Register Declaration */ /* CAN Control Registers */ #define CR #define SR #define IR #define BTR0 #define BTR1 #define GMS0 #define GMS1 #define UGML0 #define UGML1 #define LGML0 #define LGML1 #define UMLM0 #define UMLM1 #define LMLM0 #define LMLM1 canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ 0] 1] 2] 4] 5] 6] 7] 8] 9] 10] 11] 12] 13] 14] 15] 16] 17] 18] 19] 20] 21] 22] 23] 24] 25] 26] 27] 28] 29] 30] 32] 33] 34] 35] 36] 37] 38] 39] 40] 41] 42] 43] 44] 45] 46] 48] 49] 50] 51] 52] 53]
/* CAN Message 1 Registers */ #define MCR0_M1 canreg[ #define MCR1_M1 canreg[ #define UAR0_M1 canreg[ #define UAR1_M1 canreg[ #define LAR0_M1 canreg[ #define LAR1_M1 canreg[ #define MCFG_M1 canreg[ #define DB0_M1 canreg[ #define DB1_M1 canreg[ #define DB2_M1 canreg[ #define DB3_M1 canreg[ #define DB4_M1 canreg[ #define DB5_M1 canreg[ #define DB6_M1 canreg[ #define DB7_M1 canreg[ /* CAN Message 2 Registers */ #define MCR0_M2 canreg[ #define MCR1_M2 canreg[ #define UAR0_M2 canreg[ #define UAR1_M2 canreg[ #define LAR0_M2 canreg[ #define LAR1_M2 canreg[ #define MCFG_M2 canreg[ #define DB0_M2 canreg[ #define DB1_M2 canreg[ #define DB2_M2 canreg[ #define DB3_M2 canreg[ #define DB4_M2 canreg[ #define DB5_M2 canreg[ #define DB6_M2 canreg[ #define DB7_M2 canreg[ /* CAN Message 3 Registers */ #define MCR0_M3 canreg[ #define MCR1_M3 canreg[ #define UAR0_M3 canreg[ #define UAR1_M3 canreg[ #define LAR0_M3 canreg[ #define LAR1_M3 canreg[
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#define #define #define #define #define #define #define #define #define
MCFG_M3 DB0_M3 DB1_M3 DB2_M3 DB3_M3 DB4_M3 DB5_M3 DB6_M3 DB7_M3
canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[ canreg[
54] 55] 56] 57] 58] 59] 60] 61] 62] 64] 65] 66] 67] 68] 69] 70] 71] 72] 73] 74] 75] 76] 77] 78] 80] 81] 82] 83] 84] 85] 86] 87] 88] 89] 90] 91] 92] 93] 94]
/* CAN Message 4 Registers */ #define MCR0_M4 canreg[ #define MCR1_M4 canreg[ #define UAR0_M4 canreg[ #define UAR1_M4 canreg[ #define LAR0_M4 canreg[ #define LAR1_M4 canreg[ #define MCFG_M4 canreg[ #define DB0_M4 canreg[ #define DB1_M4 canreg[ #define DB2_M4 canreg[ #define DB3_M4 canreg[ #define DB4_M4 canreg[ #define DB5_M4 canreg[ #define DB6_M4 canreg[ #define DB7_M4 canreg[ /* CAN Message 5 Registers */ #define MCR0_M5 canreg[ #define MCR1_M5 canreg[ #define UAR0_M5 canreg[ #define UAR1_M5 canreg[ #define LAR0_M5 canreg[ #define LAR1_M5 canreg[ #define MCFG_M5 canreg[ #define DB0_M5 canreg[ #define DB1_M5 canreg[ #define DB2_M5 canreg[ #define DB3_M5 canreg[ #define DB4_M5 canreg[ #define DB5_M5 canreg[ #define DB6_M5 canreg[ #define DB7_M5 canreg[
/* CAN Message 6 Registers */ #define MCR0_M6 canreg[ 96] #define MCR1_M6 canreg[ 97] #define UAR0_M6 canreg[ 98] #define UAR1_M6 canreg[ 99] #define LAR0_M6 canreg[100] #define LAR1_M6 canreg[101] #define MCFG_M6 canreg[102] #define DB0_M6 canreg[103] #define DB1_M6 canreg[104] #define DB2_M6 canreg[105] #define DB3_M6 canreg[106] #define DB4_M6 canreg[107] #define DB5_M6 canreg[108] #define DB6_M6 canreg[109] #define DB7_M6 canreg[110] /* CAN Message 7 Registers */ #define MCR0_M7 canreg[112] #define MCR1_M7 canreg[113] #define UAR0_M7 canreg[114] #define UAR1_M7 canreg[115] #define LAR0_M7 canreg[116]
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#define #define #define #define #define #define #define #define #define #define
LAR1_M7 MCFG_M7 DB0_M7 DB1_M7 DB2_M7 DB3_M7 DB4_M7 DB5_M7 DB6_M7 DB7_M7
canreg[117] canreg[118] canreg[119] canreg[120] canreg[121] canreg[122] canreg[123] canreg[124] canreg[125] canreg[126]
/* CAN Message 8 Registers */ #define MCR0_M8 canreg[128] #define MCR1_M8 canreg[129] #define UAR0_M8 canreg[130] #define UAR1_M8 canreg[131] #define LAR0_M8 canreg[132] #define LAR1_M8 canreg[133] #define MCFG_M8 canreg[134] #define DB0_M8 canreg[135] #define DB1_M8 canreg[136] #define DB2_M8 canreg[137] #define DB3_M8 canreg[138] #define DB4_M8 canreg[139] #define DB5_M8 canreg[130] #define DB6_M8 canreg[131] #define DB7_M8 canreg[132] /* CAN Message 9 Registers */ #define MCR0_M9 canreg[144] #define MCR1_M9 canreg[145] #define UAR0_M9 canreg[146] #define UAR1_M9 canreg[147] #define LAR0_M9 canreg[148] #define LAR1_M9 canreg[149] #define MCFG_M9 canreg[150] #define DB0_M9 canreg[151] #define DB1_M9 canreg[152] #define DB2_M9 canreg[153] #define DB3_M9 canreg[154] #define DB4_M9 canreg[155] #define DB5_M9 canreg[156] #define DB6_M9 canreg[157] #define DB7_M9 canreg[158] /* CAN Message 10 Registers */ #define MCR0_M10 canreg[160] #define MCR1_M10 canreg[161] #define UAR0_M10 canreg[162] #define UAR1_M10 canreg[163] #define LAR0_M10 canreg[164] #define LAR1_M10 canreg[165] #define MCFG_M10 canreg[166] #define DB0_M10 canreg[167] #define DB1_M10 canreg[168] #define DB2_M10 canreg[169] #define DB3_M10 canreg[170] #define DB4_M10 canreg[171] #define DB5_M10 canreg[172] #define DB6_M10 canreg[173] #define DB7_M10 canreg[174] /* CAN Message 11 Registers */ #define MCR0_M11 canreg[176] #define MCR1_M11 canreg[177] #define UAR0_M11 canreg[178] #define UAR1_M11 canreg[179]
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#define #define #define #define #define #define #define #define #define #define #define
LAR0_M11 LAR1_M11 MCFG_M11 DB0_M11 DB1_M11 DB2_M11 DB3_M11 DB4_M11 DB5_M11 DB6_M11 DB7_M11
canreg[180] canreg[181] canreg[182] canreg[183] canreg[184] canreg[185] canreg[186] canreg[187] canreg[188] canreg[189] canreg[190]
/* CAN Message 12 Registers */ #define MCR0_M12 canreg[192] #define MCR1_M12 canreg[193] #define UAR0_M12 canreg[194] #define UAR1_M12 canreg[195] #define LAR0_M12 canreg[196] #define LAR1_M12 canreg[197] #define MCFG_M12 canreg[198] #define DB0_M12 canreg[199] #define DB1_M12 canreg[200] #define DB2_M12 canreg[201] #define DB3_M12 canreg[202] #define DB4_M12 canreg[203] #define DB5_M12 canreg[204] #define DB6_M12 canreg[205] #define DB7_M12 canreg[206] /* CAN Message 13 Registers */ #define MCR0_M13 canreg[208] #define MCR1_M13 canreg[209] #define UAR0_M13 canreg[210] #define UAR1_M13 canreg[211] #define LAR0_M13 canreg[212] #define LAR1_M13 canreg[213] #define MCFG_M13 canreg[214] #define DB0_M13 canreg[215] #define DB1_M13 canreg[216] #define DB2_M13 canreg[217] #define DB3_M13 canreg[218] #define DB4_M13 canreg[219] #define DB5_M13 canreg[220] #define DB6_M13 canreg[221] #define DB7_M13 canreg[222] /* CAN Message 14 Registers */ #define MCR0_M14 canreg[224] #define MCR1_M14 canreg[225] #define UAR0_M14 canreg[226] #define UAR1_M14 canreg[227] #define LAR0_M14 canreg[228] #define LAR1_M14 canreg[229] #define MCFG_M14 canreg[230] #define DB0_M14 canreg[231] #define DB1_M14 canreg[232] #define DB2_M14 canreg[233] #define DB3_M14 canreg[234] #define DB4_M14 canreg[235] #define DB5_M14 canreg[236] #define DB6_M14 canreg[237] #define DB7_M14 canreg[238] /* CAN Message 15 Registers */ #define MCR0_M15 canreg[240] #define MCR1_M15 canreg[241] #define UAR0_M15 canreg[242]
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8-Bit C500 Family The CAN Controller in the C515C
#define #define #define #define #define #define #define #define #define #define #define #define
UAR1_M15 LAR0_M15 LAR1_M15 MCFG_M15 DB0_M15 DB1_M15 DB2_M15 DB3_M15 DB4_M15 DB5_M15 DB6_M15 DB7_M15
canreg[243] canreg[244] canreg[245] canreg[246] canreg[247] canreg[248] canreg[249] canreg[250] canreg[251] canreg[252] canreg[253] canreg[254]
B
INTC515C.H
/**********************************************************************/ /* */ /* INTC515C.H" */ /* */ /* symbolic interruptnumbers for C151C-interrupt routines */ /* */ /**********************************************************************/ #define EXTI0 0 // (03H) external interrupt 0 #define TIMER0 1 // (0BH) Timer 0 Overflow #define EXTI1 2 // (13H) external interrupt 1 #define TIMER1 3 // (1BH) Timer 1 Overflow #define SINT 4 // (23H) serial interrupt #define TIMER2 5 // (2BH) Timer 2 Overflow #define ADCI 8 // (43H) A/D-Converter interrupt #define EXTI2 9 // (4BH) external interrupt 2 #define EXTI3 10 // (53H) external interrupt 3 #define EXTI4 11 // (5BH) external interrupt 4 #define EXTI5 12 // (63H) external interrupt 5 #define EXTI6 13 // (6BH) external interrupt 6 #define PWD 15 // (7BH) Power Down interrupt #define CANI 17 // (8BH) CAN interrupt #define SSCI 18 // (93H) SSC interrupt #define EXTI7 20 // (A3H) external interrupt 7 #define EXTI8 21 // (ABH) external interrupt 8
C
REGC515C.H
/* (c) Copyright SIEMENS 1996 , All rights reserved. */ /* Register Declarations for the C515C Processor */ /**********************/ /* BYTE Register */ sfr P0 = 0x80; sfr SP = 0x81; sfr DPL = 0x82; sfr DPH = 0x83; sfr WDTREL = 0x86; sfr PCON = 0x87; sfr TCON = 0x88; sfr TMOD = 0x89; sfr TL0 = 0x8A; sfr TL1 = 0x8B; sfr TH0 = 0x8C; sfr TH1 = 0x8D; sfr sfr sfr sfr sfr P1 XPAGE DPSEL SSCCON STB = = = = = 0x90; 0x91; 0x92; 0x93; 0x94;
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8-Bit C500 Family The CAN Controller in the C515C
sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr sfr
SRB SSCMOD SCON SBUF IEN2 P2 IEN0 IP0 SRELL SCF SCIEN P3 SYSCON IEN1 IP1 SRELH IRCON CCEN CCL1 CCH1 CCL2 CCH2 CCL3 CCH3 T2CON CRCL CRCH TL2 TH2 PSW ADCON0 ADDATH ADDATL P6 ADCON1 P7 CCPL CCPH ACC P4 B P5 DIR5
= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
0x95; 0x96; 0x98; 0x99; 0x9A; 0xA0; 0xA8; 0xA9; 0xAA; 0xAB; 0xAC; 0xB0; 0xB1; 0xB8; 0xB9; 0xBA; 0xC0; 0xC1; 0xC2; 0xC3; 0xC4; 0xC5; 0xC6; 0xC7; 0xC8; 0xCA; 0xCB; 0xCC; 0xCD; 0xD0; 0xD8; 0xD9; 0xDA; 0xDB; 0xDC; 0xDD; 0xDE; 0xDF;
= 0xE0; = 0xE8; = 0xF0; = 0xF8; = 0xF8;
/*********************/ /* BIT Register */ /* TCON */ sbit TF1 sbit TR1 sbit TF0 sbit TR0 sbit IE1 sbit IT1 sbit IE0 sbit IT0 /* SCON */ sbit SM0 sbit SM1 sbit SM2 sbit REN = = = = = = = = = = = = 0x8F; 0x8E; 0x8D; 0x8C; 0x8B; 0x8A; 0x89; 0x88; 0x9F; 0x9E; 0x9D; 0x9C;
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8-Bit C500 Family The CAN Controller in the C515C
sbit TB8 sbit RB8 sbit TI sbit RI /* IEN0 */ sbit EAL sbit WDT sbit ET2 sbit ES sbit ET1 sbit EX1 sbit ET0 sbit EX0 /* IEN1 */ sbit EXEN2 sbit SWDT sbit EX6M sbit EX5 sbit EX4 sbit EX3 sbit EX2 sbit EADC /* P3 */ sbit RD sbit WR sbit T1 sbit T0 sbit INT1 sbit INT0 sbit TXD sbit RXD /* T2CON */ sbit T2PS sbit I3FR sbit I2FR sbit T2R1 sbit T2R0 sbit T2CM sbit T2L1 sbit T2I0 /* IRCON */ sbit EXF2 sbit TF2 sbit IEX6 sbit IEX5 sbit IEX4 sbit IEX3 sbit IEX2 sbit IADC /* ADCON0 */ sbit BD sbit CLK sbit ADEX sbit BSY sbit ADM sbit MX2 sbit MX1 sbit MX0 /* PSW */ sbit CY sbit AC sbit F0 sbit RS1 sbit RS0 sbit OV sbit F1 sbit P
= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
0x9B; 0x9A; 0x99; 0x98; 0xAF; 0xAE; 0xAD; 0xAC; 0xAB; 0xAA; 0xA9; 0xA8; 0xBF; 0xBE; 0xBD; 0xBC; 0xBB; 0xBA; 0xB9; 0xB8; 0xB7; 0xB6; 0xB5; 0xB4; 0xB3; 0xB2; 0xB1; 0xB0; 0xCF; 0xCE; 0xCD; 0xCC; 0xCB; 0xCA; 0xC9; 0xC8; 0xC7; 0xC6; 0xC5; 0xC4; 0xC3; 0xC2; 0xC1; 0xC0; 0xDF; 0xDE; 0xDD; 0xDC; 0xDB; 0xDA; 0xD9; 0xD8; 0xD7; 0xD6; 0xD5; 0xD4; 0xD3; 0xD2; 0xD1; 0xD0;
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AP0820 12.96

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