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October 2004
AS91L1001
JTAG Test Controller
Description
The AS91L1001 device provides an interface between the 60x bus on the Motorola MPC8260 processor and two totally independent IEEE1149.1 interfaces, namely, the primary and secondary ports. It handles all the protocol for the 60x bus to write and read directly to registers within the device with no additional glue logic. The AS91L1001 has three distinct modes of rd operation, namely Slave mode, Master mode, and 3 Party Support mode. These different modes control how data will be transferred on the IEEE1149.1 buses. Slave mode: This is the default mode after the AS91L1001 has received a power-on reset. In this mode, there is a transparent connection between the primary and secondary JTAG ports. The processor interface is not used in the slave mode. This configuration is typically used to test a line card from a system back plane (the primary port is usually connected to the back plane and the secondary port is connected to the onboard JTAG chain). Once testing from the system back plane is completed, the AS91L1001 is reconfigured for master mode operation through a register. The master mode of operation is used to test the onboard JTAG chain, using the microprocessor interface. Master mode: This mode is accessed via a command to a AS91L1001 register. The key feature of this mode is that both the Primary and Secondary are now both totally independent IEEE1149.1 bus masters, which enable concurrent operation on both the IEEE1149.1 channels. The Master mode enables the primary IEEE1149.1 channel to be used to access other PCB's connected via the 5-wire IEEE1149.1 interface on the back plane. The secondary IEEE1149.1 port is used to test the card that is hosting the AS91L1001. This mode may be used for performing Interconnect testing or Flash/CPLD programming.
Key Features
Interprets between the Motorola MPC8260 processor and two IEEE1149.1 ports Three distinct modes of operation: Slave mode, Master mode, and 3rd Party support mode Supports a wide range of 3rd Party tools Pinout and feature set compatible (complete second source) with the Firecron JTS01 device Available in a 100-pin LQFP or a 100-pin FPBGA lead free package
Device Block Diagram
Figure 1 - AS91L1001 JTAG Test Controller
Alliance Semiconductor
2575 Augustine Drive * Santa Clara, CA 95054 * P: 408-855-4900 * F: 408-855-4999 * www.alsc.com
October 2004
AS91L1001
Description (Cont.)
MPC8260
IEEE 1149.1 secondary port
AS91L1003
AS91L1001
on board JTAG chain
Back Plane TRST Back Plane TDI Back Plane TDO Back Plane TMS Back Plane TCK Back Plane Auto-Wr
IEEE 1149.1 primary port
Alliance Semiconductor supplies a Windows executable that converts industry standard SVF into Alliance Semiconductor proprietary BVF file format. Users of the ANSI C Code are only required to provide the base read and write function for the stream I/O. So in order to execute a BVF file, the user has to call the primary C function, which will then perform all the required setup of the AS91L1001 along with obtaining the BVF file to process at the required time or report any errors if applicable. If the user wishes to embed the ANSI C routines from FPGA/CPLD vendors, then this is handled in a very similar manner. As one of the IEEE1149.1 ports will be operating in Alliance Semiconductor BVF mode, the method of reading and writing data is the same as before. However, the user will need to consult the 3rd party routines to see how the data flow is performed. Ultimately, the user will call a Alliance Semiconductor provided C routine that will set the AS91L1001 for 3rd party support on one of the IEEE1149.1 channels while the other will be used for executing the 3rd party code. In summary, 3rd Party Support mode enables serial shifting of data on any of the two JTAG ports and is used to configure legacy FPGA/CPLD devices.
Figure 2 - Slave mode
BVF Data 3rd Party Data
MPC8260 AS91L1003
AS91L1001
Secondary IEEE1149.1 Port Primary IEEE1149.1 Port
Back Plane TRST Back Plane TDI Back Plane TDO Back Plane TMS Back Plane TCK Back Plane Auto-Wr
Figure 3 - Master mode 3rd Party Support mode: This mode is intended to support legacy FPGA/CPLD 1149.1 devices that require adaptive programming algorithms to ensure data retention, due to the fact that decision branching is not supported in Service Vector Format (SVF). This mode will not be required for devices that adhere to the IEEE1532 specification, as IEEE1532 compliant parts from all CPLD/FPGA vendors adhere to this open standard. The 3rd Party support mode which is accessible via control registers in the AS91L1001 selects one of the IEEE1149.1 ports to operate with the standard SVF->BVF flow while the remaining IEEE1149.1 port will support commands for the embedded C Code routines provided by FPGA/CPLD vendors. This eliminates any issues regarding data retention when using the AS91L1001 on a PCB.
BVF Data 3rd Party Data
MPC8260 AS91L1003
AS91L1001
Secondary IEEE1149.1 Port Primary IEEE1149.1 Port
Back Plane TRST Back Plane TDI Back Plane TDO Back Plane TMS Back Plane TCK Back Plane Auto-Wr
Figure 4 - 3rd Party support mode
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2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved.
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October 2004
AS91L1001
Signal Description
PIN NAME RESETn JTS03_06_SELECTEDn PIN TYPE IN IN PIN NUMBER LQFP 14 65 PIN NUMBER FPBGA F4 E10 DESCRIPTION This active low reset signal resets the AS91L1001 and places the device in Slave mode This active low input from either a AS91L1003 or AS91L1006 provides the control status of the AS91L1003/06 connected to the Secondary port of the AS91L1001 (operating in Slave mode) IEEE1149.1 Primary Test Data Input in Slave mode; in Master mode, this pin acts as Test Data Output IEEE1149.1 Primary Test Data Output in Slave mode; in Master mode, this pin acts as Test Data Input IEEE1149.1 Primary Test Reset Input in Slave mode; in Master mode, this pin is an output IEEE1149.1 Primary Test Mode Select in Slave mode; in Master mode, this pin is an output IEEE1149.1 Primary Test Clock in Slave mode; in Master mode, this pin is an output Primary Auto-write input controlled by test equipment to shorten Flash memory programming, signal is driven low for write pulse IEEE1149.1 Test Data Output on Secondary port IEEE1149.1 Test Data Input on Secondary port IEEE1149.1 Test Logic Reset on Secondary port IEEE1149.1 Test Mode Select Out on Secondary port IEEE1149.1 Test Clock Out on Secondary port Secondary Auto-Write Output controlled by test equipment to shorten Flash memory programming, signal is driven low for write pulse
Primary IEEE1149.1 Port PRIM_TDI PRIM_TDO PRIM_TRST PRIM_TMS PRIM_TCK PRIM_AUTOWR INOUT INOUT INOUT INOUT INOUT IN 19 20 22 21 87 16 G3 G1 H2 G2 A6 F1
SECONDARY IEEE1149.1 SEC_TDO SEC_TDI SEC_TRST SEC_TMS SEC_TCK SEC_AUTOWR
OUT IN OUT OUT OUT OUT
57 58 64 60 61 63
G10 G8 E9 F9 F10 F7
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2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved.
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October 2004
AS91L1001
PIN TYPE OUT PIN NUMBER LQFP 71 PIN NUMBER FPBGA DESCRIPTION
PIN NAME SLAVE_MODE MASTER_MODE PRIM_TDO_OE
DATA(7:0) ADDR(31:28)
This signal, when low, indicates that the AS91L1001 is in Slave mode of operation OUT 72 This signal, when low, indicates that the AS91L1001 is in the Master mode of operation OUT 27 This active low signal derived while in Slave Mode, provides the control foradditional current drive to the buffer on the primary TDO signal INOUT 98,97,96,94 A3,B3,A4,B4, 8-bit data bus for the processor ,9392,85,84 C4,C5,C6,C7( interface LSB-MSB LSB-MSB) IN 83,81,80,79 B7,A7,B8,A8( 4-bit address bus for the processor LSB-MSB LSB-MSB) interface
WRn RDn CSn OSC_IN TOE GND
IN IN IN IN IN
77 76 78 75 88
VCC
POWER 11,26,43,59 ,74,95,2,17, 90,55,56,38 ,86 POWER 39,91,3,18, 34,51,66,82 ,23,54 IN IN OUT IN 62 15 73 4
ASIC_TCK ASIC_TMS ASIC_TDO ASIC_TDI
Active low, write enable signal for the processor interface B10 Active low read enable signal for the processor interface A9 Active low, chip select signal for the processor interface C10 This is the master clock into the AS91L1001 device B6 Test output enable this signal when taken low tristates all devices I/O D6,G5,C3,J9, AS91L1001 Ground connection G9,D7,E5,F6, G4,H8,A5,F2, B1 D5, G6, C8, AS91L1001 VCC connection D4, E6, F5, G7, H3, H1, H9 F8 IEEE1149.1 ASIC Test F3 IEEE1149.1 ASIC Test IEEE1149.1 ASIC Test IEEE1149.1 ASIC Test
B9
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2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved.
4
October 2004
AS91L1001
PIN TYPE PIN PIN NUMBER NUMBER LQFP FPBGA 1,5,6,7,8,9, C1,B5,E4,E3, 10,12,13,24 E1,E2,A2,B2, ,25,27,28, C2,D3,D1,D2, 29,30,31,32 J1,K1,K2,C9, D8,D10,D9,E ,33, 35,36,37,40 7,E8,J2,K3,J3 ,H4,J4,K4,H5, ,41, 42,44,45,46 J5,K5,K6,J6,H 6,K7,J7,H7,J8 ,47, 48,49,50,52 ,K8,K10,J10, H10 ,53, 67,68,69,70 ,71, 72,89,99,10 0 DESCRIPTION
PIN NAME No connects
Table 1 - AS91L1001 Signal Description
Absolute Maximum Ratings
Parameter Supply Voltage (Vcc) DC Input Voltage (Vi) Max sink current when Vi = -0.5V Max source current when Vi = Vcc + 0.5V Max Junction Temperature with power applied Tj Max Storage temperature Maximum Range -0.3V to 5.5V -0.5V to Vcc +0.5V -20mA +20mA +125 degrees C -55 to +150 degree C
Table 2 - Absolute Maximum Ratings Note: Stress above the stated maximum values may cause irreparable damage to the device, correct operation of the device at these values is not guaranteed.
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2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved.
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October 2004
AS91L1001
Recommended Operating Conditions
Parameter Supply Voltage (Vcc) Input Voltage (Vi) Output Voltage (Vo) Operating Temperature (Ta) Commercial Industrial (Ta) Operating Range 3.0V to 3.6V 0V to Vcc 0V to Vcc 0 C to 70 C -40 deg C to +85 deg C, 3.00V to 3.6V Table 3 - Recommended Operating Conditions
DC Electrical Characteristics
Symbol VIH VIL Parameter Minimum High Input Voltage Maximum Low Input Voltage Parameter Minimum High Output Voltage Minimum Low Output Voltage Tristate output leakage Maximum quiecennt supply current Maximum dynamic supply current Min 2.0 -0.3V Max 5.25 0.8V Condition
Symbol VOH VOL Ioz Icc Iccd
Value 2.4V 0.4V -10 or 10 mA 2mA 80mA
Condition Ioh=24mA or 8mA as defined by pin Iol=24mA or 8mA as defined by pin
TCK freq equal to 10 MHz
Table 4 - AS91L1001 DC Electrical Characteristics
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2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved.
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October 2004
AS91L1001
AC Timing Information
From To Type Setup Hold Value 18ns -3ns 5 to 17ns 11ns 13ns 66MHz 5ns 1ns 11ns 25ns
Prim_TCK/Sec_TCK Prim/ Sec Inputs Prim_TCK/Sec_TCk OSC_IN OSC_IN OSC_IN OSC_IN CSn CSn CSn CSn Prim inputs Sec inputs Sec output Prim output Cpu i/f inputs Cpu i/f inputs Databus Prim/Sec Inputs
Prim_TCK/Slave_tck Delay Prim outputs Sec outputs Delay Delay Freq Setup Hold Delay Width (low)
Comb Delay 9ns Comb Delay 9ns
Table 5 - AS91L1001 AC timing information
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2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved.
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October 2004
AS91L1001
Packaging Information
The AS91L1001 is available in a 100-pin LQFP or a 100-pin FPBGA lead free package.
SYMBOL
LEAD S
TO L.
100 LEAD
1
A
MAX.
1
1 .6 0
0 .0 5 0 .1 5
D Square D1 Square
A
M IN
MAX
A
2
M IN
NOM
MAX
1 .3 5
1 .4 0
1 .4 5
D
B A S IC
1
1 6 .0 0
D
L
B A S IC
0 .1 5
REF
M IN MAX
1 4 .0 0
0 .6 0
1 .0 0
0 .1 7
0 .5 0
0 .0 8
0 .0 8
L1
b
e
ccc
ddd
0 .2 7
B A S IC
MAX
NOM
JED E C R EF #
M S -0 2 6
3
NOTES : 1. ALL LIN EAR DIM ENSIO NS ARE IN M ILLIM E TE RS . 2. PLAS TIC BO DY D IM EN SIO NS DO N O T INC LU DE FLAS H O R PR O TUSIO N . M AX ALLO W ABLE 0.25 PER SIDE. 3. LEAD C O UN T O N D RA W ING N O T RE PRESENTATIVE O F A CTUAL PACKAG E.
12 NOM
A
0-7 TYP
A1
A2
-C0.09/0.20 TYP
A
e
0.25
L1 L
b
CCC LEAD COPLANARITY al al al M A-B S DS
12 NOM
Figure 6 - LQFP-100
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2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved.
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October 2004
AS91L1001
D 2
A B
REV. A B
Revisions DESCRIPTION Initial document release. Updated ball coplanarity limits from 0.20mm to 0.15mm.
ECN 91253
DATE 12-04-01
E
C
0.15 C
D1
K I H G F E D C B A 1 2 3 4 5 6 7 8 9 10
E1
SYMBOL A A1 A2 b D D1 E E1 e PACKAGE NUMBER JEDEC REF #
DIMENSIONS MIN. -0.30 0.25 0.50
NOM. ---0.60 11.00 BSC 9.00 BSC 11.00 BSC 9.00 BSC 1.00 FBGA0100-11F MO-192 VAR. AAC-1
MAX. 1.70 -1.10 0.70
b
0.25 M 0.25 M
CAB C
Figure 7 - FPBGA-100
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2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved.
10
October 2004
AS91L1001
Device Selector Guide and Ordering Information
AS91L
Aliance Semiconductor system solution
XXXX
UU - CC PP - TEMP - L
Blank = leaded F = lead free G = green
Device family 1001 1002 1003 1006 Product version S = standard U = 16-bit user code BU = 8-bit status/user code E = enhanced
C = Commercial (0 to 70 degrees C) I = Industrial (-40 to 85 degrees C) Package L100 = 100 pin LQFP F100 = 100 pin FPBGA Clock speed 10 = Low Frequency 40 = High Frequency
Figure 8 - Part Numbering Guide
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2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved.
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October 2004
AS91L1001
Description JTAG Test Controller, 100-pin LQFP package, commercial JTAG Test Controller, 100-pin LQFP package, industrial JTAG Test Controller 100-pin FPBGA package, commercial JTAG Test Controller 100-pin FPBGA package, industrial JTAG Test Controller, 100-pin LQFP package, commercial, High frequency JTAG Test Controller, 100-pin LQFP package, commercial, lead free, High Frequency JTAG Test Controller, 100-pin LQFP package, industrial, High Frequency JTAG Test Controller, 100-pin LQFP package, industrial, lead free, High Frequency JTAG Test Controller 100-pin FPBGA, commercial, High Frequency JTAG Test Controller 100-pin FPBGA, commercial, green package, High Frequency JTAG Test Controller 100-pin FPBGA, industrial, High Frequency JTAG Test Controller 100-pin FPBGA, industrial, green package, High Frequency Table 6 - Valid Part Number Combinations Availability now now Please contact Alliance Semiconductor Please contact Alliance Semiconductor Please contact Alliance Semiconductor now
Part Number AS91L1001S - 10L100-C AS91L1001S - 10L100-I AS91L1001S - 10F100-C AS91L1001S - 10F100-I AS91L1001S - 40L100-C
AS91L1001S - 40L100-CF
AS91L1001S - 40L100-I
Please contact Alliance Semiconductor now
AS91L1001S - 40L100-IF
AS91L1001S - 40F100-C
Please contact Alliance Semiconductor Please contact Alliance Semiconductor Please contact Alliance Semiconductor Please contact Alliance Semiconductor
AS91L1001S - 40F100-CG
AS91L1001S - 40F100-I
AS91L1001S - 40F100-IG
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Alliance Semiconductor
2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved.
12
October 2004
AS91L1001
Device Master AS91L1001 AS91L1002 AS91L1003U
Description
FPBGA-100 (1mm pitch)
Package Options
LQFP-100
JTAG Test Controller JTAG Test Sequencer 3-Port Gateway
x x x x
x x x x
AS91L1006BU 6-Port Gateway
Table 7 - JTAG Controller Product Family
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Alliance Semiconductor
2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved.
13
October 2004
AS91L1001
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2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved.
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