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| December 2004 AS91L1003U Description 3-Port JTAG Gateway control. Partitioning the IEEE1149.1 chains on the PCB has several benefits, which include easier fault diagnostics capabilities, as a fault on one of the IEEE1149.1 Local Scan Ports (LSPs) does not render the PCB un-testable, faster flash programming on the PCB's and removal of IEEE1149.1 signal loading issues. All of the protocols required for addressing the AS91L1003U device via the MultiDrop capability and the protocols for configuring which of the three IEEE1149.1 LSPs of the AS91L1003U are to be used, is handled via the 3rd party ATPG tools from vendors like AssetIntertech and JTAG Technologies. In a Multi-Drop environment, it is also possible to perform interconnect tests between multiple PCBs within the system thus extending the interconnect tests to the back plane itself. The AS91L1003U is a one to 3-port JTAG gateway. It partitions a single JTAG chain into three separate chains. These separate chains can be optionally configured to operate as a single chain. The AS91L1003U device is used to provide enhanced capabilities to the standard IEEE1149.1. It enables the IEEE1149.1 interface to be used in a true Multi-Drop environment without any additional signals. This Multi-Drop capability enables the standard IEEE1149.1 interface to be used not just for stand alone Printed Circuit Board (PCB) testing, but complete system testing including all PCBs within a system back plane environment. The AS91L1003U provides the capability of partitioning the PCB into multiple smaller IEEE1149.1 scan chains totally under software Key Features Device Multi-Drop addressable via the IEEE 1149.1 protocol Support for 3 local scan chains addressable via the IEEE 1149.1 interface Support for Pass-Through Support for the IEEE 1149.1 USERCODE instruction Support for Status instruction enabling nonintrusive monitoring of the system card Local Scan Port (LSP) enable signal provides the ability to use non IEEE 1149.1 compliant devices that require JTAG enable signal Provides the ability to initiate Self-Test on a remote PCB via a standard IEEE 1149.1 command Support for JTAG Technologies AutoWR feature Pinout and feature set compatible (complete second source) with the Firecron JTS03U device Available in a 100-pin LQFP or a 100-pin FPBGA lead free package Device Block Diagram P a s s T h r o u g h E n a b le P r im a r y 1 1 4 9 .1 J T A G In te rfa c e S ta tu s D a ta U s e rc o d e D a ta 1 1 4 9 . 1 T A P C o n t r o l le r and B o u n d a r y R e g is t e r S e l e c t io n L o g i c LSP1 Pass T h ro u g h L o g ic & Local S can P o rt C o n n e c tio n /C o n f ig lo g ic LSP2 LSP3 D e v ic e a d d re s s D e v ic e S e le c tio n L o g ic L o c a l S c a n P o rt P a rk /U n -p a rk S y n c L o g ic Figure 1 - AS91L1003U Device Block Diagram Alliance Semiconductor 2575 Augustine Drive * Santa Clara, CA 95054 * T: 408-855-4900 * F: 408-855-4999 * www.alsc.com December 2004 AS91L1003U AS91L1003U Gateway Functional Description The basic structure of the AS91L1003U device is shown in Figure 1. The core of the device is the 16-state IEEE1149.1 TAP controller state machine. All accesses to the internal registers of the AS91L1003U device are controlled via this state machine during normal operation as per the IEEE1149.1 standard. The address selection logic enables the AS91L1003U to operate in a MultiDrop environment within system backplane. The address selection logic compares the scanned address to the slot address value presented on the I/O of the AS91L1003U device. The LSP park/unpark logic provides control through instructions scanned in under the IEEE1149.1 protocol, to select which LSP will be placed into the active scan chain. The passthrough and LSP connection logic selects the signal paths for the LSP IEEE1149.1 signals. The device also supports a Pass-Through mode which enables the primary IEEE1149.1 signals to be routed to any of the LSPs. This signal routing is selectable via I/O pins on the AS91L0003U device. The AS91L1003U operation is controlled via core blocks through three closely coupled state machines. Figure-2 shows the device selection state machine. The AS91L1003U will perform an address compare on the slot address presented at its I/O and the value scanned in via the IEEE1149.1. If the value matches, then the AS91L1003U becomes selected and is ready for normal access via IEEE1149.1 commands. If the address does not match then the device will proceed to the unselected mode, where it will remain until the AS91L1003U is issued a GOTOWAIT instruction or a reset occurs via either TRST or the LSP_RESET pin. Selected Single Device Device Unselected Parked-RTI Wait for Selection Parked-TLR ParkedPauseDR UnParked Select Group of Devices Select All Devices ParkedPauseIR Figure 2 - AS91L1003U Selection Logic State machine Figure 3 - The LSP Park/Unpark State Machine The LSP Park/Unpark state machine controls the insertion of the LSPs into the current active scan chain. The ability to park the LSP in certain IEEE1149.1 states, enable the AS91L1003U to perform several functions including backplane interconnect testing and IC BIST. www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 2 December 2004 AS91L1003U AS91L1003U Detailed Mode of Operation Addressing the AS91L1003U device After a Test-Logic-Reset or power-up, the AS91L1003U device will be in its Wait-forSelection state with its TDO pin tri-stated, thus avoiding contention in a Multi-Drop environment. The AS91L1003U device will respond to a deviceselect sequence for a particular address that is auto generated by third party test tools with respect to the address that is pre-loaded on its S(5..0) pins. Once this sequence has been completed, the AS91L1003U device will respond to normal IEEE 1149.1 instructions. Note that addresses 60-63 have been reserved and the AS91L1003U device will not respond if the user selects these addresses. To be selected, the AS91L1003U device should be in the Wait-for-Selection mode which can be entered into by issuing an asynchronous reset (through the deassertion of TRST) or by issuing synchronous reset (through the assertion of TMS for five cycles of TCK). After the device has been selected, it can be issued a GOTOWAIT instruction or a reset of the AS91L1003U device. The internal IEEE1149.1 state machine of the AS91L1003U device is taken to the Shift-IR phase and the required Device-ID is shifted into the Instruction register. As the IEEE1149.1 state machine passes through the Update-IR phase, the address is matched to the value on the S(5-0) pins on the AS91L1003U device; if the values match then the AS91L1003U device is selected and is ready to receive any normal IEEE1149.1 command. S(5-0) value < 3A hex or 60 decimal IR (7 - 0) value XXVVVVVV Table 1 - AS91L1003U Device Selection Table www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 3 December 2004 AS91L1003U Table 2 - AS91L1003U Multi Cast Group Selection Table Selection Mode Single Address Mode Binary Function Address XX000000 to Single AS91L1003U XX111010 selected the TDO of the device will be active All accessible AS91L1003U devices are selected for operation. TDO on all devices will be in HighZ Access all AS91L1003U device that have been placed in GRP0 by their MCGR contents Access all AS91L1003U device that have been placed in GRP1 by their MCGR contents Access all AS91L1003U device that have been placed in GRP2 by their MCGR contents Access all AS91L1003U device that have been placed in GRP3 by their MCGR contents Table 3 - AS91L1003U Device Register Description Register Name Instruction Register Description AS91L1003U device addressing and instruction-decode IEEE Std. 1149.1 required register IEEE Std. 1149.1 required register IEEE Std. 1149.1 required register IEEE Std. 1149.1 optional register IEEE Std. 1149.1 optional register AS91L1003U device non intrusive 8-bit register pre load able from the I/O pins AS91L1003U device specific single bit register for initiating self testing on a PCB AS91L1003U device local-port configuration and control bits AS91L1003U device Auto Write feature enable register AS91L1003U device Async reset register for the LSPs BroadXX111011 Cast Mode Multi-Cast XX111100 Group 0 Multi-Cast XX111101 Group 1 BoundaryScan Register Bypass Register Device Identification Register User Code Register Status Register Self Test Register Mode Register Auto Write Register Local Scan Port Async Reset Register Multi-Cast XX111110 Group 2 Multi-Cast XX111111 Group 3 www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 4 December 2004 AS91L1003U Hex OpCode FF 00 81 AA E7 C5 84 C6 C3 8E 03 88 97 98 99 9A 9B TBD Binary Op- Data Register Code 11111111 Bypass Register 00000000 10000001 10101010 11100111 11000101 10000100 11000110 11000011 10001110 00000011 10001000 10010111 10011000 10011001 10011010 10011011 TBD Boundary-Scan Register Boundary-Scan Register Device Identification Register Device Identification Register Device Identification Register Device Identification Register Device Identification Register Device Identification Register Mode Register Multi-Cast Group Register. Device Identification Register User Programmable 32 Bit Identification Register Auto Write Feature Enable Register Single bit low pulse used to initiate function on PCB (SELF_TEST pin) User programmable status byte (USER_STATUS_DATA pins) Toggles LSP TRST while maintaining the AS91L1003U in the selected state. Device Identification Register Instructions BYPASS EXTEST SAMPLE/PRELOAD IDCODE UNPARK PARKTLR PARKRTI PARKPAUSE GOTOWAIT* MODESELECT MCGRSELECT SOFTRESET USERCODE AUTOWR STEST_PCB STATUS_BYTE LSP_ASYNC_RESET Other Undefined Table 4 - AS91L1003U Device Instruction Register OpCodes Note: All instructions act on a single selected AS91L1003U device only. * This instruction causes the AS91L1003U to become unselected and revert to the Wait-forSelection state. www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 5 December 2004 AS91L1003U AS91L1003U device Register descriptions Bypass Register It is a mandatory single bit register that can be connected between PRIM_TDI and PRIM_TDO of the AS91L1003U device. MCGR Register Bits [1..0] 00 01 10 11 Multi-Cast Group Register This 2-bit data register enables the host system to place the AS91L1003U into one of four distinct addressable groups. MCGR GROUP GRP0 GRP1 GRP2 GRP3 Binary Selection Address XX111100 XX111101 XX111110 XX111111 Table 5 - Multicast Group Register Mapping Note: The MCGR is reset to 00 upon receiving TRST or the entering of the Test-Logic-Reset state. IDCODE Register It is an optional 32-bit register that can be connected between PRIM_TDI and PRIM_TDO of the AS91L1003U device. The contents of the IDCODE register will be loaded with the following data when the AS91L1003U enters Test-LogicReset or passes through Capture-IR: "00000000000000001000001101101111" Bits 0 to 11 indicate ALSC Jedec ID value of: "001101101111" Bits 12 to 27 indicate the part number of the device: "0000000000010000" Bits 28 to 31 indicate the revision of the device: "0000" USERCODE Register The USERCODE is a 32-bit register that can be addressed via standard IEEE1149.1 commands, which are automatically generated by third party test tools. The end user has the ability to program the binary value that will be transmitted back to the host via the USERCODE command; by setting the binary pattern on the USERCODE pins on the AS91L1003U device. * The AS91L1003U is a complete second source and pin for pin replacement of the Firecron JTS03U device. www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 6 December 2004 AS91L1003U STATUS_BYTE Register The STATUS_BYTE register on the AS91L1003U device provides a means to sense the value on the USER_STATUS_DATA pins on the AS91L1003U device. This is an 8-bit field where the user can non-intrusively monitor signals on the printed circuit card via the IEEE1149.1 interface. The data in the register is loaded each time the state machine passes through the Capture-DR phase. Note: Value is positive logic. LSP_ASYNC_RST Register The AS91L1003U device supports async reset tests on the devices connected to the LSPs. The standard method of performing these tests by utilizing the PRIM_TRST pin cannot be used as it will cause the AS91L1003U to deselect and all its internal registers to be reset. In order to enable async reset tests on the LSP, the test tool should instruct the device to toggle the local scan port reset pins while maintaining the set up information in the AS91L1003U. When the instruction is loaded into the AS91L1003U instruction register, a single bit data register is connected which is always set to zero when the TAP state machine enters Capture-DR. This will cause the LSP TRST pins to pulse low for one TCK cycle, during the Update-DR phase. SELF_TEST Register The AS91L1003U device supports a single output pin that can be controlled via the IEEE1149.1 interface. When the instruction is loaded into the AS91L1003U instruction register, a single bit data register is connected which is set to zero when the TAP state machine enters CaptureDR. This will cause the SELF_TEST pin to pulse low for one cycle of TCK, during the Update-DR phase. This low going pulse can be used to initiate self-tests on PCB's in a rack via the JTAG interface. AutoWr Register (Bit 2 - Bit 0) 000 001 011 100 101 110 111 LSP 3 AutoWr Signal High Z High Z High Z Active Active Active Active AUTOWR Register This is a 3-bit register that controls the passthrough of the JTAG Technologies AutoWR signal to any Local Scan Port. The register is reset to all zeros when entering the Test-LogicReset state. LSP 2 AutoWr Signal High Z High Z Active High Z High Z Active Active LSP 1 AutoWr Signal High Z Active Active High Z Active High Z Active Table 6 - AUTOWR Register Mapping www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 7 December 2004 AS91L1003U If the Local Scan Port is not parked in a stable state, i.e.: Pause-DR, Pause-IR, Run-TestIdle or Test-Logic-Reset, it will be connected into the active scan chain. If all LSPs are parked in a stable state, then the AS91L1003U will perform a loopback of TDI->Register->TDO. MODE_SELECT Register The Mode_Select register allows the Local Scan Port of the AS91L1003U to be connected in various different configurations. A LSP is selected for connection within the scan chain by the contents of the Mode_Select register. Mode_Select Register LSP Configuration (If Port Unparked) (Bit 7 -> Bit 0) XXX0X000 TDI->Register->TDO XXX0X001 XXX0X010 XXX0X011 XXX0X100 XXX0X101 XXX0X110 XXX0X111 TDI->Register->LSP1->PAD->TDO TDI->Register->LSP2->PAD->TDO TDI->Register->LSP1->PAD->LSP2->PAD->TDO TDI->Register->LSP3->PAD->TDO TDI->Register->LSP1->PAD->LSP3->PAD->TDO TDI->Register->LSP2->PAD->LSP3->PAD->TDO TDI->Register->LSP1->PAD->LSP2->PAD->LSP3->PAD->TDO Table 7 - Mode Select Register Mapping X = don't care Register = AS91L1003U device instruction register or any of the AS91L1003U device test data registers. PAD = Insertion of a 1-bit register for data synchronization. Upon entering Test-Logic-Reset, the register bits will be loaded with "0000000". www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 8 December 2004 AS91L1003U Pass-Through Support within the AS91L1003U Device The AS91L1003U device supports a PassThrough mode where the primary or master IEEE1149.1 JTAG signals can be routed to any one of the LSPs. When this mode is activated, the "Debug Enable" signal for that LSP will go active, which can be used to place a processor such as the MPC8260 into BDM (Background Debug Mode) if required. If no processors are present in the LSP, the Pass-Through mode can be used to assist in the generation of the test vectors or memory tests for the devices that are linked into the selected LSP. The pass-through feature has the effect of simplifying the test vector generation for the LSP, as it also has the effect of removing the AS91L1003U device from the test vector generation process. The pass-through mode can be used in FPGA or PLD programming applications, where a direct path between the primary and a specific LSP is desired. PASS_THRU_ENABLE High Low Low Low PASS_THRU_SEL(1) X Low Low High PASS_THRU_SEL(0) X Low High Low Active LSP Normal Operation LSP1 LSP2 LSP3 Table 8 - Pass-Through mode in AS91L1003U Note: When PASS_THRU_ENABLE enable is deasserted (logic "1"), then the LSPs are under control of the AS91L1003U device logic. www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 9 December 2004 AS91L1003U Signal Description PIN NUMBER LQFP 31 PIN NUMBER FPBGA H4 Stable signals states, with device unselected and active outputs on the device Buffered version of signal present on primary TCK PIN NAME PIN TYPE OUT DESCRIPTION LSP1_TCK IEEE1149.1 Test Clock on Local Scan Port 1 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[1:0] = 00. This pin is tri-stated for all other combinations. IEEE1149.1 Test Mode Select on Local Scan Port 1 when PASS_THRU_ENABLE is HIGH. LSP1_TMS OUT 32 J4 Logic '1' LSP1_TDO OUT 35 H5 Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[1:0] = 00. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data Out on Local Logic '1' Scan Port 1 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[1:0] = 00. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data In on Local Scan Port 1 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[1:0] = 00. IEEE1149.1 Test Reset on Local Scan Port 1 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[1:0] = 00. LSP1_TDI IN 33 K4 LSP1_TRST OUT 29 K3 Buffered version of signal present on primary TRST www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 10 December 2004 AS91L1003U Stable signals states, with device unselected and active outputs on the device Logic '1' PIN NAME PIN TYPE OUT PIN NUMBER LQFP 30 PIN NUMBER FPBGA J3 DESCRIPTION LSP1_AutoWR Flash, Memory Auto-Write on Local Scan Port 1 when PASS_THRU_ENABLE is HIGH. LSP1_DE OUT 28 J2 Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[1:0] = 00. This pin is tri-stated for all other combinations. Pass-Through Debug Enable Output Logic '1' on Local Scan Port 1. Active low output when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[1:0] =00. This pin is high for all other combinations. IEEE1149.1 Test Clock on Local Scan Port 2 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[1:0] = 01. This pin is tri-stated for all other combinations. IEEE1149.1 Test Mode Select on Local Scan Port 2 when PASS_THRU_ENABLE is HIGH. LSP2_TCK OUT 41 J6 Buffered version of signal present on primary TCK LSP2_TMS OUT 42 H6 Logic '1' LSP2_TDO OUT 45 J7 Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[1:0] = 01. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data Out on Local Logic '1' Scan Port 2 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[1:0] = 01. This pin is tri-stated for all other combinations. www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 11 December 2004 AS91L1003U Stable signals states, with device unselected and active outputs on the device PIN NAME PIN TYPE IN PIN NUMBER LQFP 44 PIN NUMBER FPBGA K7 DESCRIPTION LSP2_TDI IEEE1149.1 Test Data In on Local Scan Port 2 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[1:0] = 01. IEEE1149.1 Test Reset on Local Scan Port 2 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[1:0] = 01. LSP2_TRST OUT 37 K5 Buffered version of signal present on primary TRST LSP2_AutoWR OUT 40 K6 Flash, Memory Auto-Write on Local Scan Port 2 when PASS_THRU_ENABLE is HIGH. Logic '1' LSP2_DE OUT 36 J5 Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[1:0] = 01. This pin is tri-stated for all other combinations. Pass-Through Debug Enable Output Logic '1' on Local Scan Port 2. Active low output when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[1:0] =01. This pin is high for all other combinations. IEEE1149.1 Test Clock on Local Scan Port 3 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[1:0] = 10. This pin is tri-stated for all other combinations. LSP3_TCK OUT 49 K9 Buffered version of signal present on primary TCK www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 12 December 2004 AS91L1003U Stable signals states, with device unselected and active outputs on the device Logic '1' PIN NAME PIN TYPE OUT PIN NUMBER LQFP 50 PIN NUMBER FPBGA K10 DESCRIPTION LSP3_TMS IEEE1149.1 Test Mode Select on Local Scan Port 3 when PASS_THRU_ENABLE is HIGH. LSP3_TDO OUT 53 H10 Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[1:0] = 10. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data Out on Local Logic '1' Scan Port 3 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[1:0] = 10. This pin is tri-stated for all other combinations. IEEE1149.1 Test Data In on Local Scan Port 3 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[1:0] = 10. IEEE1149.1 Test Reset on Local Scan Port 3 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[1:0] = 10. LSP3_TDI IN 52 J10 LSP3_TRST OUT 47 J8 Buffered version of signal present on primary TRST LSP3_LSP_ AutoWR OUT 48 K8 Flash, Memory Auto-Write on Local Scan Port 3 when PASS_THRU_ENABLE is HIGH. Pin is in Pass-Through mode when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[1:0] = 10. This pin is tri-stated for all other combinations. Logic '1' www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 13 December 2004 AS91L1003U Stable signals states, with device DESCRIPTION unselected and active outputs on the device Pass-Through Debug Enable Output Logic '1' on Local Scan Port 3. Active low output when PASS_THRU_ENABLE = 0 and PASS_THRU_SEL[1:0] =10. This pin is high for all other combinations. IEEE1149.1 Primary Test Clock Input. IEEE1149.1 Primary Test Mode Select Input. IEEE1149.1 Primary Test Data HighZ Output. This pin is tri-stated when AS91L1003 is not selected. IEEE1149.1 Primary Test Data Input IEEE1149.1 Primary Test Reset Input. PIN NAME PIN TYPE OUT PIN NUMBER LQFP 46 PIN NUMBER FPBGA H7 LSP3_DE PRIM_TCK PRIM_TMS PRIM_TDO IN IN OUT 87 21 20 A6 G2 G1 PRIM_TDI PRIM_TRST IN IN 19 22 G3 H2 PRIM_AutoWR S[5:0] IN IN *TOE IN This active low asynchronous reset input signal places AS91L1003U in Wait-for-Selection state. 16 F1 Primary Auto-Write Input controlled by test equipment to shorten Flash memory programming. 8,7,6,5,100, D2,D1,D3,C2, Slot Address (5:0) Inputs. 99 B2,A2 Used to set address at which AS91L1003U will respond; typically set by hardwired connection on the backplane. 88 B6 Test Output Enable Input. Tri-states all LSPs, when asserted low. Local Scan Port Reset Input. Active low resets AS91L1003U to "Wait-for-Selection" state and pulses all LSP TRST output pins to low. This resets all devices with TRST function; typically this signal would be connected to a power-on-reset function. LSP_RESET_n IN 14 F4 www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 14 December 2004 AS91L1003U Stable signals states, with device unselected and active outputs on the device PIN NAME PIN TYPE OUT PIN NUMBER LQFP 25 PIN NUMBER FPBGA K1 DESCRIPTION AS91L1003U_ SELECTED AS91L1003U_Selected Output. Active low when AS91L1003U is selected; typically used to control off board buffering. Local Scan Port Enable Output. LSP_ENABLE OUT 24 J1 USERCODE [15:0] IN USER_STATUS _BYTE[7:0] IN SELF_TEST OUT PASS_THRU_ ENABLE IN Active low output when AS91L1003U is selected; typically used to set IEEE1149.1 compliance enable pins on devices. 64,65,67,68 E9,E10,E8,E7 User/Board Identification Inputs. ,69,70,71,7 ,D9,D10,D8,C 2,75,76,77, 9,C10,B10,B9 Used to establish board type and 78,79,80,81 ,A9,A8,B8,A7, revision so as to ensure correct ,83 (MSBB7 (MSB- IEEE1149.1 test vector sets are LSB) LSB) applied. 84, 85, 92, C7,C6,C5,C4, USER_Status_Byte Inputs. 93, 94, 96, B4,A4,B3,A3( 97, 98 MSB-LSB) Used to provide status information of (MSB-LSB) the PCB under test back to the test master via the IEEE1149.1 bus. Eight signals levels can be monitored and then reported via the IEEE1149.1 bus in a non intrusive manner. 27 K2 Provides a low going output pulse Logic '1' under command from the IEEE1149.1 bus, which can be used to start self-test functions on a PCB. 9 E4 PASS_THRU Enable Input. Active high disables Pass-Through mode. Active low enables Pass-Through mode. PASS_THRU Select Inputs. Used to select active routing of PassThrough ports enabled by active low on PASS_THRU_ENABLE pin. 00 = LSP1 01 = LSP 10 = LSP3 PASS_THRU_ SEL[1:0] IN 12,10 E1,E3 www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 15 December 2004 AS91L1003U Stable signals states, with device unselected and active outputs on the device PIN NAME PIN TYPE PIN NUMBER LQFP PIN NUMBER FPBGA DESCRIPTION GND VCC ASIC_TEST_ EN ASIC_TCK ASIC_TMS ASIC_TDO ASIC_TDI No Connects POWER 38, 86, 11, D6, G5, C3, Ground Pins. 26, 43, 59, D7, E5, F6, 74, 95, 2, G4,H8, H9, 17, 54, 90 J9,B1, A5, F2 POWER 39, 91, 3, D5, G6, C8, VCC pins. 18, 34, 51, D4, E6, F5, 66, 82,23, G7, H3,G9,H1 55, 56 IN 89 B5 Factory Test_Enable Input. IN IN OUT IN 62 15 73 4 F8 F3 A10 A1 This pin should be left unconnected. IEEE1149.1 ASIC Test Clock Input. IEEE1149.1 ASIC Test Mode Select Input. IEEE1149.1 ASIC Test Clock Output. IEEE1149.1 ASIC Test Clock Input. 1,13,63,61, C1,E2,F7,F10 60,58,57 ,F9,G8,G10 Table 10 - AS91L0003U Signal Description www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 16 December 2004 AS91L1003U Absolute Maximum Ratings Parameter Supply Voltage (Vcc) DC Input Voltage (Vi) Max sink current when Vi = -0.5V Max source current when Vi = Vcc + 0.5V Max Junction Temperature with power applied Tj Max Storage temperature Maximum Range -0.3V to 5.5V -0.5V to Vcc +0.5V -20mA +20mA +125 degrees C -55 to +150 degree C Table 11 - Absolute Maximum Ratings Note: Stress above the stated maximum values may cause irreparable damage to the device. Correct operation of the device at these values is not guaranteed. Recommended Operating Conditions Parameter Supply Voltage (Vcc) Input Voltage (Vi) Output Voltage (Vo) Operating Temperature (Ta) Commercial Industrial (Ta) Operating Range 3.0V to 3.6V 0V to Vcc 0V to Vcc 0 C to 70 C -40 deg C to +85 deg C, 3.00V to 3.6V Table 12 - Recommended Operating Conditions www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 17 December 2004 AS91L1003U AC Electrical Characteristics Tch TCK Tsu Th Tcl Tcw TMS TDI Toe Tco TDO Tpd Lsp Signal High Z High Z Figure 4 - AS91L1003U AC Timing Diagram SYMBOL Parameter Tcw Tch Tcl Tsu Th Toe Tco Tpd TCK clock pulse width TCK pulse width high TCK pulse width low TCK Setup time TCK Hold time Neg Edge TCK to valid data enable Neg Edge TCK to valid data Pass through Mode Primary/LSP Delay MIN 100 50 50 30 40 20 15 MAX 10 UNITS ns ns ns ns ns ns ns ns Table 9 - AS91L1003U AC Timing Information www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 18 December 2004 AS91L1003U DC Electrical Characteristics Symbol VIH VIL Parameter Minimum High Input Voltage Maximum Low Input Voltage Parameter Minimum High Output Voltage Minimum Low Output Voltage Tristate output leakage Maximum quiecennt supply current Maximum dynamic supply current Min 2.0 -0.3V Max 5.25 0.8V Condition Symbol VOH VOL Ioz Icc Iccd Value 2.4V 0.4V -10 or 10 mA 2mA 80mA Condition Ioh=24mA or 8mA as defined by pin Iol=24mA or 8mA as defined by pin TCK freq equal to 10 MHz Table 13 - AS91L1003U DC Electrical Characteristics AC Timing Information From Prim_TCK Prim_TCK To Prim inputs Prim inputs Type Setup Hold Setup Hold Value 3ns 2ns 7ns 0ns LSP[1:3]_TCK LSP inputs LSP[1:3]_TCK LSP inputs Prim inputs LSP inputs Prim_TCK Prim_TCK LSP_TCK Prim_TCK LSP outputs Comb Delay 11.5ns Prim outputs Comb Delay 10ns LSP_TCK Comb Delay 8.5ns 10ns 5ns 40MHz Prim outputs Delay LSP outputs Delay Freq Table 14 - AS91L1003U AC Timing Information www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 19 December 2004 AS91L1003U Packaging Information The AS91L1003U is available in a 100-pin LQFP or a 100-pin FPBGA lead free package. SYMBOL LEAD S TO L. MAX. 1 2 100 LEAD 1 .6 0 0 .0 5 1 .3 5 1 .4 0 1 6 .0 0 1 4 .0 0 0 .6 0 1 .0 0 0 .1 7 0 .5 0 0 .0 8 0 .0 8 M S -0 2 6 0 .2 7 0 .1 5 1 .4 5 1 A D Square D1 Square A A D D L M IN M IN MAX MAX NOM B A S IC 1 B A S IC 0 .1 5 REF M IN MAX L1 b e ccc ddd B A S IC MAX NOM JED E C R EF # 3 NOTES : 1. ALL LIN EAR DIM ENSIO NS ARE IN M ILLIM E TE RS . 2. PLAS TIC BO DY D IM EN SIO NS DO N O T INC LU DE FLAS H O R PR O TUSIO N . M AX ALLO W ABLE 0.25 PER SIDE. 3. LEAD C O UN T O N D RA W ING N O T RE PRESENTATIVE O F A CTUAL PACKAG E. 12 NOM A 0-7 TYP A1 A2 -C0.09/0.20 TYP A e 0.25 L1 L b CCC LEAD COPLANARITY al al al M A-B S DS 12 NOM Figure 5 - LQFP-100 www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 20 December 2004 AS91L1003U D 2 A B REV. A B Revisions DESCRIPTION Initial document release. Updated ball coplanarity limits from 0.20mm to 0.15mm. ECN 91253 DATE 12-04-01 E C 0.15 C D1 K I H G F E D C B A 1 2 3 4 5 6 7 8 9 10 E1 SYMBOL A A1 A2 b D D1 E E1 e PACKAGE NUMBER JEDEC REF # DIMENSIONS MIN. -0.30 0.25 0.50 NOM. ---0.60 11.00 BSC 9.00 BSC 11.00 BSC 9.00 BSC 1.00 FBGA0100-11F MO-192 VAR. AAC-1 MAX. 1.70 -1.10 0.70 b 0.25 M 0.25 M CAB C Figure 6 - FPBGA-100 www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 20 December 2004 AS91L1003U Device Selector Guide and Ordering Information AS91L Aliance Semiconductor system solution XXXX UU - CC PP - TEMP - L Blank = leaded F = lead free G = green C = Commercial (0 to 70 degrees C) I = Industrial (-40 to 85 degrees C) Package L100 = 100 pin LQFP F100 = 100 pin FPBGA Clock speed 10 = Low Frequency 40 = High Frequency Device family 1001 1002 1003 1006 Product version S = standard U = 16-bit user code BU = 8-bit status/user code E = enhanced Figure 7 - Part Numbering Guide www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 21 December 2004 AS91L1003U Description 3-Port JTAG Gateway, 100-pin LQFP package, commercial 3-Port JTAG Gateway, 100-pin LQFP package, industrial 3-Port JTAG Gateway, 100-pin FPBGA package, commercial 3-Port JTAG Gateway, 100-pin FPBGA package, industrial 3-Port JTAG Gateway, 100-pin LQFP package, commercial, High Frequency 3-Port JTAG Gateway, 100-pin LQFP package, commercial, lead free, High Frequency 3-Port JTAG Gateway, 100-pin LQFP package, industrial, High Frequency 3-Port JTAG Gateway, 100-pin LQFP package, industrial, lead free, High Frequency 3-Port JTAG Gateway, 100-pin FPBGA, commercial, High Frequency 3-Port JTAG Gateway, 100-pin FPBGA, commercial, green package, High Frequency 3-Port JTAG Gateway, 100-pin FPBGA, industrial, High Frequency 3-Port JTAG Gateway, 100-pin FPBGA, industrial, green package, High Frequency Table 15 - Valid Part Number Combinations Availability now now Please Contact Alliance Semiconductor Please Contact Alliance Semiconductor Please Contact Alliance Semiconductor now Part Number AS91L1003U - 10L100-C AS91L1003U - 10L100-I AS91L1003U - 10F100-C AS91L1003U - 10F100-I AS91L1003U - 40L100-C AS91L1003U - 40L100-CF AS91L1003U - 40L100-I Please Contact Alliance Semiconductor now AS91L1003U - 40L100-IF AS91L1003U - 40F100-C Please Contact Alliance Semiconductor Please Contact Alliance Semiconductor Please Contact Alliance Semiconductor Please Contact Alliance Semiconductor AS91L1003U - 40F100-CG AS91L1003U - 40F100-I AS91L1003U - 40F100-IG www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 22 December 2004 AS91L1003U Device Master AS91L1001 AS91L1002 AS91L1003U AS91L1006BU Description FPBGA-100 (1mm pitch) Package Options LQFP-100 JTAG Test Controller JTAG Test Sequencer 3-Port Gateway 6-Port Gateway x x x x x x x x Table 16 - JTAG Controller Product Family www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 23 December 2004 AS91L1003U www.alsc.com Alliance Semiconductor 2003, 2004 (c) Copyright Alliance Semiconductor Corporation. All Rights reserved. 24 |
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