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Features
* AVR(R) Microcontroller * Clock Generator Provides CPU Rates up to 24 MHz * Programmable UART with 16-byte FIFOs at the Receiver Side (1), with a Maximum Rate * * * * * * * * * * * * * * *
of 921K Baud Programmable SPI Interface Full-speed USB Function Controller On-chip 2K Bytes SRAM (for Data) On-chip 2K Bytes Dual-port RAM for Segmentation and Reassembly of Packets Exchanged between the USB and the UART Interfaces 8K x 16-bit In-system SRAM for Program Code On-chip Bootstrap ROM for Program Uploading to the Internal Program SRAM, Either from the USB or the SPI One USB Control Endpoint Five USB Programmable Endpoints (up to 64 Bytes) with Double-buffered FIFOs for Back-to-back Transfers One 8-bit Timer/Counter One 16-bit Timer/Counter External and Internal Interrupt Sources Programmable Watchdog Timer Independent UART BRG Oscillator 64-pin TQFP Package 3.3V Operation
AVR(R)-based Bridge between Full-speed USB and Fast Serial Asynchronous Interfaces AT76C711
Figure 1. Pin Configuration
NC VCC GND PD7_INT1 PD6_INT0 PD5 PD4 PD3 PD2 PD1_SOUT PD0_SIN UXTALO UXTALI GND LFTU VCC TCK TP LC VCC GND DP DM SUSP GND VCC PM0 PM1 PC0 PC1 PC2 PC3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RST PB0_T0 PB1_T1 PB2_ICP PB3 PB4_SS PB5_MOSI PB6_MISO PB7_SCK VCC LFT GND XTAL1 XTAL2 TEST1 PSDIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P_RX P_TX GND VCC PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 VCC GND TEST2 ECK
Rev. 1643AS-10/00
Note: This is a summary document. A complete document is available on our web site at www.atmel.com.
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Description
The Atmel AT76C711 is a compound USB device designed to provide a high-speed USB interface to devices that need to communicate with a base station through fast serial links, like UARTs and IrDA interfaces. It is based on the AVR-enhanced RISC architecture and consists of a USB function interface with a devoted DMA controller for fast transfers of data between the endpoint FIFOs and the DPRAM, a 2 KB internal RAM, a Synchronous Peripheral Interface (SPI), a UART, supporting a maximum rate of 921K baud, an 8K x 16-bit in-system SRAM for microcode storage, which is loaded from the SPI controller, 2K bytes dual-port RAM (DPRAM) and a programmable DMA controller for packet transfers between the UART and the DPRAM, without microcontroller intervention. An IrDA controller is also provided, attached to a second UART module and is able to communicate with an IrDA transceiver with a maximum rate of 1.2 Mbps. A hardwired Device Firmware Upgrade (DFU) protocol handler is implemented for programming an external AT45BDxxx serial Flash during the production phase. An internal bootstrap ROM contains the executable program for uploading the application code from an external serial Flash to the on-chip program SRAM. Alternatively, microcode can be stored in the program SRAM using the slave program mode while the chip is in the reset state. The USB and peripheral device controller function should be implemented in the microcontroller's firmware. The device is suitable for applications where minimization of power dissipation is required, since there are no powerconsumable transactions with external parallel devices.
The USB H/W block consists of a USB transceiver, the SIE, endpoint controllers and an interface to the microcontroller. The USB H/W interfaces to the USB host at the packet level. The microcontroller firmware handles the higher-level USB protocol layers that are not processed by the USB H/W and in addition, it performs the peripheral control functions. A typical application of AT76C711 and its functional diagram are shown in Figures 2 and 3.
Applications
AT76C711 can be used in applications where peripherals supporting fast serial asynchronous or synchronous transfer of data have to communicate with a host or other peripherals through a high-speed serial link, like USB. Typical areas of AT76C711 usage are: * Connection of Network Interface Cards (NICs) to a host system * Wireless communications * Bridging of microcontrollers with different types of serial interfaces * USB to UART bridge * USB to IrDA bridge * IrDA to UART bridge * Packet adaptation of network protocol packets to USB requirements
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AT76C711
AT76C711
Block Diagram
Figure 1. Block Diagram
PROGRAM MEMORY CONTROLLER
Osc Clock Generator SRAM UART 1
IrDA 1.0 encdec
Timers AVR core WD
USB
address decoder
DPRAM
DMA controller
USART
SPI
Figure 2. Typical AT76C711 Application
USB
AT76C 711 Desktop System
UART
Network Adaptor RF Trsc RF Trsc Network Adaptor Printer
Figure 3. Functional Diagram
S/U# XTAL1 XTAL2 LFT
Debug ROM
16K x 16-bit SRAM
Clock Generator SRAM
IrDA 1.0 encdec UART 1 Timers WD
Data
Program Bus AVR Core
SUSP#
Interrupt Lines
DATA PORT REGISTERS - PORT DIRECTION REGISTERS DRIVERS/BUFFERS
PROGRAM MEMORY CONTROLLER
CLOCK Osc
2Kx8 Bits
DP DM
USB
RAM Address Bus & Bi-directional Data Bus
TDMAC, RDMAC, UINT
Address & Control Bus for AVR Register File Programming RST#
TXRDY# RXRDY# UINT
Address Decoder
/
SPI USART 0 UART Osc
DPRAM 2Kx8 Bits
DMA Controller
USCLK
LFTU
General Purpose I/O
PA0/SIN1/IrRx# PA1/SOUT1/IrTx PA2 PA3 PA4 PA5 PA6 PA7 PB0/T0 PB1/T1 PB2/INT0 PB3/INT1 PB4/SS# PB5/MOSI PB6/MISO PB7/SCK PC0-3 PD0/SIN0 PD1/SOUT0 PD2/RTS0# PD3/CTS0# PD4/DSR0# PD5/DTR0# PD6 PD7 UXTALO UXTALI
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Pin Summary
Pin Assignment Type: I V = Input = Power supply, ground O B = = Output Bi-directional OD = Output, open drain
Table 1. Pin Assignment in Alphabetical Order
Pin # 23 22 33 19 14 50 * 64 48 47 37 38 39 40 41 42 Signal DM DP ECK LC LFT LFTU GND NC P_IRX P_ITX PA0 PA1 PA2 PA3 PA4 PA5 I O B B B B B B Type B B I I I I V Pin # 44 2 3 4 5 6 7 8 9 29 30 31 32 54 55 56 57 Signal PA7 PB0_T0 PB1_T1 PB2_ICP PB3 PB4_SS PB5_MOSI PB6_MISO PB7_SCK PC0 PC1 PC2 PC3 PD0_SIN PD1_SOUT PD2 PD3 Type B B B B B B B B B B B B B B B B B Pin # 58 59 60 61 16 1 27, 28 24 17 15 34 18 ** 51 52 11 12 Signal PD4 PD5 PD6_INT0 PD7_INT1 PSDIN RST PM0, PM1 SUSP TCK TEST1 TEST2 TP VCC UXTALI UXTALO XTAL1 XTAL2 Type B B B B I I I O I I I I V I O I O
43 PA6 B Notes: 1. (*) GND: 12, 21, 25, 35, 46, 51, 62 2. (*) VCC: 10, 20, 24, 36, 45, 49, 63
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AT76C711
AT76C711
Table 2. Pin Assignment in Numerical Order
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Signal RST PB0_T0 PB1_T1 PB2_ICP PB3 PB4_SS PB5_MOSI PB6_MISO PB7_SCK VCC LFT GND XTAL1 XTAL2 TEST1 PSDIN TCK TP LC VCC GND DP Type I B B B B B B B B V I V I O I I I I I V V B Pin # 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Signal DM SUSP GND VCC PM0 PM1 PC0 PC1 PC2 PC3 ECK TEST2 GND VCC PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 Type B O V V I I B B B B I I V V B B B B B B B B Pin # 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Signal VCC GND P_ITX P_IRX VCC LFTU GND UXTALI UXTALO PD0_SIN PD1_SOUT PD2 PD3 PD4 PD5 PD6_INT0 PD7_INT1 GND VCC NC Type V V O I V I V I O B B B B B B B B V V V
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Signal Description
Table 3. Signal Description
Name Type Description
Program Memory Controller Signals PM0, PM1 PSDIN TP LC I I I I See Figure 4. Program Serial Data In: In slave program mode, this signal carries the serial program data that are samples with the positive edge of TCK. When RST is active (low), a high level of this signal, for at least two TCK pulses, forces the program address generator. Load Complete: A transition from low to high denotes the completion of program data transfer from the external device. The AVR will start executing instructions from the internal SRAM as soon as the RST goes high. A clock signal for sampling PSDIN input.
TCK Port Signals PA[0:7] PA[0:7]
I
B B
Port A, PB0 through PB7. 8-bit bi-directional port. Port B, PB0 through PB7. 8-bit bi-directional port. PB0, PB1, PB2, PB4 through PB7 are dual functions as shown below: Port Alternate Function PB0 Timer/Counter0 clock input PB1 Timer/Counter1 clock input PB2 (ICP) Input Capture Pin for Timer/Counter1 PB4 (SS#) SPI slave port select input PB5 (MOSI) SPI slave port select input PB6 (MISO) SPI master data in, slave data out PB7 (SCK) SPI master clock out, slave clock in Port C, PC0 through PC3. 4-bit output port. Port D, PD0 through PD7. 8-bit bi-directional I/O port. PD0, PD1 also serve as the data lines for the asynchronous serial port as listed below: Port Alternate Function PD0 (SIN) Serial Data In (I): This pin provides the serial receive data input to 16550 UART. The SIN signal will be a logic "1" during reset, idle (no data). During the local loopback mode, the SIN input pin is disabled and SOUT data is internally connected to the UART SIN input. PD1 (SOUT) Serial Data Out (O): This pin provides the serial transmit data from the 16550 UART. The SOUT signal will be a logic "1" during reset, idle (no data). PD6 (INT0) External Interrupt0 source PD7 (INT1) External Interrupt1 source
PC[0:3] PD[0:7]
B B
USB Serial Interface DP DM SUSP B B O Upstream Plus USB I/O. DP and DM form the differential signal pin pair connected to the host controller or an upstream hub. Upstream Minus USB I/O Suspend. This output pin is deactivated (high) during normal operation. It is used to signal the host microcontroller that AT76C711 has received USB suspend signaling. This pin will stay asserted while AT76C722 is in the suspend mode. This pin is deactivated whenever a USB resume signaling is detected on DP and DM.
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AT76C711
AT76C711
Table 3. Signal Description (Continued)
Name Test Signals TEST1 TEST2 ECK IrDA Interface P_ITX O Infrared Data Out: This pin provides the serial transmit data from the IrDA codec to external IR Data Transceiver. This function is activated when the IrDA interface is enabled from PERIPHEN I/O Register. Infrared Data In: This pin provides the serial receive data input from the external IR Data Transceiver to IrDA codec. This function is activated when the IrDA interface is enabled from PERIPHEN I/O Register. I I I Test signal for clocks (used in production phase only - normally tied to high) Test signal for monitoring internal signal levels using the four data ports (used in production phase only - normally tied to high) Clock pulse for activating various test modes when TEST2 is active Type Description
P_IRX
I
Other Signals GND VCC RST XTAL1 XTAL2 LFT UXTALI UXTALO V V I I O I I O Ground 3.3V power supply Reset. A low on this pin for two machine cycles, while the oscillator is running, resets the device. Oscillator Input. Input to the inverting oscillating amplifier. A 12 MHz clock oscillator should be applied. Oscillator Output. Output of the inverting oscillator amplifier. Master clock PLL LFT pin UART BRG Oscillator Input. Input to the UART oscillator amplifier. UART BRG Oscillator Output. Output of the UART oscillator amplifier.
LFTU I UART clock PLL LFT pin Note: Any signal with a # indicates that it is an active low signal.
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1643AS-10/00/xM
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