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AWT921
Integrated High Power Amp 900 MHz
PRELIMINARY DATA SHEET - Rev 1.2 FEATURES
* * * * * * High output power levels High Efficiency True Surface Mount Package with Integrated Heat Slug Internal Bias Circuit Requiring Nominal Input Voltages +10% Low Cost Off Chip Output Matching Circuit Allows Application Optimization
S11 SSOP-28 28 Pin Wide Body w/ Heat Slug PRODUCT DESCRIPTION
The AWT921 is a monolithic amplifier for use in communication systems that require high gain and output intercept point. This device has been
Vd1
specifically designed for multi carrier and micro cell base station applications .
Vd2
Vd3
Bypass
Bypass
Bypass
RFC
RFC
RFC
RFin
RFout M1 M2 M3
Bias Network Vss On Chip Rref
Vg3
Vg1
Vg2
Vref
Vdd
Figure 1: Block Diagram
03/2003
AWT921
Pin 1 GND V GS1 V DD RFIN VD1 VD1 GND GND VD2 V D2 VREF V SS VGS2 GND Pin 14 Pin 28 GND N/C N/C VD3 V D3 VD3 V D3 VD3 VD3 VD3 VD3 V GS3 VGS3 GND Pin 15
Figure 1: Pin Layout
Table 1: Pin Description
PIN NAME DESCRIPTION
1,14,15,28, slug 2 3 4 5,6 7,8 9,10 11 12 13 16,17 18-25 26,27
GND VGS1 VDD RF IN VD1 GND VD2 V REF V SS V GS2 V GS3 VD3 N/C
AC and RF Ground First Stage Gate terminal Positive Supply of Bias Circuit (+5V) RF Input First Stage drain supply First Stage Source ground Second Stage drain supply Bias control Pin Negative Supply for Bias Circuit (-3V) Second Stage Gate terminal Third Stage Gate terminal Third Stage drain supply & RF out Not Connected
Procedure for Amplifier Operation and Test 1) Slug must be thermally and electrically connected to obtain rated performance. 2) The VSS Voltage should be applied first to the amplifier prior to VD1, VD2, or VD3 voltages. 2
3) The Bias Pins VDD and VREF may be applied with no VSS voltage present. 4) Always follow ESD precautions when handling these devices.
PRELIMINARY DATA SHEET- Rev 1.2 03/2003
AWT921
ELECTRICAL CHARACTERISTICS
Table 2: Electrical Specifications: (1)
(Pin +12 dBm, fo = 925-960 MHz, V DS1 = V DS2 = V DS3 = 8.5V, V SS = - 3V,V REF=+5V,V DD=+5V,Tc=25C, 50 System(2)
PARAMETER Frequency Power Output Power Added Efficiency Gain @POUT=+37.5 dBm Harmonics@37.5 dBm POUT 2nd 3rd Stability: -60 dBc all spurious outputs relative to desired signal
SYMBOL fo POUT
EFF
MIN 925 26
TYP +39 40 28 30 35
MAX 960 -
UNIT MHz dBm % dB
PG
dBc VSWR load, all phase angles, mA mA mA
-
-
3:1
-
Bias Supply Currents
I SS I REF I DD IDQ1 IDQ2 IDQ3 PG
-
8 1.2 8 100 250 200
-
Quiescent Currents Input Return Loss Gain Flatness vs. Frequency @ POUT=+37.5 dBm @ POUT=+30 dBm Thermal Resistance3
-
12 0.5 0.5 4.5
-
dB dB dB C/W
Notes: 1. As measured in ANADIGICS test fixture, see application section 2. 50 Measurement system after off chip matching circuit, input terminated in 50 3. Thermal resistance for junction to bottom of slug. Qjc= (Tj-Tc)/((ID1+ID2 +ID3)*VSUP - POUT )
PRELIMINARY DATA SHEET - Rev 1.2 03/2003
3
AWT921 Table 3: Absolute Maximum Ratings
PIN 2 3 4,5 NAME V DD RF IN V D1 MAX RATING +7V DC +20 dBm +10 VDC PIN 11 12 18,19,20,21,22,23,24,25 NAME VREF V SS MAX RATING +7 VDC -7 VDC +10 VDC
VD3
8,9
VD2
+10 VDC
Stresses in excess of the absolute ratings may cause permanent damage. Functional operation is not implied under these conditions. Exposure to absolute ratings for extended periods of time may adversely affect reliability. Operating Temperature: -30 to + 85o C Storage Temperature: -55 to + 100o C
PERFORMANCE DATA
Conditions unless otherwise stated (Pin +12 dBm, fo = 925-960 MHz, VDS1 = VDS2 = VDS3 = 8.5V, VSS = - 3V, VREF = +5V, VDD =+ 5 V, Tc=25C, 50 W system (2)) Figure 2: POUT & Eff vs. Pin
40 Pout (dBm) 38 36 34 32 30 0 2 4 6 8 Pin (dBm) 10 12 14 100 90 80 70 60 50 40 30 20 10 0
Figure 3: POUT & Eff vs. Frequency
43 42 41 40 39 38 37 36 35 920 930 940 950 Freq (MHz) 960 60 40 30 20 10 0 Padd Eff (%) 50
Padd Eff (%)
Pout Eff
Pout (dBm)
Pout Eff
Figure 4: POUT vs. Supply Voltage
41 40 Pout (dBm) 39 38 37 36 35 5 6 7 8 9 Vsup (V) 10 11 Pout
Figure 5: Idq3 vs. Vdd
120 100 Idq3 (mA) 80 60 40 20 0 0 2 4 6 Vdd (Volts) 8
Notes: 1: As measured in ANADIGICS test fixture, see application section 2: 50 Measurement system after off chip matching circuit, input terminated in 50
4
PRELIMINARY DATA SHEET- Rev 1.2 03/2003
AWT921 Figure 6: Idq vs. Vref
500
Figure 7: Idq vs. Vss
450 400 Idq3 (mA)
600 500 Idq3 (mA) 400 300 200 100 0 0 2 4 6 Vref (Volts) 8 Rref=1.5 K Rref=3 K Rref=6 K
350 300 250 200 150 100 -7 -6 -5 -4 Vss (Volts) -3 -2
Bias Ckt Gain vs Vref
Bias Ckt Current Gain 120 115
Figure 8: Bias Ckt Gain vs. Vref
400 350 Iq3 (mA) 300 250 200 150
Figure 9: Iq3 & Iref vs. Temperature
1.3 1.25 1.2 1.15 1.1 1.05 Iref (mA) Iq3 Iref
110 105 100 95 90 2 3 4 5 6 Vref (Volts) 7 8
Idq3/Iref
100 1 -40 -20 0 20 40 60 80 100 Temperature (C)
Figure 10: P Pout,PG,&OUT & Eff vs. Temperature Eff vs Temperature
Pout (dBm) & SS Gain (dB)
TX30D 8672-2
40 43 39 41 38 37 39 36 37 35 34 35 33 32 33 -40 -20 0 20 40 60 80 100 Temperature (C)
Figure 11: S22 Reverse Reflection Impedance Output Impedance as seen by VDS3
1 .5 3 2
TRACE MEMORY DISK OPERATIONS CHANNEL 4
4
Eff (%)
Pout Eff
0
.2
5
SAVE MEMORY TO HARD DISK SAVE MEMORY TO FLOPPY DISK
1 .2 .5 1 2 5
SS PG
-.2 -5
RECALL MEMORY FROM HARD DISK RECALL MEM0ORY FROM FLOPPY DISK
-.5 -1 -2
PRESS TO SELECT
0.050000000 - 2.800000000 GHz
PRELIMINARY DATA SHEET - Rev 1.2 03/2003
5
AWT921 Figure 12: S11 Reverse Reflection Impedance Impedance as seen by VDS1
S11 REVERSE REFLECTION IMPEDANCE 1 .5 2
1 CH 4 S11 REFERENCE PLANE 9.0821 cm MARKER 1 0.957500000 G H z 7.074 131.906 j MARKER TO MAX MARKER TO MIN .2 .5 2 1 2 5 2 0.098125000 G H z 36.919 -13.501 j 3 1.920000000 G H z 11.446 -111.641 j 4 2.800000000 G H z 3.133 -24.550 j MARKER READOUT FUNCTIONS
Figure 13: S11 Reverse Reflection Impedance Impedance as seen by VDS2
S11 REVERSE REFLECTION IMPEDANCE
1 .5 2
1
CH 4 -
S11
REFERENCE PLANE 9.0821 cm MARKER 1 0.957500000 GHz 7.659 161.181 j 5 MARKER TO MAX MARKER TO MIN 2 0.098125000 GHz 37.237 -11.817 j 3 1.920000000 GHz 13.308 -171.126 j 4 2.800000000 GHz 4.466 -60.044 j MARKER READOUT FUNCTIONS
.2
5
.2
0
0
.2
.5
2
1
2
5
-.2
4 3
-5
-.2
3
-5
-.5 -1
-2
-.5 -1
4
-2
0.050000000 -2.800000000 GHz
0.050000000 - .800000000 GHz 2
6
PRELIMINARY DATA SHEET- Rev 1.2 03/2003
AWT921 Figure 14: 925 - 960 MHz Test Circuit Schematic
F2 C1 L2
F1 C5
L3
AWT921S11
C4 9 10 C6
RF
IN
VD2 VD1 RFIN GND VD3
5 6 4 7 8
25 24 23 22 21 20 19 18 C17 C13 L1
RFOUT
RREF VD2 11 3 12 C8 VD1 SLUG 1 14 15 28 VREF VD D VSS VGS1 VGS2 VGS3
C7
GND
2 13 16 17 C10
R1 C11 R2 C12 F3 C15 F4 C14
VD D/ VREF
C9
VSS C16
VGS3
VD3
GND
Table 4: Pin Designations
DESIGNATION R1 R2 RREF C1, C5, C16 C4, C15, C19 C6, C17 C7, C8, C9, C12 C10, C11 C13 C14 L1 L2 L3 F1, F2, F3, F4, VALUE 7500 2.2 K 1.8 K 2.2 F 33 pF 47 pF 0.01 F 2700 pF 11 pF 4700 pF 8 nH Colicraft, A03T 12 nH 6 nH Ferrite 47 @100 MHz, 1A Rating Taiyo Yuden, BK2125HS470
PRELIMINARY DATA SHEET - Rev 1.2 03/2003
7
AWT921
Figure 15: Test Circuit Top Layer Pattern
Notes: Board material -6 layer FR4 1) 1 oz. Copper 2) 14 mil core layers 3) Gerber Files available
8
PRELIMINARY DATA SHEET- Rev 1.2 03/2003
AWT921 Table 5: 925 - 960 MHz GSM Test Circuit Component Listing
DESIGNATION R1 R2 RREF C1,C5,C16 C4,C15,C19 C6,C17 C7,C8,C9,C12 C10,C11 C13 C14 L1 L2 L3 VALUE 7500 2.2 K 1.8 K 2.2 uF 33 pF 47 pF 0.01 uF 2700 pF 11 pF 4700 pF 8 nH 12 nH 6.8 nH Ferrite 47 @ 100 MHz, 1A Rating MANUFACTURE Panasonic Panasonic Panasonic Panasonic Murata Murata Murata Murata American Technical Ceramics Murata Coilcraft Coilcraft Coilcraft MANUFACTURE PART # ERJ-36SYJ752V ERJ-36SYJ222V ERJ-36SYJ182V ECS-H1AY225R GRM36COG330J50 GRM36COG470J50 GRM36X7R103K16 GRM36X7R272K50 ATC100A110JW150X GRM36X7R472K25 A03T 0805CS060XMBC 0805CS120XMBC WEB ADDRESS PHONE CONTACT # 201-348-5232 201-348-5232 201-348-5232 201-348-5232 1-800-237-1431 1-800-237-1431 1-800-237-1431 1-800-237-1431 (516) 547-5700 1-800-237-1431 1-800-322-2645 1-800-322-2645 1-800-322-2645
www.panasonic.com www.panasonic.com www.panasonic.com www.panasonic.com www.murata.com www.murata.com www.murata.com www.murata.com www.atc-cap. com www.murata.com www.coilcraft.com www.coilcraft.com www.coilcraft.com
F1,F2,F3,F4
Taiyo Yuden
BK2125HS470
www.t-yuden.com
800-348-2496
PRELIMINARY DATA SHEET - Rev 1.2 03/2003
9
AWT921
PACKAGE OUTLINE
D T L LE C
HEAT SINK
SLUG S E
h
a A A2 A1
e
Figure 16: Package Outline Drawing
INCHES SYMBOL A A1 A2 B C D E e H h L LE a S T MIN 0.087 0.000 0.087 0.008 0.007 0.400 0.292 0.025 0.410 0.018 0.034 0.84 0 0.139 0.349 8 0.141 0.351 MAX 0.093 0.004 0.089 0.012 0.009 0.408 0.296 BSC 0.418 0.024 0.038 MILLIMETERS MIN 2.21 0.00 2.21 0.36 0.18 10.16 7.42 0.64 10.41 0.48 0.86 1.37 0 3.54 8.86 8 3.55 8.92 MAX 2.36 0.10 2.25 0.46 0.25 10.36 7.52 BSC 40.62 0.61 0.97
Notes: 1. Controlling dimensions : inches. 2. Dimension "d" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions and gate burrs shall not exceed 0.006 (0.16mm). 3. Dimension "e" does not include inter-lead or protrusions. Inter-lead flash and protrusions shall not exceed 0.010 (0.25mm) per side. 4. Maximum lead twist/skew to be 0.002 (0.05mm). 5. Mold flash shall not extend more than 0.010 (0.25mm) on any edge of heat slug.
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PRELIMINARY DATA SHEET- Rev 1.2 03/2003
AWT921
NOTES
PRELIMINARY DATA SHEET - Rev 1.2 03/2003
11
AWT921
ORDERING INFORMATION
ORDER NUMBER PACKAGE DESCRIPTION S11
COMPONENT PACKAGING 28 Pin Body with Heat Slug
AWT921S11
ANADIGICS, Inc.
141 Mount Bethel Road Warren, New Jersey 07059, U.S.A. Tel: +1 (908) 668-5000 Fax: +1 (908) 668-5132 URL: http://www.anadigics.com E-mail: Mktg@anadigics.com IMPORTANT NOTICE
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to change prior to a product's formal introduction. Information in Data Sheets have been carefully checked and are assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers to verify that the information they are using is current before placing orders.
WARNING
ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS product in any such application without written consent is prohibited.
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PRELIMINARY DATA SHEET - Rev 1.2 03/2003

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