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CDB4228A
Evaluation Board for CS4228A
Features
l Demonstrates
Description
The CDB4228A evaluation board is an excellent means for quickly evaluating the CS4228A 2 in, 6 out, 24-bit, 96kHz capable CODEC. Evaluation requires an analog signal source and analyzer, a digital signal source and analyzer, a PC compatible computer for control, and a power supply. System timing can be supplied by the CS8414 digital audio receiver I.C., or an onboard oscillator. Control is provided by PC software. The evaluation board may also be configured to accept external timing, data, and control signals for operation in a user application during system development. ORDERING INFORMATION CDB4228A Evaluation Board
recommended layout and grounding arrangements l CS8414 receives AES/EBU, S/PDIF & EIAJ340 compatible digital audio l CS8404 transmits AES/EBU, S/PDIF & EIAJ340 compatible digital audio l PC software provides easy to use board and device control l Interfaces for external serial audio I/O and microprocessor control
PC Control Port CS8414 Digital Audio Receiver CS8404 Digital Audio Transmitter Digital Audio Port PLD
External Control Port
SCK SDA/CDIN CDOUT CS
MCLK LRCLK SCLK SDIN1 SDIN2 SDIN3 SDOUT
Analog Outputs CS4228A
Oscillator
Analog Inputs
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 2000 (All Rights Reserved)
OCT '00 DS511DB1 1
CDB4228A
TABLE OF CONTENTS
1. CDB4228A SYSTEM OVERVIEW .................................................................. 4 2. CS4228A CODEC ........................................................................................... 4 3. BOARD CONTROL ........................................................................................ 4 3.1 Graphical User Interface ...................................................................... 4 3.2 External Control Interface .................................................................... 4 4. DIGITAL AUDIO I/O ........................................................................................ 4 4.1 Receiver ............................................................................................... 4 4.2 Transmitter ........................................................................................... 4 4.3 Digital Audio Port ................................................................................. 5 4.4 Master Clock ........................................................................................ 5 4.5 Serial Data Format ............................................................................... 5 5. ANALOG INPUT ............................................................................................. 5 6. ANALOG OUTPUT ......................................................................................... 5 7. EXTERNAL CONTROL MODE ...................................................................... 5 7.1 Serial Mode .......................................................................................... 6 7.2 MCLK Multiplexer ................................................................................ 6 7.3 Transmitter Clock Divider .................................................................... 6 8. POWER SUPPLY CIRCUITRY ....................................................................... 6 9. GROUNDING AND POWER SUPPLY DECOUPLING .................................. 6 10. BILL OF MATERIALS .............................................................................. 31
LIST OF FIGURES
Figure 1. CDB4228A Top Level Schematic ......................................................... 9 Figure 2. Analog Input Filter .............................................................................. 10 Figure 3. External Control ................................................................................. 11 Figure 4. Digital Audio Port ............................................................................... 12 Figure 5. Analog Output Filter 1 ........................................................................ 13 Figure 6. Analog Output Filter 2 ........................................................................ 14 Figure 7. Analog Output Filter 3 ........................................................................ 15 Figure 8. Analog Output Filter 4 ........................................................................ 16 Figure 9. Analog Output Filter 5 ........................................................................ 17 Figure 10.Analog Output Filter 6 ........................................................................ 18 Figure 11.Low Cost Analog Output Filter ........................................................... 19 Figure 12.Control Port Interface ......................................................................... 20 Figure 13.Programmable Logic .......................................................................... 21
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales/cfm
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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CDB4228A
Figure 14.Power Supply ..................................................................................... 22 Figure 15.Master Clock Circuit ........................................................................... 23 Figure 16.CS8414 Digital Audio Receiver .......................................................... 24 Figure 17.CS8404 Digital Audio Transmitter ...................................................... 25 Figure 18.Silkscreen Top ................................................................................... 26 Figure 19.Top Side ............................................................................................. 27 Figure 20.Level 2 Ground Plane ........................................................................ 28 Figure 21.Level 3 ............................................................................................... 29 Figure 22.Bottom Side ....................................................................................... 30
LIST OF TABLES
Table 1. Board Level Serial Mode Settings ............................................................. 6 Table 2. System Connections ................................................................................. 7 Table 3. MCLK Multiplexer Settings ........................................................................ 7 Table 4. CDB4228A Jumper and Switch Settings ................................................... 8 Table 5. Transmitter Clock Divider Settings ............................................................ 8 Table 6. Bill of Materials ........................................................................................ 31
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CDB4228A
1. CDB4228A SYSTEM OVERVIEW
The CDB4228A evaluation board is an excellent means of quickly evaluating the CS4228A. Input and output analog interfaces are provided as well as a CS8414 digital interface receiver and CS8404 digital interface transmitter that provide an easy interface to digital audio test equipment. The evaluation board also allows the user to interface external systems' digital audio clocks and data through the digital audio port (DAP) 20-pin header. An external two wire or SPI control interface is also provided through a 10-pin header for easy system development using the evaluation board. The CDB4228A schematic has been partitioned into 17 schematics shown in Figures 1 through 17. Each partitioned schematic is represented in the top level schematic shown in Figure 1.
4. DIGITAL AUDIO I/O 4.1 Receiver
Digital-to-Analog (DAC) performance can be quickly tested by connecting a S/PDIF audio source to the CS8414 receiver. The S/PDIF input can be either optical or coax, see Figure 16. However, both inputs cannot be driven simultaneously. The interface for the CS8414 includes a serial bit clock, serial data, left-right clock (FSYNC), and a 256 Fs master clock. The bit clock and left-right clock signals are bidirectional, and as a pair can be selected to supply these signals to the system, or can be selected as inputs from the CS4228A or DAP. The receiver data output can be simultaneously connected to the SDIN1, SDIN2, and SDIN3 inputs on the CS4228A. The receiver can be powered down to prevent asynchronous clock interference by depressing all three rocker switches to the OFF position on the RX PWR DIP switch S1. The operation of the CS8414 and a discussion of the digital audio interface are included in the CS8414 data sheet.
2. CS4228A CODEC
A complete description of the CS4228A CODEC is included in the CS4228A data sheet.
3. BOARD CONTROL 3.1 Graphical User Interface
The CDB4228A is shipped with Windows based graphical user interface (GUI) software for interfacing with the CS4228A control port via a PC parallel port connected to the DB25 connector, J15. Parallel port control is selected by placing the CONTROL switch S2 in the PP position. The software can be used to communicate with the CS4228A in two wire or SPI mode by selecting the MODE switch S4. Further documentation for the software is available on the distribution diskette in the plain text format file, README.TXT.
4.2
Transmitter
3.2
External Control Interface
The evaluation board can also be controlled via a external host such as a microcontroller connected to the EXTRNL CONTROL port JP9 by placing the CONTROL switch S2 in the EXTRNL position. For more information, see section 7.
4
The analog-to-digital converter performance can be quickly evaluated by connecting an analog generator to the left and right inputs, and connecting the S/PDIF optical or coaxial output to audio test equipment. The CS8404 digital interface transmitter is connected to the CODEC serial data output SDOUT, and the system bit clock, left-right clock and master clock as shown in Figure 17. The transmitter and CS4228A share several serial modes, but not all modes of each device are supported. SMODE 4 and 5 will not work properly with the transmitter: The data will be right-shifted by 8 bits. The transmitter must always be supplied a 128 Fs master clock, which is supplied by clock dividers within the PLD. The clock divider source is the same as that selected for the CS4228A MCLK. The
DS511DB1
CDB4228A
PLD can support division ratios of 1, 2, 3, and 4 to support MCLK frequencies of 128, 256, 384, and 512 Fs respectively. The proper division ratio can be selected in the GUI in PP mode, or S5 in EXTRNL mode.
4.5
Serial Data Format
4.3
Digital Audio Port
The digital audio port (DAP) provides an interface to the CODEC serial audio clocks and data. The DAP can be used to interface to external compressed audio decoder systems such as the CS492x or CS49300 families of digital signal processors for ease in evaluating complete audio system solutions. MCLK, LRCLK, and SCLK are bidirectional signals. The direction of these signals can be controlled by the GUI in PP mode, or S5 switches in EXTRNL mode. The direction of SCLK and LRCLK is always selected as a pair.
The serial data format for the evaluation board is set by the GUI in PP mode or by S5 switches in EXTRNL mode. Not all serial modes of each device are supported. SMODE 4 and 5 are not supported by the transmitter. Two serial formats are common to all three devices; I2S, 16 to 24 bits/sample, and right justified, 16 bits/sample. Each of the three SDIN inputs to the CS4228A comes from a multiplexer within the PLD and can be individually sourced from the CS8414 receiver or from the DAP. The multiplexer can be disabled and jumpers JP3-JP5 can be used to select the source.
5. ANALOG INPUT
Analog inputs to the CDB4228A are single ended, with a full scale of 2V RMS (5.66V p-p). The inputs are AC coupled, then converted to a differential signal with a 2.3V common mode voltage derived from the 5V supply. The differential signal is then antialiased with a passive filter, Fc = 200 kHz, before being sent to the ADC as shown in Figure 2.
4.4
Master Clock
Master clock (MCLK) for the evaluation board can come from one of three sources: the on-board CS8414 receiver, the on-board oscillator, or an external source via the DAP port. One of the three sources is selected by multiplexer U2 which is controlled via the GUI in PP mode or the S5 switches in EXTRNL mode. The on-board oscillator provided with the board is 12.288 MHz for evaluation at 256 Fs at a 48kHz sample rate, or 128 Fs at a 96kHz sample rate. The oscillator is socketed for easy replacement and can be powered down with header JP1 to prevent asynchronous clock interference when the S/PDIF receiver is being used. The MCLK multiplexer adds a small amount of clock jitter to the MCLK signal, which has a very slight effect on converter performance. The system can be evaluated without the buffer by installing a 3x2 pin header in JP2, and removing R3. A 2-socket shorting jumper is then installed in JP2 to select the system MCLK source. Refer to Figure 15.
6. ANALOG OUTPUT
The analog outputs from the DACs are buffered with a 2-pole active butterworth filter, Fc = 50 kHz. The filter has a DC gain of 1.56V/V for a 2V RMS full scale output. For a lower cost alternative, the outputs can be filtered with a single pole passive filter with Fc = 50 kHz and RL > 10k ohms as shown in Figure 11. The outputs also have a mute circuit that is controlled by the MUTEC pin on the CS4228A.
7. EXTERNAL CONTROL MODE
The CDB4228A system can be controlled without using a PC by connecting a host controller to the EXTRNL CTRL port. All board functions set by the parallel port are available to the user on the 10 position DIP switch, S5. There are three parameters on S5; board level serial mode, MCLK multiplexing, and S/PDIF transmitter clock divider control. On S5, an open switch denotes a one for that bit position.
5
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CDB4228A
7.1 Serial Mode
CS4228A MCLK multiplexer. The clock divider ratios are shown in Table 5.
The SMODE[4..0] switches on S5 set the serial mode and the LRCLK/SCLK direction of all other devices in the system except the CS4228A. The devices controlled by SMODE include the CS8414, the CS8404, and the DAP. SMODE settings on S5 are only active when in EXTRNL mode. The SMODE mapping is shown in Table 1. Care must be taken when setting up SMODE so that the LRCLK/SCLK direction corresponds with the CS4228A master/slave setting to avoid bus contention. The CS4228A serial port master/slave mode is set in the Serial Port Mode register 0x0D.
8. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by four binding posts (+5V, GND, +12V, -12V). The +5V input supplies power to the analog and digital +5 Volt circuitry and to a 3.3V voltage regulator. There is a power supply header for selecting either 5V or 3.3V supplies to the CS4228A VL pin. A second header selects the interface voltage for the programmable logic device that supplies the control port interface. The VL setting should always be equal or greater than the PLD PWR to prevent noise due to charge injection.
7.2
MCLK Multiplexer
The board level MCLK source is controlled by the MCLK-SEL[2..0] switches on S5 when in EXTRNL mode. The multiplexer settings are shown in Table 3. The MCLK source should be the CS8414 whenever the S/PDIF data source is used.
9. GROUNDING AND POWER SUPPLY DECOUPLING
The CS4228A requires careful attention to power supply and grounding arrangements to optimize performance. The decoupling capacitors are located as close to the CS4228A as possible. Extensive use of ground plane fill on both the analog and digital sections of the evaluation board yields large reductions in radiated noise.
7.3
Transmitter Clock Divider
The TX_MCLK[1..0] switches on S5 control the clock divider for the CS8404 S/PDIF transmitter when in EXTRNL mode. The transmitter must be supplied a 128 Fs MCLK which is sourced from the
SMODE [4..0] 0 1 2 3 4 5 6 7 8 9 10 - 31 Board Level Serial Mode I2S, TX Master, 64Fs SCLK only I2S, CODEC Master I2S, DAP Master Right Justified, TX Master, 16 bits Right Justified, CODEC master Right Justified, DAP master Left Justified, CODEC master Left Justified, DAP master Left Justified, test mode Left Justified, test mode I2S, CODEC master
CS8414 MODE Output Input Input Output Input Input Input Input Output Input Input
CS8404 MODE Input Input Input Input OFF OFF OFF OFF Input Output Input
DAP CLK MODE Input Input Output Input Input Output Input Output Input Input Input
CS8414 M[3..0] 2 3 3 5 15 15 15 15 0 1 3
CS8404 M[2..0] 4 4 4 5 4 4 1 1 1 0 4
Table 1. Board Level Serial Mode Settings
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CDB4228A
CONNECTOR +5V +12V, -12V GND J9, SPDIF IN U9, SPDIF IN LEFT RIGHT DAC1 - DAC6 J7, SPDIF OUT U5, SPDIF OUT Parallel Port EXT CTRL DAP PGM INPUT/OUTPUT Input Input Input Input Input Input Input Output Output Output Input/Output Input/Output Input/Output Input/Output + 5 Volt power + 12/-12V Volt power for the op-amps Ground connection from power supply Digital audio interface input via coax Digital audio interface input via optical Analog audio input, 2V RMS (5.65Vp-p) full scale Analog audio input, 2V RMS (5.65Vp-p) full scale Analog audio output, 2V RMS (5.65Vp-p) full scale Digital audio interface output via coax Digital audio interface output via optical Parallel connection to PC for two wire(R) or SPI control port signals I/O for two wire(R) or SPI control port signals I/O for serial audio clocks and data Programming header for PLD Table 2. System Connections MCLK-SEL [2..0] 0 1 2 3 4 5 6 7 MCLK Source Oscillator Oscillator S/PDIF Receiver S/PDIF Receiver DAP None None None Table 3. MCLK Multiplexer Settings DAP MCLK DIR OFF Output OFF Output Input OFF OFF OFF SIGNAL PRESENT
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CDB4228A
JUMPER VD VL RX PWR OSC PWR S1 S2 S3 S4 S5
PURPOSE Selects the supply voltage for the CS4228A digital core. Selects the supply voltage for the CS4228A logic interface pins Selects the supply voltage for the Altera PLD I/O pins. Connects power to the oscillator Connects power and clocks to the CS8414 Selects control port interface Selects the CS4228A SDIN1,2,3 source in EXTRNL control mode Selects the control port data format Selects serial mode and DAP clock directions in EXTRNL control mode. Optional pin header select for MCLK
POSITION 3.3V* 5V 3.3V 5V* 3.3V 5V* ON* OFF ON* OFF PP* EXTRNL SPDIF* DAP Two wire* SPI CLOSED* OPEN
FUNCTION SELECTED
Power and LRCLK and SCLK are connected Power, LRCLK, and SCLK are disconnected Parallel port control enabled. EXTRNL CTRL header enabled CS8414 data is routed to SDIN1,2,3 SDIN1,2,3 source is the DAP Two wire control format SPI control format See external control mode section for more information.
JP2
OSC MCLK source is onboard oscillator. SPDIF MCLK MCLK source is CS8414 receiver MUX MCLK MCLK source is multiplexer
Notes: *Default setting from factory Table 4. CDB4228A Jumper and Switch Settings
TX-MCLK [1..0] 0 *1 2 3
MCLK Division Ratio 1:1 1:2 1:3 1:4
System MCLK Rate 128 256 384 512
Table 5. Transmitter Clock Divider Settings
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2
2
DS511DB1
J1 PHONO JACK RA 1 A/D Input AINL GND J2 PHONO JACK RA 1 AINR A/D Input OUTLOUTL+ OUTROUTR+ AINLAINL+ AINRAINR+ GND VL TP3 TP5 TP7 TP9 TP11 TP12 TP14
SPDIF Out MCLK SCLK LRCLK SDIN M[2..0] RESETn TX_U TX_C TX_CBL SPDIF TX TX_MCLK SCLK LRCLK SDOUT TX_M[2..0] MRESETn TX_U TX_C TX_CBL
SPDIF In MCLK SCLK FSYNC SDOUT M[3..0] RXPWR RX_C RX_U RX_CBL RX_ERF RX_VERF SPDIF RX SPDIF_SDOUT DAP_SDIN3 SPDIF_MCLK SCLK LRCLK SPDIF_SDOUT RX_M[3..0] RXPWR RX_C RX_U RX_CBL RX_ERF RX_VERF SPDIF_SDOUT DAP_SDIN1
JP3 1 3 2 4 AOUT1 SDIN1
Output Buffer1 IN MUTE Out1
HEADER 2X2 JP4 SPDIF_SDOUT DAP_SDIN2
Output Buffer2 1 3 2 4 SDIN2 AOUT2 IN MUTE Out2 1 3 2 4 SDIN3 AOUT3 Output Buffer3 IN MUTE Out3
HEADER 2X2 JP5
HEADER 2X2
U3 CLKIN SCLK LRCLK SDIN1 SDIN2 SDIN3 SDOUT R98 R99 R100 R101 R102 R103 150 150 150 150 150 150 10 5 6 3 2 1 4 11 12 13 TP23 TP25 2 4 C9 47nf MRESETn MUTEC 14 15 9 8 7 CLKIN SCLK LRCLK SDIN1 SDIN2 SDIN3 SDOUT SCL/CCLK SDA/CDIN AD0/CS RESET MUTEC VL VD DGND CS4228A-KS C13 47nf GND GND Control Switches X_CTRL SDIN_CTRL CTRL_MODE SDOUT MODE_CTRL[9..0] X_CTRL SDIN_CTRL CTRL_MODE SDOUT_LOAD MODE_CTRL[9..0] CONTROL J3 TERMINAL BLUE 16 AINR+ 17 AINR20 AINL+ 19 AINLFILT AOUT1 AOUT2 AOUT3 AOUT4 AOUT5 AOUT6 18 23 24 25 26 27 28 AINR+ AINRAINL+ AINLFILT AOUT1 AOUT2 AOUT3 AOUT4 AOUT5 AOUT6 TP15 TP17 TP19 TP21 TP22 TP24 TP4 TP6 TP8 TP10 TP13 AOUT4
Output Buffer4 IN MUTE Out4 Output Buffer5 AOUT5 IN MUTE Out5
+3.3V
VD VCC
JP6 1 3 2 4
R5 R6 R7
10k 3.16k 10k
+5V
HEADER 2X2
+ C5
10uf C6 47nf GND
VLOGIC SEL
TP16 TP18 TP20
SCL SDA/CDIN AD0/CS
GND
+3.3V
VD VCC
JP11 1 3
+5V
+ C7
10uf
TP26
VA AGND
21 22
VA TP27 C12 47nf
Output Buffer6 AOUT6 MUTE IN MUTE Out6
+ C8
10uf
HEADER 2X2
VD SEL
+12V
Host Interface PPRESETn 1 RESETn D[7..0] A[1..0] STROBEn STATUS[3..0] ACKn D[7..0] A[1..0] STROBEn STATUS[3..0] ACKn TX_CBL TX_C TX_U RX_CBL RX_C RX_U RXPWR RX_VERF RX_ERF MRESETn Power +12VBUS GND -12VBUS +5VBUS +12VBUS GND -12VBUS +5VBUS Power J6 TERMINAL RED PPRESETn X_RESETn MRESETn MUTEC MUTE PPRESETn X_RESETn MRESETn MUTEC MUTE
Programmable Logic D[7..0] A[1..0] STROBEn STATUS[3..0] ACKn TX_CBL TX_C TX_U RX_CBL RX_C RX_U RXPWR RX_VERF RX_ERF MRESETn SCL SDA/CDOUT CDIN AD0/CS SCLK LRCLK SDIN[3..1] DAP_SDIN[3..1] SPDIF_SDOUT SDIN_CTRL TX_M[2..0] RX_M[3..0] DAP_CTRL REFCLK_CTRL[3..0] X_CTRL CTRL_MODE CLKIN TX_MCLK MODE_CTRL[9..0] SCL SDA/CDIN MUTEC AD0/CS SCLK LRCLK SDIN[3..1] DAP_SDIN[3..1] SPDIF_SDOUT SDIN_CTRL TX_M[2..0] RX_M[3..0] DAP_CTRL REFCLK_CTRL[3..0] X_CTRL CTRL_MODE CLKIN TX_MCLK MODE_CTRL[9..0]
Reference Clock SPDIF_MCLK DAP_MCLK REFCLK_CTRL[3..0] SDIN1 SDIN2 SDIN3 SPDIF_MCLK DAP_MCLK REFCLK_CTRL[3..0] RefClk REFCLK CLKIN R104 75
J4 TERMINAL BLACK
Parallel Port
GND Digital Audio Port (DAP)/External Control DAP_SDIN[3..1] MCLK DAP_SDIN[3..1] SCLK SDA/CDIN LRCLK X_SDA SCL DAP_SDOUT X_SCL AD0/CS X_AD0/CS X_RESETn DAP_CTRL X_RESETn MUTEC MUTEC DAP
GND
1
DAP_MCLK SCLK LRCLK SDOUT DAP_CTRL
J5 TERMINAL GREEN
-12V
1
PLD
+5V
1
CDB4228A
Figure 1. CDB4228A Top Level Schematic
9
CDB4228A
C80 100pf
R75 OUTLC81 100pf 150
R76 4.99k
-12V C83
R77 10k
C82 2.2nf
C84 10uf AINL
R78 10k 2
4
47nf GND U14A 1 MC33078 C85 R79 10k 7 + 5 MC33078 150 6 U14B R80 OUTL+
8
+12V
+12V
8
C89 10uf
R85 10k
3 2
+ 4 C90
AINR
-12V C92 R87 4.99k
Figure 2. Analog Input Filter
10
+
3
-
+ +
47nf GND TP86 R81 10k VA
+ C86
10uf C88 47nf GND U15B MC33078 GND R84 1 U15A MC33078 10k R86 6 5 + R83 7 150 GND GND C87 47nf
R82 8.25k
OUTR+
47nf GND
10k C91 2.2nf
100pf R88 OUTR-
C93 100pf
150
DS511DB1
1
1
R41 33k
R42 374
R43 374 CTRL_MO DE X_CT RL 2 SDIN_CTRL 2 S2 SW SPDT 3 1 3
1 R44 374
5
2
CONTROL PORT MODE SELECT SPI/2wire
CONTROL SOURCE XTERNAL/PPORTn
1
6
4
3
1
VCC
MODE_CTRL[9..0]
R96 10k
MODE_CTR MODE_CTR MODE_CTR MODE_CTR MODE_CTR MODE_CTR MODE_CTR MODE_CTR MODE_CTR MODE_CTR
L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
SMODE4 SMODE3 SMODE2 SMODE1 SMODE0 MCLK_SEL2 MCLK_SEL1 MCLK_SEL0 TX_MCLK_RATE1 TX_MCLK_RATE0
20 19 18 17 16 15 14 13 12 11
0 1
ON
1 2 3 4 5 6 7 8 9 10
1 2 3 4 5 6 7 8 9 10
DS511DB1
SDOUT_LOAD GND
VCC 2
VCC 2
VCC 2 D4 GREEN LED D5 GREEN LED
D3 GREEN LED
I2C
PPORT
SPDIF
S4 SW DPDT
S3 SW SPDT
SERIAL CONTROL DAP/SPDIFn
GND GND VCC VCC VCC
GND
RP10 10k RPACK9
S6 SW DIP10
CDB4228A
GND
Figure 3. External Control 11
12
VCC C76 47nf C77 47nf C78 47nf C79 47nf GND U12 R105 75 18 17 16 15 14 13 12 11 B1 B2 B3 B4 B5 B6 B7 B8 A1 A2 A3 A4 A5 A6 A7 A8 G DIR 74HC245AW M GND 2 3 4 5 6 7 8 9 19 1 JP8 TP82 1 3 5 7 9 11 13 15 17 19 GND 2 4 6 8 10 12 14 16 18 20 TP83 MC LK R66 R68 33 33 GND R67 R69 33 33 SCLK LRCLK TP84 X_DAP_SDOUT X_DAP_SDIN1 X_DAP_SDIN2 X_DAP_SDIN3 TP85 DAP_CTRL HEADER 10X2
Digital Audio Port (DAP)
U13 2 3 4 5 6 7 8 9 19 1 GND A1 A2 A3 A4 A5 A6 A7 A8 G DIR 74HC245AW M B1 B2 B3 B4 B5 B6 B7 B8 18 17 16 15 14 13 12 11
DAP_SDIN[3..1]
DAP_SDIN1 DAP_SDIN2 DAP_SDIN3
R70 R71 R72 R73
33 33 33 33
X_DAP_SDIN1 X_DAP_SDIN2 X_DAP_SDIN3
DAP_SDOUT
VCC R74 10k
JP9 1 3 5 7 9 2 4 6 8 10 X_SD A X_SC L X_AD0/CS X_RES ETn MUTEC
CDB4228A
HEADER 5X2
XTERNAL CONTROL
GND
DS511DB1
Figure 4. Digital Audio Port
8
2 C41 1nf GND
4
MC330 78 C42 47nf
604 10uf
+
GND GND -12V R18 GND Q1 2SC3326 R19 1 2 R17 C117 3.16k 47nf MU TE 3
1.78k GND 3.16k
GND GND
C43 100pf
Figure 5. Analog Output Filter 1
2
DS511DB1
C38 1nf TP65 +12V C39 47nf R13 3.16k IN R14 3.16k 3 GND C40 + U7A 1 R15 J8 PHONO JACK RA 1 R16 100k
CDB4228A
13
6 C54 1nf GND
-
MC330 78
604 10uf
+
GND R31 GND 3 R32 Q2 2SC3326 1
2 C118 47nf GND R33 3.16k
2
14
C52 TP77 1nf R27 3.16k IN R28 3.16k 5 + U7B 7 R29 C53 J10 PHONO JACK RA 1 R30 100k 1.78k GND 3.16k C55 GND 100pf MU TE
Figure 6. Analog Output Filter 2
CDB4228A
DS511DB1
8
2 C59 1nf GND
4
MC330 78 C60 47nf
604 10uf
+
GND GND -12V R39 GND Q3 2SC3326 R40 1 C119 47nf 2 R38 3.16k MUT E 3
1.78k GND 3.16k C61
GND GND
100pf
Figure 7. Analog Output Filter 3
2
DS511DB1
C56 1nf TP78 +12V C57 47nf R34 3.16k IN R35 3.16k 3 GND C58 + U10A 1 R36 J11 PHONO JACK RA 1 R37 100k
CDB4228A
15
6 C64 1nf GND
-
MC330 78
604 10uf
+
GND GND 3 R49 3.16k GND 1 C65 GND 100pf GND C120 47nf R50 1.78k Q4 2SC3326
2 R51 3.16k
2
16
C62 1nf TP79 R45 3.16k IN R46 3.16k 5 + U10B 7 R47 C63 J12 PHONO JACK RA 1 R48 100k MUT E
Figure 8. Analog Output Filter 4
CDB4228A
DS511DB1
8
2 C69 1nf GND
4
MC3307 8 C70 47nf
604 10uf
+
GND GND -12V R57 GND Q5 2SC3326 R58 1 C121 47nf 2 R56 3.16k MUT E 3
1.78k GND 3.16k
GND GND
C71 100pf
2
DS511DB1
C66 1nf TP80 +12V C67 47nf R52 3.16k IN R53 3.16k 3 GND C68 + U11A 1 R54 J13 PHONO JACK RA 1 R55 100k
CDB4228A
Figure 9. Analog Output Filter 5
17
6 C74 1nf GND
-
MC3307 8
604 10uf
+
GND GND R63 R64 Q6 2SC3326 1.78k GND 3.16k C75 1 C122 47nf GND 100pf 2 R65 3.16k MUT E 3
GND
Figure 10. Analog Output Filter 6
2
18
C72 1nf TP81 R59 3.16k IN R60 3.16k 5 + U11B 7 R61 C73 J14 PHONO JACK RA 1 R62 100k
CDB4228A
DS511DB1
+
DS511DB1
R3 10k From DAC R1 100K
Mute
R2 100k C2 3.3nF Mute Control
To Amp
C1 10uF
CDB4228A
Figure 11. Low Cost Analog Output Filter 19
1 2 3 4 5 6 7 8 9 10
VCC RP6 PP_D0 PP_D1 PP_D2 PP_D3 PP_D4 PP_D5 PP_D6 PP_D7 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k RPACK8 D0 D1 D2 D3 D4 D5 D6 D7 D[7..0]
VCC TP87 RP7 PP_nSTROBE nAUTOFEED nINIT nSELECTIN TP89 TP91 TP93 TP95 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 4.7k RPACK8 STROBEn A0 A1 TP88
1 2 3 4 5 6 7 8 9 10
PP_D4 PP_D5 PP_D6 PP_D7 PP_nACK nBUSY PE SELEC T ACKn
VCC RP9 TP97 TP99 TP101 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 22 RPACK8 PP_nACK TP98 TP100 TP102
1 2 3 4 5 6 7 8 9 10
20
RP5 1k RPACK9 RP4 1k RPACK9 TP90 TP92 TP94 TP96 A[1..0] 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 J15 DB25M_R A PP_nSTROBE nAUTOFEED PP_D0 nERROR PP_D1 nINIT PP_D2 nSELECTIN PP_D3 RESET n RP8 1k RPACK9 nBUSY PE SELEC T nERROR STATUS STATUS STATUS STATUS 0 1 2 3 STATUS[3..0]
CDB4228A
GND
Figure 12. Control Port Interface
DS511DB1
1 2 3 4 5 6 7 8 9 10
PLD PWR SEL
SPDIF_SDOUT SPDIF_SDOUT
2
EPM7128STC100-15 GND RESET_LED
2 D2 RED LED 1
+
C19 10uf
+
C20 10uf
C27 47nf
C28 47nf
C29 47nf
C30 47nf
C31 47nf
C32 47nf
1
DS511DB1
RP3 1k RPACK9 MODE_CTRL[9..0] MODE_CTRL0 MODE_CTRL1 MODE_CTRL2 MODE_CTRL3 MODE_CTRL4 MODE_CTRL5 MODE_CTRL6 MODE_CTRL7 MODE_CTRL8 MODE_CTRL9 JP7 TCK TDO TMS TDI 1 3 5 7 9 2 4 6 8 10 VCC VCC HEADER 5X2 GND U6 STROBEn MRESETn RXPWR CLKIN D[7..0] D0 D1 D2 D3 D4 D5 D6 D7 MODE_CTRL6 MODE_CTRL7 MODE_CTRL8 MODE_CTRL9 D0 STATUS3 D1 A0 D2 A1 D3 D4 D5 D6 D7 ACKn STATUS[3..0] STATUS0 STATUS1 STATUS2 STATUS3 TP51 TP53 CTRL_MODE X_CTRL SDIN_CTRL TP56 R EFCLK_CTRL[3..0] REFCLK_CTRL0 REFCLK_CTRL1 REFCLK_CTRL2 REFCLK_CTRL3 RX_VERF RX_ERF TP55 TP58 SPDIF_ERRORn RESET_LED TP61 SDIN1 SDIN2 SDIN3 SPDIF_SDOUT REFCLK_CTRL0 REFCLK_CTRL1 REFCLK_CTRL2 REFCLK_CTRL3 VCC 2 4 STATUS0 STATUS1 STATUS2 87 89 88 90 1 2 5 6 7 8 9 10 12 13 14 16 17 19 20 21 22 23 24 25 27 28 29 30 31 32 33 35 36 37 40 41 42 44 45 46 47 48 49 50 39 91 3 18 34 51 66 82 GCLK1 GCLRn OE1 OE2/GCLK2 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO13 IO14 IO15 IO16 IO17 IO18 IO19 IO20 IO21 IO22 IO23 IO24 IO25 IO26 IO27 IO28 IO29 IO30 IO31 IO32 IO33 IO34 IO35 IO36 IO37 IO38 IO39 IO40 VCCINT1 VCCINT2 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 TDI TMS TCK TDO IO41 IO42 IO43 IO44 IO45 IO46 IO47 IO48 IO49 IO50 IO51 IO52 IO53 IO54 IO55 IO56 IO57 IO58 IO59 IO60 IO61 IO62 IO63 IO64 IO65 IO66 IO67 IO68 IO69 IO70 IO71 IO72 IO73 IO74 IO75 IO76 4 15 62 73 52 53 54 55 56 57 58 60 61 63 64 65 67 68 69 70 71 72 75 76 77 78 79 80 81 83 84 85 92 93 94 96 97 98 99 100 TDI TMS TCK TDO TP43 CDIN AD0/CS SDA/CDOUT SCL HALFSCLK TP47 TP48 SCLK LRCLK TP49 TP50 RX_C RX_U RX_CBL TX_M0 TX_M1 TX_M2 RX_M[3..0] TX_C TX_U TX_CBL RX_M0 RX_M1 RX_M2 RX_M3 A[1..0] A0 A1 RX_M3 RX_M2 RX_M0 RX_M1 MODE_CTRL0 MODE_CTRL1 MODE_CTRL2 TX_M[2..0] TX_M0 TX_M1 TX_M2 MODE_CTRL3 TP60 MODE_CTRL4 MODE_CTRL5 DAP_SDIN1 DAP_SDIN2 DAP_SDIN3 DAP_CTRL TX_MCLK TP64 SDIN[3..1] SDIN1 SDIN2 SDIN3 DAP_SDIN[3..1] DAP_SDIN1 DAP_SDIN2 DAP_SDIN3 VCC GNDINT1 GNDINT2 GNDIO1 GNDIO2 GNDIO3 GNDIO4 GNDIO5 GNDIO6 38 86 11 26 43 59 74 95
+3.3V
VD VCC
JP10 1 3
R11 374
VCC
+5V
HEADER 2X2
R12 374 D1 RED LED
SPDIF_ERRORn
GND VCC
CDB4228A
+ C33
10uf
C34 47nf
C35 47nf
GND
Figure 13. Programmable Logic 21
2
+ C94
D11 P6KE13A C100 47nf C101 47nf
22uf
2
1
2
D12 P6KE13A
+ C102
C109 47nf L4 C103 47nf 22uf R90 1k
2
1
-12V
Analog Supply Voltage
TP109
VA TP115 L5
+5V Analog Supply Voltage
+ C110
C111 47nf 22uf
GND
5V Digital Supply Voltage
VCC TP110 L6 +5VBUS R91 374 2 1 D13 P6KE6.8A 3 TP111 TP112 U16 LT1086CT-3.3 VIN ADJ VOUT 2 TP103 TP114 VD
1
-12VBUS
1
1
6.8V
1
C114 47nf
C115 47nf
2
GND GND 3
1
5
22
+12V
Analog Supply Voltage
R89 1k
TP105
L3 +12VBUS
D6 GREEN LED
+ C95
10uf
+ C96
10uf
+ C97
10uf
+ C98
10uf
+ C99
10uf TP106 TP107 TP108
13V
GND
+ C104
D7 GREEN LED
13V
10uf
+ C105
10uf
+ C106
10uf
+ C107
10uf
+ C108
10uf
3.3V Digital Supply Voltage
+ C112
22uf R92 121
+
C113 22uf
D8 GREEN LED R93 500 POT
GND 2
+ C116
GND GND
22uf
R94 0
GND TP104 D9 1N4148 2 1 D10 1N4148 2 1
X_RESETn
MRESETn D14 1N4148 2 1 R95 0
VL 1 Q7 MUN2111T1 D15 1N4148 2 1 3 2 Q8 MUN2211T1 2 TP116 3 MUTE R97 10k GND 1 GND
MRESETn
PPRESETn
VCC S5 PTS645TL50 1 2 U17 4 3 2 VCC RESETn GND DS1233-10 3 1 MUTEC MUTEC
CDB4228A
DS511DB1
GND
-12V
Figure 14. Power Supply
REFCLK_CTRL3 U2B 74AC125SC R2 SPDIF_MCLK SPDIF_MCLK 5 6 33 4
1
R106 75 R4 33
REFCLK_CTRL1
GND 11
U2D 74AC125SC 12 REFCLK
REFCLK_CTRL0 REFCLK_CTRL[3..0]
13
10
DS511DB1
U1 1 7 GND R1 TP1 OSC 33 U2A 74AC125SC 2 3 TP2 NC GND +5V CLKOUT 14 8 GND 12.2880 MHZ REFCLK_CTRL2 U2C 74AC125SC DAP_MCLK 9 8 DAP_MCLK VCC C3 47nf GND GND C4 47nf
OFF
VCC
3 2 1
ON
JP1 HDR3X1
OSC
C1 47nf GND C2 47nf
JP2 OSC SPDIF_MCLK MUX_ MCLK 2 4 6 1 3 5 REFCLK REFCLK
HEADER 3X2
REFCLK SELECT
R3
0
CDB4228A
Figure 15. Master Clock Circuit
23
CASE2 CASE1 GND2 GND1
6 5 4 2
GND GND
2
24
RXPWR L1 U8 22 C44 47nf C48 R21 C45 47nf GND 20 VCC GND 68nf NPO 470 16 13 M3 M2 M1 M0 SEL CS12/FCK FILT VERF ERF CBL U C C0/E0 Ca/E1 Cb/E2 Cc/F0 Cd/F1 Ce/F2 MCK SCK FSYNC SDATA 28 25 15 14 1 6 5 4 3 2 27 19 12 11 26 VA+ VD+ 7 C46 47nf GND RX_VERF RX_ERF C47 47nf TP66 TP67 TP68 RX_CB L RX_U RX_C TP70 TP71 TP72 TP73 TP75 TP76 R22 R23 R24 R25 TP74 R20 10k 21 AGND DGND 8 L2 47uH U9 TORX 173 VCC 3 GND OUT 1 C51 47nf 47nf J9 PHONO JACK RA 1 R26 75 1% GND 10 C50 9 C49 47nf M[3..0] TP69 17 18 24 23 M3 M2 M1 M0 RXP RXN CS8414-CS S1 33 33 33 33 1 2 3 6 5 4 SW DIP-3 MCL K VCC SCLK FSYNC
PWR DOWN
SDOUT
Figure 16. CS8414 Digital Audio Receiver
CDB4228A
DS511DB1
2 3 4 5 6 7 8 9 10
TP28 TP30 TP32 TP34 TP36 TP38 TP39 TP40 VCC
TRNPT/FC1 nPRO V C/SBF U nC9/nC15 EM0/nC9
TP29 TP31 TP33 TP35 TP37 GND
nC7/nC3 nC1/FC0 nC6/nC2 EM1/nC8
VCC U4 TP41 C15 47nf C16 47nf 19 18 VD+ GND TRNPT/FC1 C7/C3 PRO C1/FC0 C6/C2 C9/C15 EM1/C8 EM0/C9 M2 M1 M0 24 1 2 3 4 12 13 14 23 22 21 TRNPT/FC1 nC7/nC3 nPRO nC1/FC0 nC6/nC2 nC9/nC15 EM1/nC8 EM0/nC9 M2 M1 M0 M[2..0] VCC C17 47nf 3 R8 CBL/SBC TX_C TX_U V C/SBF U 9 10 11 V C/SBF U CS8404A-CS C18 R9 374 3 47nf 1% R10 93.1 1% 2 J7 PHONO JACK RA 1 2 TXP TXN 15 20 17 CASE1 CASE2 5 6 GND 1 TX_C BL 2 GND 8.25k 4
GND RESET n nMRE SET 16 RST
MCL K SCLK LRCLK SDIN
MCL K SCLK LRCLK
2 3 4 5 6 7 8 9 10
GND GND
Figure 17. CS8404 Digital Audio Transmitter 25
5
DS511DB1
GND
RP1 1 10k RPACK9 VCC
RP2 1 10k RPACK9
5 6 7 8
MCK SCK FSYNC SDATA
U5 TO TX173 VCC R IN
4
CDB4228A
1
6 GND T1 6712960 0
CDB4228A
Figure 18. Silkscreen Top
26
DS511DB1
CDB4228A
Figure 19. Top Side
DS511DB1
27
CDB4228A
Figure 20. Level 2 Ground Plane
28
DS511DB1
CDB4228A
Figure 21. Level 3
DS511DB1
29
CDB4228A
Figure 22. Bottom Side
30
DS511DB1
10. BILL OF MATERIALS
Item 1 Qnty 55 Reference C1,C2,C3,C4,C6,C9,C12, C13,C15,C16,C17,C18,C27, C28,C29,C30,C31,C32,C34, C35,C39,C42,C44,C45,C46, C47,C49,C50,C51,C57,C60, C67,C70,C76,C77,C78,C79, C83,C85,C87,C88,C90,C100, C101,C103,C109,C111,C114, C115,C117,C118,C119,C120, C121,C122 C5,C7,C8,C19,C20,C33,C40, C53,C58,C63,C68,C73,C84, C86,C89,C95,C96,C97,C98, C99,C104,C105,C106,C107,C108 C38,C41,C52,C54,C56,C59, C62,C64,C66,C69,C72,C74 C43,C55,C61,C65,C71,C75, C80,C81,C92,C93 C48 C82,C91 Value 47nf Mfg KEMET Mfg P/N Description C1206C473K5R CAP, CERAMIC, 47NF, 50V, 10%, X7R, AC 1206 PCB Footprint CSN_1206
DS511DB1 31
2
25
10uf
PANASONIC
ECEV1CS100SR
CAP, ELECT, 10UF, 16V, 20%, AL, SM_A CSP_ELEC_130SQ
3 4 5 6 7 8 9 10 11 12 13 14 15
12 10 1 2 6 2 6 4 2 1 1 1 6
1nf 100pf 68nf 2.2nf
KEMET KEMET KEMET KEMET PANASONIC LITEON LITEON LITEON MOTOROLA MOTOROLA SAMTEC
C94,C102,C110,C112,C113,C116 22uf D2,D1 D3,D4,D5,D6,D7,D8 D9,D10,D14,D15 D11,D12 D13 JP1 JP2 JP3,JP4,JP5,JP6,JP10,JP11 RED LED GREEN LED 1N4148 P6KE13 A P6KE6.8 A HDR3X1
C1206C102J1G AC C1206C101J1G AC C1206C683K5R AC C1206C222J1G AC ECEV1EA220SP LT1139 LT1142 1N4148 P6KE13A P6KE6.8A TSW-103-07-GS TSW-103-07-GD TSW-102-07-GD
CAP, CERAMIC, 1NF, 100V, 5%, NPO, 1206 CAP, CERAMIC, 100PF, 100V, 5%, NPO, 1206 CAP, CERAMIC, 68NF, 50V, 10%, X7R, 1206 CAP, CERAMIC, 2.2NF, 50V, 5%, NPO, 1206 CAP, ELECT, 22UF, 25V, 20%, AL, SM_D LED, RED, DIFF, T1 LED, GREEN, DIFF, T1 DIODE, SWITCHING, DO35 DIODE, ZENER, 13V, DO7 DIODE, ZENER, 6.8V, DO7 HEADER, MALE, 3X1 HEADER, MALE, 3X2 HEADER, MALE, 2X2
CSN_1206 CSN_1206 CSN_1206 CSN_1206 CSP_ELEC_260SQ LED_T-1 LED_T-1 DO35 DO7 DO7 HDR3X1
CDB4228A
HEADE SAMTEC R 3X2 HEADE SAMTEC R 2X2
HDR3X2 HDR2X2
Table 6. Bill of Materials
32 DS511DB1
16 17 18
2 1 10
JP7,JP9 JP8 J1,J2,J7,J8,J9,J10,J11, J12,J13,J14 J3
19
1
20
1
J4
21
1
J5
22
1
J6
23 24 25 26 27 28 29 30 31 32 33
1 5 1 6 1 1 3 4 2 1 15
J15 L1,L3,L4,L5,L6 L2 Q1,Q2,Q3,Q4,Q5,Q6 Q7 Q8 RP1,RP2,RP10 RP3,RP4,RP5,RP8 RP7,RP6 RP9 R1,R2,R4,R22,R23,R24,R25, R66,R67,R68,R69,R70,R71, R72,R73
HEADE R 5X2 HEADE R 10X2 PHONO JACK RA TERMINAL BLUE TERMINAL BLACK TERMINAL GREEN TERMINAL RED DB25M_ RA ELDR25
SAMTEC
TSW-105-07-GD SAMTEC TSW-110-07-GD A/D ELECT ARJ2018
HEADER, MALE, 5X2 HEADER, MALE, 10X2 PHONO JACK, RA, GOLD
HDR5X2 HDR10X2 CON_RCA_RA
E.F.JOHNS 111-0110-001 ON E.F.JOHNS 111-0103-001 ON E.F.JOHNS 111-0104-001 ON E.F.JOHNS 111-0102-001 ON DB25-PL-24 EXC-ELDR25 8230-60 2SC3326 MUN2111T1 MUN2211T1 4610X-101-103 4610X-101-102 4816P-T01-472 4816P-T01-220 ERJ-8GEYJ330
BINDING POST, BLUE, BPOST
CON-BINDPOST
BINDING POST, BLACK, BPOST
CON-BINDPOST
BINDING POST, GREEN, BPOST
CON-BINDPOST
BINDING POST, RED, BPOST
CON-BINDPOST
ADAM TECH PANASONIC 47uH J.W. MILLER 2SC332 TOSHIBA 6 MUN211 MOTOR1T1 OLA MUN221 MOTOR1T1 OLA 10k BOURNS RPACK9 1k BOURNS RPACK9 4.7k BOURNS RPACK8 22 BOURNS RPACK8 33 PANASONIC
CONNECTOR, DB25, MALE, RA FERRITE, RADIAL, RADIAL200 INDUCTOR, 47UH, SHIELDED, IND500 BJT, NPN, MUTE, SC59 BJT, PNP, 10K INTERNAL BIAS, SC59 BJT, NPN, 10K INTERNAL BIAS, SC59 RES, R-PACK9, 10K, 1/8W, 2%, SIP10 RES, RPACK9, 1K, 1/8W, 2%, SIP10 RES, RPACK8, 4.7K, 1/8W, 2%, SOM16 RES, RPACK8, 22, 1/8W, 2%, SOM16 RES, THICK FILM, 33, 1/8W, 5%, 1206
CON_DB25M_RA EXC-ELDR25 IND500 SC59 SC59 SC59 SIP10 SIP10 SO16-220
CDB4228A
SO16-220 RES_1206
Table 6. Bill of Materials
34 35 36
3 13 25
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
2 7 1 6 6 6 1 4 1 10 2 2 1 1 1 2 1
R3,R94,R95 R5,R7,R20,R74,R77,R78, R79,R81,R84,R85,R86,R96,R97 R6,R13,R14,R17,R18,R27, R28,R31,R33,R34,R35,R38, R39,R45,R46,R49,R51,R52, R53,R56,R57,R59,R60,R63,R65 R8,R82 R9,R11,R12,R42,R43,R44,R91 R10 R15,R29,R36,R47,R54,R61 R16,R30,R37,R48,R55,R62 R19,R32,R40,R50,R58,R64 R21 R26,R104,R105,R106 R41 R75,R80,R83,R88,R98,R99, R100,R101,R102,R103 R76,R87 R89,R90 R92 R93 S1 S3,S2 S4
0 10k 3.16k
YAGEO PANASONIC PANASONIC
ERJ-8GEYJ000 ERJ-8ENF1002 ERJ-8ENF3161
RES, 0 OHM JUMPER, 1/8W, 1206 RES, THICK FILM, 10K, 1/8W, 1%, 1206 RES, THICK FILM, 3.16K, 1/8W, 1%, 1206
RES_1206 RES_1206 RES_1206
DS511DB1 33
8.25k 374 93.1 604 100k 1.78k 470 75 33k 150 4.99k 1k 121
500 3296Y-501 POT SW DIP- GRAYHILL 76SB03 3 SW C&K TS01CBE SPDT SW AUGUAT TSS21NGPC DPDT
PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC BOURNS
ERJ-8ENF8251 ERJ-8ENF3740 ERJ-8ENF93R1 ERJ-8ENF6040 ERJ-8GEYJ104 ERJ-8ENF1781 ERJ-8GEYJ470 ERJ-8ENF75R0 ERJ-8GEYJ333 ERJ-8ENF1500 ERJ-8ENF4991 ERJ-8GEYJ102 ERJ-8ENF1210
RES, THICK FILM, 8.25K, 1/8W, 1%, 1206 RES, THICK FILM, 374, 1/8W, 1%, 1206 RES, THICK FILM, 93.1, 1/8W 1%, 1206 RES, THICK FILM, 604, 1/8W, 1%, 1206
RES_1206 RES_1206 RES_1206 RES_1206
RES, THICK FILM, 100K, 1/8W, 5%, 1206 RES_1206 RES, THICK FILM, 1.78K, 1/8W, 1%, 1206 RES, THICK FILM, 470, 1/8W, 5%, 1206 RES, THICK FILM, 75, 1/8W, 1%, 1206 RES, THICK FILM, 33K, 1/8W, 5%, 1206 RES, THICK FILM, 150, 1/8W, 1%, 1206 RES, THICK FILM, 4.99K, 1/8W, 1%, 1206 RES, THICK FILM, 1K, 1/8W, 5%, 1206 RES, THICK FILM, 121, 1/8W, 1%, 1206 POTENTIOMETER, 25T, TOP ADJ, 500, 3296Y SWITCH, DIP, 3 POS, ROCKER, DIP6 SWITCH, SLIDE, SPDT SWITCH, SLIDE, DPDT RES_1206 RES_1206 RES_1206 RES_1206 RES_1206 RES_1206 RES_1206 RES_1206 POT_BRNS_3296Y SW-DIP3
CDB4228A
SW_CK_TS01CBE SW_AGT_TSS21NG PC
Table 6. Bill of Materials
34 DS511DB1
54 55 56
1 1 106
57 58 59 60 61 62 63
1 1 1 1 1 1 1
64
5
PTS645 C&K TL50 S6 SW GRAYHILL DIP10 TP1,TP2,TP3,TP4,TP5,TP6,TP7, TEST TP8,TP9,TP10,TP11,TP12,TP13, POINT TP14,TP15,TP16,TP17,TP18, TP19,TP20,TP21,TP22,TP23, TP24,TP25,TP26,TP27,TP28, TP29,TP30,TP31,TP32,TP33, TP34,TP35,TP36,TP37,TP38, TP39,TP40,TP41,TP43,TP47, TP48,TP49,TP50,TP51,TP53, TP55,TP56,TP58,TP60,TP61, TP64,TP65,TP66,TP67,TP68, TP69,TP70,TP71,TP72,TP73, TP74,TP75,TP76,TP77,TP78, TP79,TP80,TP81,TP82,TP83, TP84,TP85,TP86,TP87,TP88, TP89,TP90,TP91,TP92,TP93, TP94,TP95,TP96,TP97,TP98, TP99,TP100,TP101,TP102, TP103,TP104,TP105,TP106, TP107,TP108,TP109,TP110, TP111,TP112,TP113,TP114, TP115,TP116 T1 6712960 SCHOTT 0 U1 12.2880 CAL MHZ CRYSTAL U2 74AC12 FAIR5SC CHILD U3 CS4228 CRYSTAL A-KS U4 CS8404 CRYSTAL A-CS U5 TOTX17 TOSHIBA 3 U6 EPM712 ALTERA 8STC10 0-15 U7,U10,U11,U14,U15 MC3307 MOTOR8 OLA
S5
PTS645TL50 76SB10 -
SWITCH, 6MM TACT W/ ESD PIN, SW-MOM-C&K 130GF, DPST SWITCH, DIP, 10 POS, ROCKER, DIP20 SW-DIP10 TEST POINT, PAD60R40 TESTPOINT
67129600 CX21AF12.2880MHZ 74AC125SC CS4228D-KS CS8404A-CS TOTX173
XFMR, PULSE, TH
XFR_SC67129600
IC, OSCILLATOR, 12.2880MHZ, 50PPM, OSC-FULL OSC14 IC, TRISTATE BUFFER, QUAD, SO14 SO14-150 IC, CODEC, SSOP28 IC, SPDIF TX, SOIC24 IC, OPTICAL TXMTR SSOP28-209 SO24-300 TOTX173
CDB4228A
EPM7128STC10 IC, CPLD, 128MC, 15NS, TQFP100 0-15 MC33078D IC, OPAMP, DUAL, SO8
QFP100_14X14
SO8-150
Table 6. Bill of Materials
65 66 67 68 69 100 101 102 103 104 105 106 107
1 1 2 1 1 4 6 6 4 4 3 2 2
U8 U9 U13,U12 U16 U17 U1 J3,4,5,6 JP6, 10, 11 J15 J15
CS8414CS TORX17 3 74HC24 5AWM LT1086 CT-3.3 DS123310
CRYSTAL TOSHIBA FAIRCHILD LINEAR DALLAS AUGUAT Keystone/DK MCMASTER CARR MOLEX
CS8414-CS TORX173
IC, SPDIF RX, SOIC28 IC, OPTICAL RX
SO28-300 TORX173 SO20-300 TO-220AB TO-92
DS511DB1 35
MM74HC245AW IC, TRANCEIVER, HEX, SOW20 M LT1086CT-3.3 IC, VOLTAGE REG, POSITIVE, 3.3V, TO220 DS1233-10 IC, POWER SUPPLY MONITOR, TO92 8134-HC-5P2 8401K-ND SOCKET, PIN, POP-IN, SM 1/2" X 4-40 HEX STANDOFF
91773A108/PAN 4-40 3/8" MACHINE SCREW, PAN 4CR6SZ 15-29-1025 SHUNT, OPEN END Connect wire, 20GA, Stranded, 2" shorting jumper, 22GA, solid MACHINE SCREW, 6-32 x 1/2", PAN HEAD NUT, #6
Table 6. Bill of Materials
CDB4228A

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