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| Back CS51227 Enhanced Voltage Mode PWM Controller The CS51227 is a fixed frequency, single output PWM controller using feed forward voltage mode control. Feed forward control provides superior line regulation and line transient response. This PWM controller has been optimized for high frequency primary side control operation. It has undervoltage lockout with 4.7 V start up voltage and 75 A start up current. One external capacitor can program the switching frequency up to 1.0 MHz. The protection features include pulse-by-pulse current limit with leading edge blanking and thermal shutdown. The CS51227 is available in 8 lead SO narrow surface mount package. http://onsemi.com 8 1 SO-8 D SUFFIX CASE 751 * * * * * * * * * * * Features 1.0 MHz Frequency Capability 4.7 V Start-Up Voltage Fixed Frequency Voltage Mode Operation with Feed Forward Undervoltage Lockout 75 A Start-Up Current Thermal Shutdown 1.0 A Sink/Source Gate Drive Pulse-By-Pulse Current Limit with Leading Edge Blanking 50 ns GATE Rise and Fall Time (1.0 nF Load) Maximum Duty Cycle Over 85% Programmable Volt-Second Clamp PIN CONNECTIONS AND MARKING DIAGRAM 1 51227 ALYW 8 GATE ISENSE FF CT A WL, L YY, Y WW, W VCC GND COMP VFB = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device CS51227ED8 CS51227EDR8 Package SO-8 SO-8 Shipping 95 Units/Rail 2500 Tape & Reel (c) Semiconductor Components Industries, LLC, 2001 1 April, 2001 - Rev. 7 Publication Order Number: CS51227/D CS51227 5.0 V 6.8 H 12 V/ 2.0 A B320DICT 0.1 F FS70VSJ-03 0.1 GATE CS51227 ISENSE 0.025 FF CT VCC GND 1.0 k + 51 k COMP 2700 pF VFB 9.1 k 5.6 nF 300 22 F x 4 + 9.31 k 1.0 nF 330 pF 22 F x 2 100 pF 110 GND GND Figure 1. Applications Diagram, 5.0 V to 12 V/2.0 A Boost Converter MAXIMUM RATINGS* Rating Operating Junction Temperature, TJ Storage Temperature Range, TS ESD Susceptibility (Human Body Model) Lead Temperature Soldering: 1. 60 second maximum above 183C. *The maximum package power dissipation must be observed. Reflow: (SMD styles only) (Note 1) Value 150 -65 to +150 2.0 230 peak Unit C C kV C MAXIMUM RATINGS Pin Name Gate Drive Output Current Sense Input Timing Capacitor Feed Forward Error Amp Output Feedback Voltage Power Supply Ground Pin Symbol GATE ISENSE CT FF COMP VFB VCC GND VMAX 20 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 20 V N/A VMIN -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V N/A ISOURCE 1.0 A Peak, 200 mA DC 1.0 mA 1.0 mA 1.0 mA 10 mA 1.0 mA 10 mA 1.0 A Peak, 200 mA DC ISINK 1.0 A Peak, 200 mA DC 1.0 mA 10 mA 25 mA 20 mA 1.0 mA 1.0 A Peak, 200 mA DC N/A http://onsemi.com 2 CS51227 ELECTRICAL CHARACTERISTICS: (-40C < TA < 85C, -40C < TJ < 125C, 4.7 V < VCC < 18 V CT = 390 pF; unless otherwise specified.) Characteristic Start/Stop Voltages Start Threshold Stop Threshold Hysteresis ICC @ Startup Supply Current ICC Operating Overcurrent Protection Overcurrent Threshold ISENSE to GATE Delay Error Amp Reference Voltage VFB Input Current Open Loop Gain Unity Gain Bandwidth COMP Sink Current COMP Source Current COMP High Voltage COMP Low Voltage PSRR Oscillator Frequency Accuracy Max Duty Cycle Peak Voltage Valley Clamp Voltage Valley Voltage Discharge Current Charge Current Gate Driver High Saturation Voltage Low Saturation Voltage High Voltage Clamp Output UVL Leakage Rise Time Fall Time Max GATE Voltage @ UVL VGATE = 0 V 1.0 nF Load, VCC = 18 V, 1.0 V < VO < 9.0 V 1.0 nF Load, VCC = 18 V, 9.0 V < VO < 1.0 V ILOAD = 100 A VCC - VGATE, VCC = 10 V, ISOURCE = 150 mA VGATE, ISINK = 150 mA - - - 11 - - - 0.4 1.5 1.2 13.5 1.0 32 25 0.7 2.0 1.5 16 50 50 50 1.5 V V V A ns ns V Note 2 - - Note 2 - - - 200 85 1.99 0.90 0.90 0.85 95 235 90 2.05 0.95 0.95 1.00 115 270 95 2.11 1.00 1.00 1.15 135 kHz % V V V mA A VFB connected to COMP VFB = 1.25 V Note 2 Note 2 COMP = 1.4 V, VFB = 1.45 V COMP = 1.4 V, VFB = 1.15 V VFB = 1.15 V VFB = 1.45 V Freq = 120 Hz, Note 2 1.234 - 60 1.5 3.0 1.0 2.8 75 60 1.263 1.3 90 2.5 12 1.7 3.1 150 85 1.285 2.0 - - 32 2.4 3.4 300 - V A dB MHz mA mA V mV dB Ramp ISENSE VFB = 0.5 V (no blanking) 0.27 - 0.30 60 0.33 125 V ns No Load - 10 16 mA Start - Stop VCC < UVL Start Threshold - - 4.4 3.2 300 - 4.5 3.8 700 38 4.7 4.2 1400 75 V V mV A Test Conditions Min Typ Max Unit 2. Guaranteed by design, not 100% tested in production. http://onsemi.com 3 CS51227 ELECTRICAL CHARACTERISTICS: (continued) (-40C < TA < 85C, -40C < TJ < 125C, 4.7 V < VCC < 18 V CT = 390 pF; unless otherwise specified.) Characteristic Feed Forward (FF) Discharge Voltage Discharge Current FF to GATE Delay FF Max VOltage Blanking Blanking Time COMP Blanking Disable Threshold Thermal Shutdown Thermal Shutdown Thermal Hysteresis Note 3 Note 3 125 5.0 150 10 180 15 C C VFB < 1.0 V - 50 2.8 150 3.0 250 3.3 ns V VFB = 1.15 V IFF = 2.0 mA FF = 1.0 V - - 2.0 50 1.7 0.3 16 75 1.8 0.7 30 125 1.9 V mA ns V Test Conditions Min Typ Max Unit 3. Guaranteed by design, not 100% tested in production. PACKAGE PIN DESCRIPTION PACKAGE LEAD # SO-8 1 2 3 4 5 6 7 8 LEAD SYMBOL GATE ISENSE FF CT VFB COMP GND VCC FUNCTION External power switch driver with 1.0 A peak capability. Rail-to-rail output occurs when the capacitive load is between 470 pF and 10 nF. Current sense comparator input. PWM ramp. Timing capacitor CT determines oscillator frequency. Feedback voltage input. Connected to the error amplifier inverting input. Error amplifier output. Ground. Supply voltage. http://onsemi.com 4 CS51227 VCC 4.7 - 18 V 3.3 V + - + - UV Lockout Start/Stop PWM COMP CT OSC 3.0 V - - + G2 VREF = 3.3 V 3.1 V VREF OK + - S Q G1 13.5 V R Q GND Low Sat Gate Driver GATE VREF Thermal Shutdown 1.263 V EAMP + VFB COMP FF - + - Blank Disable 1.8 V FF Discharge 0.3 V ISENSE 150 ns Blank + ILIM - Figure 2. Block Diagram THEORY OF APPLICATION THEORY OF OPERATION Feed Forward Voltage Mode Control VIN Power Stage GATE R Latch & Driver Feedback Network FF COMP PWM FB - VOUT C Figure 3. Feed Forward Voltage Mode Control http://onsemi.com 5 + + - In conventional voltage mode control, the ramp signal is fixed and often generated by the oscillator. The output voltage is the only feedback path for regulation against load and line variations. Feed forward voltage mode uses the ramp signal driven by the input line, as shown in Figure 3. Therefore, the ramp signal responds immediately to line change. At the start of each switch cycle, the FF pin capacitor is charged up through a resistor connected to the input line. Meanwhile, the Gate output is turned on to drive an external power switching device. When the FF pin voltage reaches the error amplifier output VCOMP , the PWM comparator turns off the Gate and the FF pin capacitor is quickly discharged by an internal current source. Error Amplifier CS51227 VOUT Powering the IC & UVL VCOMP FF VIN CT GATE Figure 4. Pulse Width Modulated By Output Current With Constant Input Voltage The internal logic monitors the supply voltage to ensure the controller has enough operating headroom. The VREF block provides power to the controller's logic. The VREF(OK) comparator monitors the internal 3.3 V VREF line and flags a fault if VREF falls below 3.1 V. The Undervoltage Lockout (UVL) comparator has two voltage references; the start and stop thresholds. During power-up, the UVL comparator disables VREF (which in-turn disables the entire IC) until the controller reaches its VCC start threshold. During power-down, the UVL comparator allows the controller to operate until the VCC stop threshold is reached. The CS51227 requires only 50 A during startup. During low VCC and abnormal operation conditions, the output stage is held at a low level, low impedance state. Current Sense and Over Current Protection Overall, the dynamics of the duty cycle are controlled by both input and output voltages. As shown in Figure 4, an elevated output voltage reduces VCOMP through the error amplifier. This in turn decreases the duty cycle and corrects the deviation of the output voltage. For line variation, the ramp signal responds immediately, which provides much improved line transient response. The delay associated with the power stage and feedback path has been totally avoided. As an example, shown in Figure 5, when the input line goes up, the slope of the ramp signal increases, reducing duty cycle to counteract the change. VOUT VCOMP FF VIN The ISENSE pin monitors the switch current for pulse by pulse current limit. When the ISENSE pin voltage exceeds the internal threshold (0.3 V typical), the current limit comparator immediately turns off the Gate signal. The Gate will then stay off for the remainder of the cycle. Various techniques, such as using current sensing resistor or current transformer, are widely adopted to generate the current signal. The current sense signal is prone to leading edge spikes caused by switching transitions. A RC low-pass filter can effectively reduce the spikes and avoid premature triggering. However, the low pass filter will inevitably change the shape of the current pulse and also add cost. The CS51227 has built-in leading edge blanking circuitry that blocks out the first 150 ns (typ) of each current pulse. This feature removes the leading edge spikes without altering the current waveform. Blanking is disabled when the COMP pin voltage exceeds 3.0 V (typ). This feature reduces the minimum duty cycle during an output short or overload condition. DESIGN GUIDELINES CT GATE Programming Oscillator Frequency Figure 5. Pulse Width Modulated By Input Voltage With Constant Output Voltage The switching frequency is set by the capacitor connected to the CT pin. The CT pin voltage oscillates between 1.0 V and 2.0 V. The ratio of the charge and discharge currents sets the maximum duty cycle to be 90%. Use the following equation to select CT, CT + 9.027 107 fs The feed forward feature can also be employed to implement volt-second clamping, which limits the maximum product of input voltage and turn on time. This clamp is used in circuits, such as Forward and Flyback converters, to prevent the transformer from saturating. The calculation for volt-second clamping is presented in the Design Guidelines section. where: fs = Switching frequency CT = Capacitance in pF http://onsemi.com 6 CS51227 When CT is less than 100 pF, parasitic capacitance associated with the CT pin starts to impact frequency accuracy. Figure 6 shows typical oscillator frequency vs. CT value. 1000 900 Oscillator Frequency (kHz) 800 700 600 500 400 300 200 100 0 0 200 400 CT (pF) 600 800 error amplifier and ramp signal can contribute to DC regulation. Select Feedback Voltage Divider As shown in Figure 7, the voltage divider output feeds the FB pin which connects to the inverting input of the error amplifier. The non-inverting input of the error amplifier is connected to a 1.263 V reference voltage. The FB pin has an input current which has to be taken into account for accurate output voltage programming. The following equation can be used to calculate the R1 and R2 value: R2 R1 ) R2 VOUT + 1.263 * where is the correction factor + Ri ) R1 R2 Ier Figure 6. Typical Performance Characteristics: Oscillator Frequency vs. CT Component Selection for Feed Forward Ramp Ri = DC resistance between the FB pin and the voltage divider output, as shown in Figure 7. Ier = FB pin input current, 1.3 A typical. VOUT R1 Ier COMP Error Amplifier + - 1.263 V + - FB Ri R2 FF discharge voltage and FF maximum voltage limit the maximum voltage rise on the FF pin to 1.5 V typical. This provides the volt-second clamp feature when the FF pin is driven by the input line. If the line voltage is much greater than the FF pin voltage, the charge current is approximately equal to VIN/R where R is the resistor connecting the FF pin and input line. The voltage second clamp then has the form of: VIN TON + 1.5 R CFF One can select RCFF to prevent magnetic devices from saturating. In a buck or forward converter, the error amplifier output VCOMP is equal to: V VCOMP + OUT NR TS ) 0.3V CFF Figure 7. The Feedback Voltage Divider Design Has to Consider the Error Amplifier Input Current Thermal Management where: N = Transformer turns ratio (use 1 for buck converter) TS = Switching period This equation shows that the error amplifier output is independent of the input voltage. Therefore, the system does not rely on the error amplifier to respond to line variations. This excludes the delay associated with the error amplifier. The line regulation is also greatly improved because both The CS51227 will enter thermal shutdown when the junction (die surface) temperature exceeds 150C, typical. 10C typical thermal hysteresis will prevent part cycling, or a "chattering" startup near the shutdown temperature. Junction temperature is a function of the ambient temperature, thermal resistance of the die and package, and the power dissipated by the package and leads. http://onsemi.com 7 CS51227 PACKAGE DIMENSIONS SO-8 D SUFFIX CASE 751-07 ISSUE V -X- A 8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 B 1 4 S 0.25 (0.010) M Y M -Y- G C -Z- H D 0.25 (0.010) M SEATING PLANE K N X 45 _ 0.10 (0.004) M J ZY S X S PACKAGE THERMAL DATA Parameter RJC RJA Typical Typical SO-8 45 165 Unit C/W C/W ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 CS51227/D |
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