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| CDB53L32A Evaluation Board for CS53L32A Features l Demonstrates Description The CDB53L32A evaluation board is an excellent means for quickly evaluating the CS53L32A 24-bit, stereo A/D converter. Evaluation requires a digital signal analyzer, an analog signal source, a PC for controlling the CS53L32A (in control port mode) and a power supply. Also included is a CS8404A digital audio interface transmitter which generates AES/EBU, S/PDIF, and EIAJ-340 compatible audio data. The digital audio data is available via RCA phono and optical connectors. recommended layout and grounding arrangements l CS8404A generates AES/EBU, S/PDIF, and EIAJ-340 compatible digital audio l Requires only an analog signal source and power supplies for a complete Analog-toDigital-Converter system l Patch Area ORDERING INFORMATION CDB53L32A Evaluation Board 8PIUSPG QPSU 8T'##6 6I6GPB 8T$"G"!6 ADIQVU 6@T@7VA TQ9DA US6ITHDUU@S TQ9DA PVUQVU DPAAPS 8GP8FT 6I9A96U6 Preliminary Product Information P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2001 (All Rights Reserved) AUG `01 DS513DB3 1 CDB53L32A TABLE OF CONTENTS 1. CDB53L32A SYSTEM OVERVIEW .......................................................................................... 3 2. CS53L32A ANALOG TO DIGITAL CONVERTER ................................................................... 3 3. CS8404A DIGITAL AUDIO TRANSMITTER ............................................................................ 3 4. CS8404A DATA FORMAT ....................................................................................................... 3 5. INPUT/OUTPUT FOR CLOCKS AND DATA ........................................................................... 3 6. POWER SUPPLY CIRCUITRY ................................................................................................. 3 7. GROUNDING AND POWER SUPPLY DECOUPLING ............................................................ 3 8. CONTROL PORT SOFTWARE ................................................................................................ 4 9. CDB53L32A PERFORMANCE PLOTS .................................................................................... 4 10. ERRATA ................................................................................................................................. 4 LIST OF FIGURES Figure 1. System Block Diagram and Signal Flow .......................................................................... 6 Figure 2. Channel 1 Analog Input.................................................................................................... 7 Figure 3. Channel 2 Analog Input.................................................................................................... 8 Figure 4. CS53L32A........................................................................................................................ 9 Figure 5. Control Port Interface ..................................................................................................... 10 Figure 6. Level Shift ...................................................................................................................... 11 Figure 7. I/O for Clocks and Data.................................................................................................. 12 Figure 8. CS8404A Digital Audio Interface.................................................................................... 13 Figure 9. Reset Circuit and Clock Generation............................................................................... 14 Figure 10. Digital Audio Outputs ................................................................................................... 15 Figure 11. Power Supply ............................................................................................................... 16 Figure 12. Frequency Response at 1.8 V...................................................................................... 17 Figure 13. Frequency Response at 3.0 V...................................................................................... 17 Figure 14. THD+N versus Amplitude at 1.8 V ............................................................................... 17 Figure 15. THD+N versus Amplitude at 3.0 V ............................................................................... 17 Figure 16. FFT of 1 kHz Sine Wave at -1 dBFS and 1.8 V ........................................................... 17 Figure 17. FFT of 1 kHz Sine Wave at -1 dBFS and 3.0 V ........................................................... 17 Figure 18. Silkscreen Top ............................................................................................................. 18 Figure 19. Top Side....................................................................................................................... 19 Figure 20. Bottom Side.................................................................................................................. 20 LIST OF TABLES Table 1. System Connections ........................................................................................................ 4 Table 2. CDB53L32A Jumper and Switch Settings ........................................................................ 5 Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/ I2C is a registered trademark of Philips Semiconductors. Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I2C Patent Rights to use those components in a standard I2C system. SPI is a registered trademark of International Business Machines Corporation. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com. 2 DS513DB3 CDB53L32A 1. CDB53L32A SYSTEM OVERVIEW The CDB53L32A evaluation board is an excellent means of quickly evaluating the CS53L32A. The CS8404A digital audio interface transmitter provides an easy interface to digital audio signal analyzers including the majority of digital audio test equipment. The CDB53L32A schematic has been partitioned into 10 schematics shown in Figures 2 through 11. Each partitioned schematic is represented in the system diagram shown in Figure 1. Notice that the system diagram also includes the interconnections between the partitioned schematics. 5. INPUT/OUTPUT FOR CLOCKS AND DATA The evaluation board has been designed to allow interfacing to external systems via the 10-pin header, HDR8. The schematic for the clock/data input/output is shown in Figure 7. The CDB53L32A allows some flexibility as to the generation of MCLK. When in slave mode you may internally generate MCLK on board and receive SLCK and LRCK by setting HDR 9, 10, and 11 to `EXT'. Generating MCLK internally on the CDB53L32A while in slave mode improves performance due to jitter effects which can occur from long cable lengths used to transmit MCLK to the CDB53L32A. If you wish to provide MCLK externally set HDR 9 and 10 to `INT' and HDR 11 to `EXT' In Master mode if you wish to provide MCLK externally via HDR8 set HDR 9 and 10 to `EXT' and HDR 11 to `INT'. 2. CS53L32A ANALOG TO DIGITAL CONVERTER A description of the CS53L32A is included in the CS53L32A datasheet. 3. CS8404A DIGITAL AUDIO TRANSMITTER The system generates and encodes standard S/PDIF data using a CS8404A Digital Audio Transmitter, Figure 8. The outputs of the CS8404A are RS422 compatible differential line drivers. The operation of the CS8404A and a discussion of the digital audio interface are included in the CS8404A datasheet. Note: The CS8404 can not be the master clock source for the board 6. POWER SUPPLY CIRCUITRY Power is supplied to the evaluation board by four binding posts (GND, +5 V, VA, VL), see Figure 11. The +5 V input supplies power to the +5 V digital circuitry (VDD) and the amplifiers (VAA), while the two +1.8/+3.3 V inputs supply power to the VA and VL pins of the CS53L32A and to the level shifter circuits. WARNING: Please refer to the CS53L32A datasheet for allowable voltages levels. 4. CS8404A DATA FORMAT The CS8404A data format can be set with headers M0, M1, and M2 as described in the CS8404A datasheet. The format selected must be compatible with the data format of the CS53L32A, as shown in the CS53L32A datasheet. Please note that the CS8404A does not support all the possible modes of the CS53L32A. 7. GROUNDING AND POWER SUPPLY DECOUPLING The CS53L32A requires careful attention to power supply and grounding arrangements to optimize performance. Figure 4 details the power distribution used on this board. The decoupling capacitors are located as close to the CS53L32A as possible. Extensive use of ground plane fill in the evaluation board yields large reductions in radiated noise. DS513DB3 3 CDB53L32A 8. CONTROL PORT SOFTWARE The CDB53L32A is shipped with Windows based software for interfacing with the CS53L32A control port via the DB25 connector, J2. The software can be used to communicate with the CS53L32A in either SPI or I2C mode; however, in SPI mode the CS53L32A registers are write-only. SDATA and the center stake of HDR6. This resistor satisfies the stand-alone pullup/pulldown requirement on SDOUT to choose between master/slave operation of the CS53L32A. - Pin 15, CBL, on the CS8404A is now floating, instead of being connected to ground. CBL is the channel status block output for the CS8404 and should have been floating in the original schematic. - Pin 4 on U5 was disconnected in order to resolve bus contention issues on the SCLK line. Because of this modification the CS8404 can no longer act as Master for the CS53L32A. In order to test the CS53L32A in slave mode, provide external clocks to HDR8. CDB53L32A B.0 There are no errata for the CDB53L32A B.0. 9. CDB53L32A PERFORMANCE PLOTS The CDB53L32A performance plots, shown if figures 12 through 16, were generated using the Audio Precision System Two Cascade. All tests were performed at a sampling rate of 48 kHz and with VA and VL as indicated, and the +5 V post at 5 V. 10. ERRATA CDB53L32A A.0 - A 47.5kohm resistor has been added on the bottom side of the board between the testpoint labled CONNECTOR +5 V VA VL GND AIN_L1 AIN_R1 AIN_L2 AIN_R2 Parallel Port HDR8 HDR7 Optical Output Coax Output INPUT/OUTPUT Input Input Input Input Input Input Input Input Input/Output Input/Output Input/Output Output Output + 5 Volt power SIGNAL PRESENT + 1.8 to + 3.3 Volt power for the CS53L32A + 1.8 to +3.3 Volt power for the CS53L32A Ground connection from power supply Analog input 1 left channel Analog input 1 right channel Analog input 2 left channel Analog input 2 right channel Parallel connection to PC for SPI / I2C control port signals I/O for master, serial, left/right clocks and serial data I/O for SPI / I2C control port signals Digital audio output Digital audio output Table 1. System Connections 4 DS513DB3 CDB53L32A JUMPER / SWITCH SW1 HDR1 HDR2 HDR3 HDR4 HDR5 Reset PURPOSE CS8404A Mode Select M0 CS8404A Mode Select M1 CS8404A Mode Select M2 CS8404A clock master/slave select CS8404A MCLK Divider POSITION HI HI *LOW HI *LOW *HI LOW *S M x1 */2 /4 FUNCTION SELECTED Resets the CDB53L32A Rev A See CS8404A datasheet for details See CS8404A datasheet for details See CS8404A datasheet for details LRCK, SCLK are inputs to the CS8404A LRCK, SCLK are outputs from the CS8404A MCLK goes directly into CS8404 (Fs = 96 kHz) MCLK is divided by two prior to CS8404 (Fs = 48 kHz) MCLK is divided by four prior to CS8404 (Fs = 24 kHz) CS53L32A in Master mode CS53L32A in Slave mode Master clock from on-board oscillator Master clock externally supplied via HDR8 LRCK/SCLK is output on HDR8 LRCK/SCLK is input on HDR8 Enable/Disable the control port See CS53L32A datasheet for details See CS53L32A datasheet for details See CS53L32A datasheet for details HDR6 HDR9/HDR10 HDR11 HDR12 HDR13 HDR14 HDR15 CS53L32A Master/Slave Select Master Clock Source Select LRCK/SCLK Source Select Control Port Enable AD0/CS/DIV SDA/CDIN/DIF SCL/CCLK/CHSEL *M S *INT EXT *INT EXT Disable *Enable *HI LOW *HI LOW *HI LOW Notes: *denotes default factory settings Table 2. CDB53L32A Jumper and Switch Settings DS513DB3 5 6 CS8404A CS53L32A SHIFTER FIG 4 FIG 6 AUDIO INTERFACE LEVEL DIGITAL DIGITAL OUTPUTS FIG 10 FIG 8 RESET CIRCUIT CONTROL PORT FIG 5 FIG 9 FIG 7 I/O FOR CLOCKS AND DATA CHANNEL 1 INPUTS FIG 2 CHANNEL 2 INPUTS FIG 3 CDB53L32A Figure 1. System Block Diagram and Signal Flow DS513DB3 DS513DB3 C45 10PF COG 7.87K R7 C51 U4 J3 AIN_L1 R5 7.87K 7 6 1 NC NC 3 4 R32 150 C55 10UF 2 5 AIN_L1 10UF + MC33202D R35 100K C8 .01UF X7R R13 VAA C53 10UF GND VAA C30 .1UF GND GND GND HDR31 1 2 GND R12 7.87K GND 7.87K GND GND X7R C52 U4 1 J4 R14 7.87K 2 AIN_R1 3 V+ GND 8 1 3 NC 4 R31 150 C58 10UF C12 .01UF X7R NC 2 AIN_R1 10UF R36 100K + MC33202D 4 V- GND GND R10 7.87K GND GND C46 10PF COG CDB53L32A Figure 2. Channel 1 Analog Input 7 8 C47 10PF COG 7.87K R15 C56 U6 7.87K 6 J6 R17 AIN_L2 7 1 NC R34 150 C59 10UF 3 4 NC 5 2 AIN_L2 10UF + MC33202D R38 100K C14 .01UF X7R GND GND GND HDR32 1 2 GND VAA GND C31 .1UF GND X7R C54 U6 1 J7 R18 7.87K 2 AIN_R2 3 V+ GND 8 1 R33 3 NC 4 NC 150 C60 10UF C13 .01UF X7R 2 AIN_R2 10UF R37 100K + MC33202D 4 V- GND GND R16 GND 7.87K GND C48 10PF COG CDB53L32A DS513DB3 Figure 3. Channel 2 Analog Input VA VL DS513DB3 10UF C9 10UF C4 C1 .1UF X7R GND C2 .1UF X7R GND RST /RST_C AIN-L1 AIN_L1 CS53L32A U1 1 VL MCLK VQ AIN_L1 AIN_R1 REF_GND AIN_L2 AIN_R2 FILT+ AFILTL AFILTR 17 16 15 14 13 12 11 18 SCLK SDOUT VA GND LRCK AD0/CS/DIV SDA/CDIN/DIF SCL/CCLK/CHSEL 19 RST 20 2 3 4 5 6 7 8 9 10 AIN-R1 AIN_R1 MCLK MCLK_C SCLK C6 .1UF X7R C10 1UF SCLK_C SDATA SDATA_C LRCK LRCK_C C7 .1UF X7R 1UF C57 GND ADO/CS/DIV AD0/CS/DIV SDA/CDIN/DIF SDA/CDIN/DIF SCL/CCLK/CHSEL CS53L32A C20 1000PF COG GND GND GND AIN-L2 C11 AIN-R2 1000PF COG AIN_R2 AIN_L2 SCL/CCLK/CHSEL CDB53L32A Figure 4. CS53L32A 9 HDR1X3 HDR13 1 2 3 HDR1X3 HDR15 1 2 3 VCC X7R 3 6 8 11 7 .1UF HDR1X3 HDR14 1 2 3 AD0/CS/DIV SN74HCT125D GND GND CDB53L32A Figure 5. Control Port Interface SCL/CCLK/CHSEL GND SDA/CDIN/DIF 10 VDD VDD CONTROL PORT VL C17 U8 U18 RN1 1K HDR12 DISABLE ENABLE VCC 1Y GND 6 8 11 7 1 3 5 7 3 14 1 2 3 .1UF DB25M_RA J2 GND 1 11 /OE CLK 2Y 3Y 4Y GND VDD 74LVC125AD SDA/CDIN/DIF SCL/CCLK/CHSEL AD0/CS/DIV R8 R9 R11 2 3 4 5 6 7 8 9 4.7K 4.7K 4.7K 1D 2D 3D 4D 5D 6D 7D 8D VCC GND C15 GND R28 2K GND R27 2K .1UF SN74HC574DW GND 20 10 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 19 18 17 16 15 14 13 12 1 2 4 5 10 9 13 12 1/G 1A 2/G 2A 3/G 3A 4/G 4A 2 4 6 8 SCL/CCLK/CHSEL AD0/CS/DIV SDA/CDIN/DIF HDR7 R29 2K GND INTERFACE CONNECTOR VDD U17 14 /R /RESET 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 VL C16 GND HI GND LOW HI LOW HI LOW GND 1Y 2Y 3Y 4Y SDA_+5 R6 4.7K 4.7K R19 1 2 4 5 10 9 13 12 1/G 1A 2/G 2A 3/G 3A 4/G 4A DS513DB3 CDB53L32A VDD VDD C39 GND .1UF VDD 14 R26 1K U11 .1UF C25 VCC CLK_CTL SCLK_INV M/S 1 U5 2 SN74HCT04D 3 4 LRCK_J SCLK_A SCLK_J M/S SCLK_A SCLK_84 5 6 1 2 4 5 10 9 13 12 VCC 1/G 1A 2/G 2A 3/G 3A 4/G 4A 1Y 2Y 3Y 4Y GND 74HC125 8 14 3 6 GND LRCK SCLK SCLK_84 11 7 SCLK_INV 9 8 11 10 GND 13 12 GND 7 GND LEVEL SHIFTER VL R4 10K R3 10K VDD LRCK_J U3 GND C40 1 2 3 4 5 6 7 STDA GNDA OUTA VCC INB+ INBSTATB STATA INAINA+ LP OUTB GNDB STOB C29 V_REF .1UF .1UF GND GND X7R 14 13 12 11 10 9 8 V_REF LRCK_C SCLK_J MAX977_SO14 CLK_CTL VL SCLK_C V_REF .1UF C3 U20 1 2 4 5 10 9 13 12 X7R 14 3 6 8 11 7 GND GND MCLK_C SCLK_C /RST_C LRCK_C 1 2 3 4 5 6 7 STDA GNDA OUTA VCC INB+ INBSTATB GND VCC 1/G 1A 2/G 2A 3/G 3A 4/G 4A 1Y 2Y 3Y 4Y GND 74LVC125AD MCLK SCLK /RST LRCK SDA_+5 VDD U22 STATA INAINA+ LP OUTB C5 GND GND .1UF GND X7R 8 GNDB STOB 14 13 12 11 10 9 V_REF SDA/CDIN/DIF SDATA VL SDATA_C V_REF HDR1X3 HDR6 1 2 3 MAX977_SO14 53L32A S GND M GND GND Figure 6. Level Shift DS513DB3 11 CDB53L32A IO INTERFACE VDD INT CLK EXT CLK HDR1X3 HDR11 1 2 3 U14 1 13 3 4 5 6 G1 G2 A1 A2 A3 A4 B1 B2 B3 B4 VCC GND 11 10 9 8 14 7 LRCK SCLK GND VDD SDATA_HDR 10 8 6 4 2 9 7 5 3 1 HDR1X3 HDR10 INT 1 2 EXT 3 HDR1X3 HDR9 1 EXT 2 3 INT SN74HC243D C26 .1UF SDATA LRCK SCLK MCLK GND MCLK HDR8 GND MCLK Figure 7. I/O for Clocks and Data 12 DS513DB3 FSYNC SDATA 10UF 18 .1UF SCK MCK DS513DB3 CS8404 VDD SCLK_84 SDATA M 8404 S M/S HDR1X3 HDR4 1 2 3 U13 LRCK_84 VDD GND LRCK SCLK 19 7 8 3 4 5 6 11 10 9 8 14 7 6 1 13 VDD G1 G2 VDD LRCK_84 SCLK_A C50 C27 VD+ 24 1 2 A1 A2 A3 A4 VCC GND SN74HC243D B1 B2 B3 B4 .1UF C24 GND 0CRE/FC1 1 C7/C3 1 PRO 3 4 12 14 13 GND 15 CBL 1 C1/FC0 9 V 0C6/C2 1 C9/C15 1 EM0/C9 GND GND 10 C U U12 GND 16 11 1 EM1/C8 RST CS8404A_CS 21 M0 M1 TXP TXN X1 DIV/2 DIV/4 VDD U15 1 3 5 17 2 4 6 20 /RST TXP TXN MCLK VDD 23 22 M2 5 HI LOW M2 HDR1X3 HDR1 1 2 3 HDR1X3 HDR3 1 2 3 HDR1X3 HDR2 1 2 3 HDR5 14 VDD M0 M1 VCC 1Q 1/Q 2Q 2/PRE 2CLK 2D 2/CLR 2/Q GND MC74HC74D MCLK 5 6 9 GND GND HDR34 1 2 4 3 2 1 1/PRE 1CLK 1D 1/CLR 10 11 12 13 C28 .1UF 8 7 GND GND GND GND CDB53L32A Figure 8. CS8404A Digital Audio Interface 13 CDB53L32A VDD LED_CMD2821SRC_T1 D3 5.1K MCLK GEN / RESET /RST R1 RESET S1 VDD VDD 3 C49 Vcc 2 RST GND 1 100PF COG GND C19 .1UF U7 DS1233-10 D11 1N4001 GND U16 1 2 4 5 10 9 13 12 14 3 6 8 11 7 GND VCC 1/G 1A 2/G 2A 3/G 3A 4/G 4A 1Y 2Y 3Y 4Y GND SN74HCT125D /RESET /R SDATA SDATA_HDR GND VDD GND X1 14 VCC 8 C44 1UF C18 MCLK .1UF 7 GND 12.2880MHZ GND Figure 9. Reset Circuit and Clock Generation 14 DS513DB3 CDB53L32A TR1 XFR_PE_67129600 C34 TXP R30 .1UF 2 1 6 X7R 374 R2 90.9 3 5 4 J5 1 2 3 NC 4 NC GND GND TXN VDD 4 TOTX173 5 R25 C33 6.2K .1UF 3 2 1 6 GND OPT1 GND GND GND Figure 10. Digital Audio Outputs DS513DB3 15 CDB53L32A VDD L1 +5 J10 Z1 P6KE6V8P C38 47UF C23 .1UF FERRITE C32 .1UF C36 VAA 47UF GND J9 GND +1.8+3.3 J11 D2 1N4001 C35 47UF C21 .1UF VL GND +1.8+3.3 J8 D1 1N4001 C37 47UF C22 .1UF VA GND Figure 11. Power Supply 16 DS513DB3 CDB53L32A +2 +1.5 +1 d B F S +0.5 -0 -0.5 -1 -1.5 -2 20 50 100 200 500 Hz 1k 2k 5k 10k 20k +2 +1.5 +1 d B F S +0.5 -0 -0.5 -1 -1.5 -2 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 12. Frequency Response at 1.8 V Figure 13. Frequency Response at 3.0 V -70 -72.5 -75 -77.5 d B F S -80 -82.5 -85 -87.5 -90 -92.5 -95 -60 -50 -40 -30 dBr -20 -10 +0 d B F S -70 -72.5 -75 -77.5 -80 -82.5 -85 -87.5 -90 -92.5 -95 -60 -50 -40 -30 dBr -20 -10 +0 Figure 14. THD+N versus Amplitude at 1.8 V Figure 15. THD+N versus Amplitude at 3.0 V +0 -20 -40 d B F S -60 -80 -100 -120 -140 20 50 100 200 500 Hz 1k 2k 5k 20k d B F S +0 -20 -40 -60 -80 -100 -120 -140 20 50 100 200 500 Hz 1k 2k 5k 20k Figure 16. FFT of 1 kHz Sine Wave at -1 dBFS and 1.8 V Figure 17. FFT of 1 kHz Sine Wave at -1 dBFS and 3.0 V DS513DB3 17 CDB53L32A Figure 18. Silkscreen Top 18 DS513DB3 CDB53L32A Figure 19. Top Side DS513DB3 19 CDB53L32A Figure 20. Bottom Side 20 DS513DB3 * Notes * |
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