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Century Semiconductor Inc.
GENERAL DESCRIPTION CS8810 is a single chip general-purpose USB controller, which integrates USB 1.1 compliant transceiver. Together with product dependent firmware and software driver, this chip is able to fulfill diverse demand of end products. FEATURES (continued)
CS8810
General Purpose USB Device
* Four endpoints (CONTROL, INTERRUPT, BULKIN and BULK-OUT) are implemented * FIFO in each of IN and OUT endpoint is to support maximum bulk size (64 bytes) * Embedded microcontroller is responsible for executing USB and device dependent commands * Hardware driven interrupt improves latency and efficiency * 16K x 14 internal metal programmable ROM to meet various application demand * Accessible external memory provides viable development tool * Built-in USB transceiver * 4MHz crystal input with internal 12X multiplier * Optional serial EEPROM to store customized data * 3.3 Volt power with 5 Volt tolerant I/O * Low power with 0.35 m technology * 100-pin LQFP package
FEATURES * Combined with application specific firmware, this chip can be configured to support 1. USB to IDE/ATAPI peripheral devices, including CDROM, CDR/RW, HDD, ZIP drivers, LS120, Compact Flash, Smart Media cards, Disk on chip, etc. 2. USB to parallel port including SPP, EPP, ECP 3. USB to serial port
BLOCK DIAGRAM
DP
HOL P
USB transceiver SIE
LQD
IN FIFO OUT FIFO
U\
uP Internal ROM
GPIO[31:0]
DM
3U
External ROM
Century Semiconductor, Inc. Taiwan: No. 2, Industry East Rd. 3rd, Science-Based Industrial Park, Hsin-Chu, Taiwan Tel: 886-3-5784866 Fax: 886-3-5784349
USA: 1485 Saratoga Ave. #200 San Jose, CA, 95129 Tel: 408-973-8388 Fax: 408-973-9388
Sales@century-semi.com Sales@century-semi.com.tw www.century-semi.com Rev.0.4 May 2001 page 1 of 24
Century Semiconductor Inc.
PIN CONNECTION DIAGRAM
CS8810
100 99 98 97 96 95 94
93 92 91 90 89 88 87 86 85 84 83 82
81 80 79 78 77 76
GND VDD GPIO18 GPIO17 GPIO16 GPIO15 GPIO14 GPIO13 GPIO12 GND VDD VDD(INT) GND(INT) GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GND NC VDD GPIO5 GPIO4 GPIO3
LQD
CS8810
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
GPIO24 GPIO25 GPIO26 GPIO27 VDD GND GPIO28 GPIO29 GPIO30 GPIO31 USBSEL EEDO EEDI EECLK EECS VDD(USB) DP DM GND(USB)
U\ HOL P
GNDA VDDA FILTER XIN XOUT NC NC RESETn ROMDATA13 ROMDATA12 ROMDATA11 ROMDATA10 ROMDATA9 ROMDATA8 TESTCLK VDD(INT) GND(INT) ROMDATA7 ROMDATA6 ROMDATA5 ROMDATA4 ROMDATA3 ROMDATA2 NC NC
NC GPIO19 GPIO20 GPIO21 GPIO22 GPIO23
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
GPIO2 GPIO1 GPIO0 GND VDD ROMADDR13 ROMADDR12 ROMADDR10 ROMADDR11 ROMADDR9 ROMADDR8 ROMADDR7 ROMADDR6 ROMADDR5 ROMADDR4 GND VDD ROMADDR3 ROMADDR2 ROMADDR1 ROMADDR0 TESTMOD ROMSEL ROMDATA0 ROMDATA1
3U
Figure-1 100-pin LQFP
50
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PIN DESCRIPTION
Name USB XIN XOUT DP DM OUSBDP OUSBDM OUSBEN IUSBDP IUSBDM IUSBDATA USBSEL EEPROM EEDI EEDO EECLK EECS ROM ROMADDR[13:0] ROMDATA[13:0] ROMSEL MISC. TESTMOD RESETn FILTER TESTCLK DEVICE I/O GPIO[31:0] POWER VDD (USB) VDD (ANALOG) VDD (INT) VDD (OB) GROUND 10 pins I/O 4 pins I O I/O I/O O O O I I I I 4 pins I O O O 29 pins 0 I I 70-69, 67, 68, 66-61, 58-55 34-39, 43-48, 51-52 53 19 18 20 21 29 30 23 24 9 10 16 14 13 15 17 Crystal Input Crystal Output Data Plus of internal USB transceiver Data Minus of internal USB transceiver Output to DP to external USB transceiver Output to DM to external USB transceiver Output enable to external USB transceiver Input from DP of external USB transceiver Pin Description
CS8810
Data from differential output of external USB transceiver 0: internal USB transceiver 1: external USB transceiver
4 pins I I
3U
28 I/O 40 32 pins I/O 10 pins 22 27 41, 89 11, 59, 71, 79, 90, 99 16-13, 10-2, 98-92, 87-82, 78-73
HOL P
0: internal ROM 1: external ROM 54 33
LQD
Data Input from EEPROM Data Output to EEPROM EEPROM Clock EEPROM Chip Select External ROM Address External ROM Data 0: normal 1: internal ROM testing Power-on reset, active low Low pass filter for PLL Test mode clock Output only if internal PLL is used page 3 of 24
U\
Input from DM of external USB transceiver
Century Semiconductor Inc.
Name GND (USB) GND (ANALOG) GND (INT) GND (OB) I/O Pin 25 26 42, 88 12,60, 72, 81, 91, 100 Description
CS8810
3U
HOL P
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LQD
U\
Century Semiconductor Inc.
Recommended pin mapping PIN 0 Port A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 C2 C3 C4 C5 C6 C7 D0 D1 IDE Interface IORDn IOWRn CS0n CS1n A0 A1 A2 IDERSTn DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[8] DATA[9] DATA[10] DATA[11] CF Interface IORDn IOWRn CS0n CS1n A0 A1 A2 IDERSTn DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[8] DATA[9] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[0] DATA[0] DATA[0] DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] XFLAG ACKRVn PRPHREQ ACKn BUSYn INTR WAIT PRPHCLK PRPHACK SPP STROBEn AUTOLFn EPP WRITEn DATASTRn ECP HOSTCLK HOSTACK TD
CS8810
Serial
RTS
DTR
U\
DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] ADDSTRn RESETn BUFDIR
RD CTS DSR DCD RI
DATA[12] DATA[14] INTQ
DATA[13]
HOL P
DATA[10] DATA[11] DATA[12] DATA[13] INITn DATA[14] INTQ DATA[15] IORDY IO16n CD1n CD2n VDD GND INTQ BUFDIR IORDY IO16n VDD GND INTQ
LQD
PAPEREND SELECT ERRORn SELPTRn
RVREQn ACT1284 BUFDIR
DATA[15]
Italic: Bidirectional Shaded: Input only Others: Output only
3U
D2 D3 D4 D5 D6 D7
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FUNCTIONAL DESCRIPTION USB transceiver
CS8810
It converts between digital and analog domain of USB signals. Either internal or external USB transceiver can be selected. Internal USB transceiver only supports full speed mode. SIE USB Serial Interface Engine takes charge of all digital functions and interfaces with transceiver. Its main tasks include serializing and de-serializing bit string. To ensure data integrity, bit stuffing and de-stuffing is handled inside of SIE. After receiving interrupt and checking status flag, microcontroller executes appropriated instructions accordingly. IN FIFO
OUT FIFO
Microcontroller
An embedded microcontroller plays a critical role in the chip. Its tasks includes: 1. interprets USB command and interrupt of SIE 2. moves data between FIFO and device
3. moves data of control and interrupt packet 4. interfaces with EEPROM
If any CRC error occurs during data transfer from device to USB, microcontroller has to send the data of original bulk again. ROM
3U
ROM mainly contains instruction sets of microcontroller. Either internal or external ROM can be selected through ROMSEL pin. In the stage of application specific firmware development, external ROM provides a very useful environment.
HOL P
LQD
It is a 16-byte deep FIFO, in which data are de-serialized from USB SIE. Microcontroller moves data out from OUT FIFO.
U\
It is a 16-byte deep FIFO, in which data are moved by microcontroller. SIE serializes byte data then sends to USB transceiver.
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USB Device Endpoint Operation Endpoint 0
CS8810
Endpoint 0 is a control endpoint which responses USB standard and vendor specific commands. It is configured as a maximum eight bytes access. Endpoint 2 Endpoint 2 is an interrupt IN endpoint, which returns status every programmable polling interval. It is configured as an eight bytes access. Endpoint 3 Endpoint 3 is a bulk OUT endpoint, in which data is from USB host to device. After data are stored from EP3 FIFO, microcontroller moves them into internal SRAM until whole USB packet (64 bytes) is done. However, data will not be sent to device until handshake stage (CRC checking) passes. Endpoint 4
USB Generic Commands:
1. Get Device Status
setup stage:
bmReq 80h bReq 00 00
HOL P
wValue 00 D[15:8] 00 wValue 00 00 wValue 00 00
LQD
wIndex 00 00 wIndex 00 00 wIndex 80h or 00 00
Endpoint 4 is a bulk IN endpoint, which is responsible for data from device to USB host. The length of bulk can be programmed as 8, 16, 32 or 64 bytes. Microcontroller takes responsibility of transferring data from device to EP4 FIFO.
U\
wLength 02h 00
data stage:
D[7:0]
D:[7:2]: 6'b00_0000D D:[1]:1'b1: remote wakeup enable D:[0]:1'b1, self powered
2. Get Interface Status
setup stage:
bmReq 81h bReq 00
3U
wLength 02h 00
data stage:
D[7:0] 00
D[15:0] 00
3. Get EP0 Status
setup stage:
bmReq 82h bReq 00 wLength 02h 00
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data stage:
D[7:0] D:[7:6]: 7'b000_0000 1: EP0 Stalled D[15:8] 00
CS8810
4. Get EP2 Status
setup stage:
bmReq 82h bReq 00 00 wValue 00 82h wIndex 00 02h wLength 00
data stage:
D[7:0] D:[7:6]: 7'b000_0000 1: EP2 Stalled D[15:8] 00
5. Get EP3 Status
setup stage:
bmReq 82h bReq 00 00 wValue 00
U\
wIndex 03h 00 02h D[15:0] 00 wIndex 00 02h 00 84h D[15:0] 00 wIndex 01h 00 00 12h Offset4 (Class) 00h Offset12 (Release ID low) 02h Offset5 (Subclass) 00 Offset13 (Release ID high) 01h 01h 00 60h 01h
wLength 00
data stage:
D[7:0] D:[7:6]: 7'b000_0000 1:EP3 Stalled
setup stage:
bmReq 82h bReq 00
HOL P
wValue 00 wValue 00 Offset2 (USB Minor Rel. No) 10h Offset10 (Product ID low) 14h Offset3 (USB Major Rel. No) Offset11 ( Product ID high)
6. Get EP4 Status
LQD
wLength 00
data stage:
D[7:0]
D:[7:6]: 7'b000_0000 1: EP4 Stalled
setup stage:
bmReq 80h
3U
bReq 06h
7. Get Device Descriptor (Total 18 bytes)
wLength 00
data stage:
Offset0 (Length) 12h Offset8 (Vendor ID low) 22h
Offset1 (Type) 01h Offset9 (Vendor ID high) 0ah
Offset6 (protocol)
Offset7 (EP0 MaxSize) 08h
Offset14 Offset15 (Index of (Index of Manufacturer Product String) String) 02h
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Offset16 (Serial no.) 03h Offset17 (no. of configuration) 01h
CS8810
Note: Some of the data can be read from EEPROM where Serial EEPROM is optional for CS8810. Note: The A1 version has Release ID 0102h and the B0 version has Release ID 0201h.
8. Get Configuration Descriptor (Total 39 bytes)
setup stage:
bmReq 80h bReq 06h 00 wValue 02h 00 wIndex 00 27h wLength 00
data stage:
Offset0 (Length) 09h Offset8 (MaxPower) 30h
Offset1 (Type) 02h
Offset2 (Total length low) 27h
Offset3 (Total length high) 00
Offset4 (NumInterface) 01h
U\
Offset5 (ConfigNo) 01h Offset5 (Interface Class) 00h* 03h Offset4 (MaxPacket Size Lo) 08h Offset4 (MaxPacket Size Lo) 40h Offset4 (MaxPacket Size Lo) 40h
configuration descriptor:
Offset6 (StringIndex) 00
Offset7 (Attribute) A0h
interface 0 descriptor:
Offset0 (Length) 09h Offset8 (StringIndex) 00 Offset1 (Type) 04h
HOL P
Offset2 Offset3 (InterfaceNum) (Altlnterface) 00 00 Offset2 (EPAddr) 82h Offset3 (Attribute) 03h interrupt Offset2 (EPAddr) 03h Offset3 (Attribute) 02h bulk Offset2 (EPAddr) 84h Offset3 (Attribute) 02h bulk
LQD
Offset4 (NumEP) Offset6 (lnterface Subclass) 00h* Offset7 (Interface Protocol) 00 Offset5 (MaxPacket Size High) 00 Offset6 (Interval) 01h 05h Offset5 (MaxPacket Size High) 00 Offset6 (Interval) 00 05h Offset5 (MaxPacket Size High) 00 Offset6 (Interval) 00 05h
Note: The numbers there are for CS6565.
EP2 descriptor:
Offset0 (Length) 07h
EP3 descriptor:
Offset0 (Length) 07h Offset1 (Type)
EP4 descriptor:
Offset0 (Length) 07h Offset1 (Type)
3U
Offset1 (Type)
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Note: Some of the data can be read from EEPROM where Serial EEPROM is optional for CS8810.
CS8810
9. Get Configuration
setup stage:
bmReq 80h bReq 08h 00 wValue 00 00 wIndex 00 01h wLength 00
data stage:
Offset0 (Configure Value) 00 or 01h
10. Get Interface
setup stage:
bmReq 81h bReq 0Ah 00 wValue 00
LQD
wIndex 00 00 wIndex 00 00 00 wIndex 00 00 00 wIndex 00 00 00 wIndex 00 EP* 00
U\
Note: If the returned configuration value is 00h, it means the device is in address state. If the returned value is 01h, it means the device had been configured.
wLength 01h 00
data stage:
Offset0 (AltInterface) 00
11. Set Address
setup stage:
bmReq 00 bReq 05h
HOL P
wValue address wValue config wValue 00 wValue 00
wLength 00 00
12. Set Configuration setup stage:
bmReq 00 bReq 09h
wLength 00 00
config=0x00h: address state config=0x01h: configured state
13. Set Interface
setup stage:
bmReq 01h
3U
bReq 0Bh
wLength 00 00
CPU has to make sure the interface number and alternate interface are 0.
14. Set Endpoint Stall
setup stage:
bmReq 02h bReq 03h wLength 00 00
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Note: EP= 00h: Stall endpoint 0 Note: EP=82h: Stall endpoint 2 Note: EP=03h: Stall endpoint 3 Note: EP=84h: Stall endpoint 4
CS8810
15. Clear Endpoint Stall
setup stage:
bmReq 02h bReq 01h 00 wValue 00 EP* wIndex 00 00 wLength 00
Note: EP= 00h: Clear endpoint 0 stall Note: EP=82h: Clear endpoint 2 stall
Note: EP=84h: Clear endpoint 4 stall
16. Set Remote Wakeup Feature
setup stage:
bmReq 00 bReq 03h 01h wValue
LQD
wIndex 00 00 00 wIndex 00 00 00 wIndex 00 00 03h 04h wIndex 03h 09h 04h Offset2 (String)
U\
wLength 00 00 wValue wLength 00 00 wValue wLength 04h 00 Offset3 (LangID hi) wValue wLength TBD 00
Note: EP=03h: Clear endpoint 3 stall
17. Clear Remote Wakeup Feature
setup stage:
bmReq 00 bReq 01h 01h
18. Get String Descriptor 0, Language ID Code
setup stage:
bmReq 80h bReq 06h
data stage:
Offset0 (Length) 04h Offset1 (Type) 03h
19. Get String Descriptor 1, Manufacture String
setup stage:
bmReq 80h bReq 06h 01h
data stage:
Offset0 (Length) TBA Offset1 (Type) 03h
3U
09h
HOL P
00 Offset2 (LangID lo)
Copy from EEPROM or hard code
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20. Get String Descriptor 2, Product String
setup stage:
bmReq 80h bReq 06h 02h wValue 03h 09h wIndex 04h TBD
CS8810
wLength 00
data stage:
Offset0 (Length) TBA Offset1 (Type) 03h Offset2 (String) Copy form EEPROM or hard code
21. Get String Descriptor 3, Serial No.
setup stage:
bmReq 80h bReq 06h 03h wValue 03h 09h wIndex wLength 04h TBD 00
data stage:
Offset0 (Length) TBA Offset1 (Type) 03h Offset2 (String)
Vendor Specific Commands
setup stage:
bmReq C0h bReq F0h
HOL P
wValue 00 00 wValue 00 00 wValue 00 00
1. Get USB Single Register Data
LQD
wIndex 00 01h wLength 00 RegIdx wIndex RegIdx 00 02h wLength 00 wIndex 00 00 01h wLength 00
Copy from EEPROM or hard code
data stage:
Offset0 Reg[Regidx]
Note: Fetch single byte of data from USB register. This command is intended for internal debugging use.
2. Get EEPROM Single Word Memory Data
setup stage:
bmReq C0h bReq F2h
data stage:
Offset0 Low Byte MEM[Regidx] Offset1 High Byte MEM[RegIdx]
3. Get EEPROM Programming Status
setup stage:
bmReq C0h bReq F4h
3U
U\
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data stage:
Offset0 Status
CS8810
Fetch single byte of EEPROM programming status. If status=0, the programming is not finished yet.
4. Get EEPROM Validation Status
setup stage:
bmReq C0h bReq F6h 00 wValue 00 00 wIndex 00 01h wLength 00
data stage:
Offset0 Status
Fetch single byte of EEPROM validation status. If status=1, the content of EEPROM consists of correct signature and valid check sum.
5. Set USB Registers Single Write
setup stage:
bmReq 40h bReq F1h AndVal wValue
LQD
wIndex OrVal RegIdx 00 wIndex 00 DataHigh RegIdx wIndex 00 00 00
U\
wLength 00 00
Note: NewValue= ((OldValue and AndVal) or OrVal) and This feature is provided to set or clear register value more easily. Note: For B0 version, this vendor command can also be issued as 40_F0_AndVal_OrVal_RegIdx_00_00_00.
6. Set EEPROM Multiple Memory Data
setup stage:
bmReq 40h bReq F3h
HOL P
wValue DataLow wValue 00
wLength 00 00
Note: This vendor command can also be issued as 40_F2_DataLow_DataHigh_RegIdx_00_00_00 for B0
version.
7. Erase all EEPROM data
setup stage:
bmReq 40h bReq F5h
3U
wLength 00 00
Note: All contents in EEPROM will be erased and filled with 0xff. Note: For B0 version, this vendor command can also be issued as 40_F4_00_00_00_00_00_00.
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List of Command and Status Registers.
Register Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h Register Names IntEnReg1 IntEnReg2 IntStsReg1 IntStsReg2 EP0TxDataReg EP0RxDataReg EP2DataReg EP3DataReg EP4DataReg EP0RxCntReg EP3CntReg EPStsReg EP3WtrMrkReg EP4WtrMrkReg EP3MaxPktSzReg HskStsReg Register Description Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Status Register 1 Interrupt Status Register 2 EP0 Transmit FIFO Data Register EP0 Receive FIFO Data Register EP2 FIFO Data Register
CS8810
EP4 FIFO Data Register
EP0 Receive FIFO Count Register EP3 FIFO Count Register Endpoint Status Register
EP3 FIFO Water Mark Register EP4 FIFO Water Mark Register
EP3 Maximum Packet Size Register Handshake Status Register EP0 Status Register
EP0StsReg
DevAddrReg
FrmNumReg1 FrmNumReg2
EP3ReqCntReg EP4ReqCntReg EP3NakCntReg EP4NakCntReg
3U
EP4CntReg
HOL P
Device Address Value Register
Frame Number MSB Register
Frame Number LSB Register EP3 Request Count Register EP4 Request Count Register
EP3 NAK Count Register EP4 NAK Count Register EP4 FIFO Count Register
LQD
U\
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EP3 FIFO Data Register
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Address 00h: Interrupt Enable Register 1 (IntEnReg1)
Bits 7 Description EP4 Interrupt Enable. When set, this bit enables a local interrupt to be set when EP4 bulk data packet has been sent by the device. EP3 Interrupt Enable. When set, this bit enables a local interrupt to be set when EP3 bulk data packet has been received by the device. EP2 Interrupt Enable. When set, this bit enables a local interrupt to be set when EP2 interrupt data packet has been sent by device to Host. EP4 FIFO Water Mark Interrupt Enable. When set, this bit enables a local interrupt to be set when EP4 FIFO falls below the corresponding water mark. EP3 FIFO Water Mark Interrupt Enable. When set, this bit enables a local interrupt to be set when EP3 FIFO crosses the corresponding water mark. SETUP Interrupt Enable. When set, this bit enables a local interrupt to be set when Host transmits a setup packet. Read Yes Write Yes
CS8810
Default 0
6
Yes
Yes
0
5
Yes
Yes
0
4
Yes
Yes
0
3
U\
Yes Yes Yes Yes Read Yes Yes Yes Yes Yes Yes
Yes
0
1
EP0 Tx Interrupt Enable. When set, this bit enables a local interrupt to be set when EP0 data packet has been sent by the device to Host successfully. EP0 Rx Interrupt Enable. When set, this bit enables a local interrupt to be set when EP0 data packet has been received by the device from Host successfully.
LQD
2
Yes Yes
0 0
0
Yes
0
Address 01h: Interrupt Enable Register 2 (IntEnReg2) Bits 7 6 Description
HOL P
Write Yes Yes
Default 0 0
EP0 Error. When set, this bit enables a local interrupt to be set when there is a likelihood of EP0 error condition. USB Reset Interrupt Enable. When set, this bit enables a local interrupt to be set when Host transmits reset special signal to the device. SOF Interrupt Enable. When set, this bit enables a local interrupt to be set when a Start Of Frame packet is received by the device. USB Suspend Interrupt Enable. When set, this bit enables a local interrupt to be set when Host does not transmit any signals to the device for more than 5 ms. Reserved EP4 Data Toggle Mode. When set, this bit resets the Data Toggle bit to zero at the end of a USB transaction from EP4. When cleared the Data Toggle bit strictly toggles with every successful USB transaction. EP3 Data Toggle Mode. When set, this bit resets the Data Toggle bit to zero at the end of a USB Transaction from EP3. When cleared the Data Toggle bit strictly toggles with every successful USB transaction.
5
3U
Yes
0
4
Yes
0
3 2
0 Yes 0
1
Yes
0
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Bits 0 Description EP2 Data Toggle Mode. When set, this bit resets the Data Toggle bit to zero at the end of a USB Transaction from EP2. When cleared the Data Toggle bit strictly toggles with every successful USB transaction. Read Yes Write Yes
CS8810
Default 0
Address 02h: Interrupt Enable Register 1(IntStsReg1) Bits 7 Description EP4 Interrupt Status. This bit indicates when EP4 bulk data packet has been sent by device. This status bit is cleared by writing a 1. EP3 Interrupt Status. This bit indicates when a EP3 bulk data packet has been received by device. This status bit is cleared by writing a 1. Read Yes Write Yes/CLR Default 0
6
Yes
Yes/CLR
0
5
4
EP4 FIFO Water Mark Interrupt Status. This bit is set when the number of bytes in the EP4 FIFO is equal to the EP4 FIFO Water Mark, the another byte is sent to the Host from the FIFO. This status bit is cleared by writing a 1. EP3 FIFO Water Mark Interrupt Status. This bit is set when the number of bytes in the EP3 FIFO is equal to the EP3 FIFO Water Mark, and another byte is received from the Host into the FIFO. This status bit is cleared by writing a 1.
LQD
EP2 Interrupt Status. This bit indicates when the EP2 interrupt data packet has been sent by device to Host successfully when EP2 Toggle Mode bit is 0 otherwise this bit will be set for every transaction on this EP irrespective of handshake from Host. This status bit is cleared by writing a 1.
U\
Yes Yes Yes Yes Yes Read Yes Yes
Yes/CLR
0
Yes/CLR
0
3
Yes/CLR
0
2
SETUP Interrupt Status. This bit indicates when a setup transaction is received by device from Host. This status bit is cleared by writing 1. Note: It is recommended that the firmware should clear this bit and then read the EP0 receive FIFO data. Misc Interrupt Enable. This bit indicates when other miscellaneous interrupts have been set. It is OR-ed signal from the bits in Interrupt Status Registers 2. CPU has to look into Interrupt Status Register 2 to see exactly which interrupt has been set. Reserved
HOL P
Description
Yes/CLR
0
1
No
0
0
3U
0
Address 03h: Interrupt Status Register 2 (IntStsReg2) Bits 7 Write Yes/CLR Default 0
EP0 Transmit Interrupt Status. This bit indicates when a EP0 data packet has been sent by device to Host successfully. This status bit is cleared by writing a 1. EP0 Receive Interrupt Status. This bit indicates when a EP0 data packet has been received by device from Host successfully. This status bit is cleared by writing a 1.
6
Yes/CLR
0
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Bits 5 Description EP0 Error. This bit indicates when a EP0 error condition signal is detected by device. This status bit is cleared by writing 1. During a control transfer, when a direction change is detected by device and if CPU has not set the data stage complete bit, then the USB IP sets this bit. This bit is also set by the IP when the host requests for more than the pre-negotiated data in the control read transfer. USB Reset Interrupt Status. This bit indicates when a reset signal has been received by device from Host. This status bit is cleared by writing a 1. USB Suspend Interrupt Status. This bit indicates when a suspend signal has been received by device from Host. This status bit is cleared by writing a 1. SOF Interrupt Status. This bit indicates when a Start of Frame packet has been received by device. This status bit is cleared by writing a 1. Reserved Read Yes Write Yes/CLR
CS8810
Default 0
4
Yes
Yes/CLR
0
3
Yes
Yes/CLR
0
1-0
U\
Read No Read Yes Read No Read Yes Read No
2
Yes
Yes/CLR
0
0
Address 04h: EP0TxDataReg Bits 7-0
Description
LQD
Write Yes
Default 0
EP0 Transmit FIFO Data Register. This port is used for writing data to the EP0 Transmit Data FIFO. The FIFO is read by Host using control transfer.
Address 05h: EP0RxDataReg Bits 7-0
HOL P
Description Description Description Description
Write No
Default 0
EP0 Receive FIFO Data Register. This port is used for reading data to the EP0 Transmit Data FIFO. The FIFO is written by Host using control transfer.
Address 06h: EP2DataReg Bits 7-0
Write Yes
Default 0
EP2 FIFO Data Register. This port is used for writing data to the EP2 FIFO. The FIFO is read by Host using interrupt transfer.
Address 07h: EP3DataReg Bits 7-0
3U
Write No
Default 0
EP3 FIFO Data Register. This port is used for reading data from the EP3 FIFO. The FIFO is written by Host using bulk transfer.
Address 08h: EP4DataReg Bits 7-0 Write Yes Default 0
EP4 FIFO Data Register. This port is used for writing data to the EP4 FIFO. The FIFO is read by Host using bulk transfer.
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Address 09h: EP0RxCntReg Bits 7-0 Description EP0 Receive FIFO Count. This register returns the count of number of bytes in EP0 receive FIFO containing valid entries at the end of the current valid data packet transaction. Values range from 0 (empty) to 8 (full). Read Yes Write No
CS8810
Default 0
Address 0Ah: EP3CntReg Bits 7-0 Description EP3 FIFO Count. This register returns the count of number of bytes in EP3 FIFO containing valid entries at the end of the current valid data packet transaction. Values range from 0 (empty) to 16 (full) Read Yes Write No Default 0
Address 0Bh: Endpoint Status Register (EPStsReg) Bits 7 Description
U\
Read Yes Yes Yes Yes No Yes Yes Read Yes
Write Yes
Default 0
6
EP2 Stall. If this bit is set, Host bulk reads from the EP2 FIFO will result in a STALL acknowledge by the USB IP. No data will be returned to the Host. EP3 Maximum packet Size Error. This bit is set by USB IP when it detects a packet whose length is more than the maximum packet size for bulk transfer. EP3 Stall. If this bit is set, Host bulk writes to the EP3 FIFO will result in a STALL acknowledge by the USB IP. No data will be returned to the Host.
LQD
EP2 FIFO Data Valid. If set, this bit allows data in EP2 FIFO to be read by the next read from the Host. This bit is automatically cleared by Host read.
Yes
0
5
No
0
4
HOL P
Description
Yes
0
3
2
EP4 FIFO Data Valid. If set, this bit allows the data in the EP4 FIFO to be read by the next read from the Host. This bit is automatically cleared by a Host read. EP4 Stall. If this bit is set, Host bulk reads from the EP4 FIFO will result in a STALL acknowledge by the USB IP. No data will be returned to the Host. reserved
3U
EP4 FIFO Data Transfer Complete. CPU sets this bit after completing the total packet transfer from its memory to the EP4 FIFO, for the cases where the packet size is greater than the FIFO size, For cases where the packet size is less than or equal to the FIFO size it is set high by CPU along with data transfer to EP4 FIFO. USB IP resets this bit after completion of the current data transaction to the Host.
Yes
0
Yes
0
1
Yes
0
0
0
Address 0Ch: EP3WtrMrkReg Bits 7-0 Write Yes Default 08h
EP3 FIFO Water Mark Register. This register determines the threshold value at which the EP3 FIFO Water Mark Interrupt Status is set. The value is set by CPU depending on the configuration selected.
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Century Semiconductor Inc.
Address 0Dh: EP4WtrMrkReg Bits 7-0 Description EP4 FIFO Water Mark Register. This register determines the threshold value at which the EP4 FIFO Water Mark Interrupt Status is set. The value is set by CPU depending on the configuration selected. Read Yes Write Yes
CS8810
Default 08h
Address 0Eh: EP3MaxPktSzReg Bits 7-0 Description EP3 Maximum Packet Size Register. This register contains the value of the maximum packet size EP3 can handle. The actual value is taken to be eight times the value stored in this register. A value of 0 represents a Maximum Packet Size of 8 bytes, a value of 1 represents 16 bytes and so on. Read Yes Write Yes Default 07h
Address 0Fh: Handshake Status Register (HskStsReg) Bits 7 Description
U\
Read Yes Yes Yes Yes Yes Yes Yes Yes Read Yes
Write
Default 0
6
EP3 ACK. The last data packet received by EP3 was successfully acknowledged with an ACK. Writing a 1 clears this bit. Writing a 0 has no effect.
LQD
EP4 ACK. The last data packet transmitted by EP4 was successfully acknowledged with an ACK from the Host. Writing a 1 clears this bit. Writing a 0 has no effect.
Yes/CLR
Yes/CLR
0
5
4
EP3 FIFO Flush. Writing a 1 to this bit causes the EP3 FIFO to be flushed. Reading this bit always returns 0. Writing a 0 has no effect. EP2 FIFO Flush. Writing a 1 to this bit causes the EP2 FIFO to be flushed. Writing a 0 has no effect. Reading this bit always returns 0. EP0 Tx FIFO Flush. Writing a 1 to this bit causes the EP0 transmit FIFO to be flushed. Reading this bit always returns 0. Writing a 0 has no effect. Status Stage. This bit is set by the USB IP, when the host changes the direction in the data stage of a control transfer before CPU sets the control transfer complete bit, i.e. when host initiates the status stage prematurely. This bit is cleared by CPU by writing a 1 in this location. Suspend Control. If set, this bit indicates that there is a pending Suspend request from the Host. Writing a 1 clears this bit and causes the USB IP to enter suspended mode.
HOL P
Description
EP4 FIFO Flush. Writing a 1 to this bit causes the EP4 FIFO to be flushed. Writing a 0 has no effect. Reading this bit always returns 0.
Yes/CLR
0
Yes/CLR
0
3
Yes/CLR
0
2
Yes/CLR
0
1
3U
Yes/CLR
0
0
Yes/CLR
0
Address 10h: EP0 Status Register (EP0StsReg) Bits 7 Write No Default 0
EP0 Maximum Packet Size Error. This bit is set by the USB IP when it detects a packet for EP0 whose length is more than the maximum packet size.
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Century Semiconductor Inc.
Bits 6 Description EP0 Tx FIFO Data Valid. If set, this bit allows data in the EP0 TX FIFO to be read by the next read from the Host. This bit is automatically cleared by Host read. EP0 Stall. If this bit is set, the control transfer data phase writes or reads to the EP0 FIFO will result in a STALL acknowledge by the USB IP. Control Transfer Complete. CPU set this bit after successful completion of data phase of a control transfer. USB IP resets this bit after completing the status phase of transfer. Control Transfer In Progress. USB IP sets this bit when a valid SETUP token is received. USB IP resets the bit after completion of the control transfer. Reserved Read Yes Write Yes
CS8810
Default 0
5
Yes
Yes
0
4
No
Yes
0
3
Yes
No
0
1
USB Enable. CPU sets this bit after completing the power on reset or USB IP reset initialization, when all the default values of registers are written by CPU. Device listens to USB traffic only after this bit is set.
U\
Yes Yes Read Yes Read Yes Yes Read Yes
2
Yes
0
0
Address 11h: Device Address Register (DevAddrReg) Bits 7-0 Description
HOL P
Description Description
Device configured. CPU sets this bit after initial configuration of the device is completed by the Host and the Device moves to USB defined CONFIGURED state. Before setting the bit, CPU writes the Host assigned Device address value, EP data transfer types, maximum data packet sizes into the respective registers. Only after CPU sets this bit, the device responds to USB transactions to EPs other than EP0. When this bit is reset the USB IP responds to USB transactions to EP0. This bit is reset on power-on, USB IP reset and USB reset.
LQD
Yes
0
Write Yes
Default 0
The Address value assigned by Host. This register holds the address for the USB function. During bus enumeration CPU writes in to this register a unique value assigned by Host via SET ADDRESS command. Only the least 7-bits are used.
Bits 7-3 2-0
3U
Address 12h: Frame Number Register 1 (FrmNumReg1)
Write No No
Default 0 0
Reserved
Frame Counter MSB. This register contains the most significant bits of the frame number counter from the most recent SOF packet.
Address 13h: Frame Number Register 2 (FrmNumReg2) Bits 7-0 Write No Default 0
Frame Counter LSB. This register contains the least significant bits of the frame number counter from the most recent SOF packet.
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Century Semiconductor Inc.
Address 14h: EP3 Request Count Register (EP3RegCntReg)
Bits 7-0 Description The register counts the number of EP3 request from host within each 1ms interval and is used for statistic purpose. This byte could be sent back as the 5th byte of interrupt transfer for performance tuning. Read Yes Write No
CS8810
Default 0
Address 15h: EP4 Request Count Register (EP4RegCntReg) Bits 7-0 Description The register counts the number of EP4 request from host within each 1ms interval and is used for statistic purpose. This byte could be sent back as the 6th byte of interrupt transfer for performance tuning. Read Yes Write No Default 0
Address 16h: EP3 NAK Count Register (EP3NakCntReg) Bits 7-0 Description
U\
Read Yes Read Yes Read Yes
Write No
Default 0
Address 17h: EP4 NAK Count Register (EP4NAKCntReg) Bits 7-0 Description
LQD
The register counts the number of EP3 NAK response from host within each 1ms interval and is used for statistic purpose. This byte could be sent back as the 7th byte of interrupt transfer for performance tuning.
Write No
Default 0
Address 18h: EP4CntReg Bits 7-0
HOL P
Description
The register counts the number of EP4 request from host within each 1ms interval and is used for statistic purpose. This byte could be sent back as the 8th byte of interrupt transfer for performance tuning.
Write No
Default 0
3U
EP4 FIFO Count. This register returns the count of number of bytes in EP4 FIFO containing valid entries at the end of the current valid data packet transaction. Values range from 0 (empty) to 16 (full).
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Century Semiconductor Inc.
Data Storage Mapping at EEPROM
The serial EEPROM used will be Fairchild FM93C46-compatible type.
CS8810
Individual developer can arbitrarily use the EEPROM contents from address 0x04. The first 4 words are reserved
Low 00h-03h 04h-07h 08h-0Bh 0Ch-0Fh 10h-13h 14h-17h 18h-1Bh 1Ch-1Fh 20h-23h 24h-27h 28h-2Bh 2Ch-2Fh 30h-33h 34h-37h 38h-3Bh 3Ch-3Fh A5h 10 14 09 30 00 01 07 00 00 1c 79 1e 6e 0e 00 High 5Ah 01 60 02 09 00 07 05 00 00 03 20 03 74 03 00 Low C3h 00 02 27 04 07 05 84 00 00 43 53 55 72 30 00 High 3Ch 00 01 00 00 05 03 02 00 00 65 65 6f Low A5h 00 01 01 00 82 02 40 High 40h 08 02 01 03 03 40 00 Low ACh 22 03 00 00 08 00 00 00 00 75 2e 43 65 30 00 High F6h 0A 01 A0 00 00 00 00 00 6C 72 00 6f 72 30 00
LQD
6e 6d 6c 53 42 30 30 00 00
3U
HOL P
by Century Semiconductor Inc. as signature words. The contents shown here is just an example.
U\
00 00 00 00 74 69 20 6c 30 00
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Century Semiconductor Inc.
PACKAGE OUTLINE (100-pin LQFP)
D D1
100 76
CS8810
1
75
25
LQD
51
U\
E1 E 1
26
HOL P
e b
L1
L
50
A2 A1
A
c
Symbol A A1 A2 b c D D1 E E1 e L L1 1
Dimensions in Millimeters NOM 1.40 0.22 16.00 14.00 16.00 14.00 0.50 0.60 1.00 REF 3.5 -
Dimensions in Inches MIN 0.002 0.053 0.007 0.004 0.624 0.547 0.624 0.547 0.018 0 0 NOM 0.055 0.009 0.630 0.551 0.630 0.551 0.020 0.024 0.039 REF 3.5 MAX 0.063 0.006 0.057 0.011 0.008 0.636 0.555 0.636 0.555 0.030 7 -
MIN 0.05 1.35 0.17 0.09 15.85 13.90 15.85 13.90 0.45 0 0
MAX 1.60 0.15 1.45 0.27 0.20 16.15 14.10 16.15 14.10 0.75 7 -
3U
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Century Semiconductor Inc.
APPLICATION CIRCUIT SCHEMATIC
CS8810
CS0n IOWRn IORDn GND 3.3V
GND 3.3V
U1
CS1n A0 A1 3.3V GND A2 IDERSTn DATA0 DATA1 DATA2 DATA3 GND 3.3V 3.3V GND DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 3.3V GND
U\
RESETn 3.3VA1 GND R4 5K 0.01uF GND C4 0.1uF C3 U2 1 2 4 3 6 CS CLK DO DI ORG VCC 8 3.3V GND 5 C5 0.1uF GND
NC DATA11 DATA12 DATA13 DATA14 DATA15 INTQ IORDY IO16n CD1n VDD GND CD2n PDIAGn DASPn NC USBSEL EEDO EEDI EECLK EECS VDD(USB) DP DM GND(USB)
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
CS0n IOWRn IORDn GND VDD ROMADDR13 ROMADDR12 ROMADDR10 ROMADDR11 ROMADDR9 ROMADDR8 ROMADDR7 ROMADDR6 ROMADDR5 ROMADDR4 GND VDD ROMADDR3 ROMADDR2 ROMADDR1 ROMADDR0 TESTMOD ROMSEL ROMDATA0 ROMDATA1
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
GND GND
CS1n A0 A1 VDD NC GND A2 IDERSTn DATA0 DATA1 DATA2 DATA3 GND(INT) VDD(INT) VDD GND DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 VDD GND
USB CONTROLLER
CS8810
NC NC ROMDATA2 ROMDATA3 ROMDATA4 ROMDATA5 ROMDATA6 ROMDATA7 GND(INT) VDD(INT) TESTCLK ROMDATA8 ROMDATA9 ROMDATA10 ROMDATA11 ROMDATA12 ROMDATA13 RESETn NC NC XOUT XIN FILTER VDDA GNDA
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
GND 3.3V
Y1 4MHz C1 33P C2 33P GND
HOL Q
10K 3.3V GND 3.3V
JP1 IDERSTn DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GND IOWRn IORDn IORDY R2 5K6 R3 5K6 INTQ A1 A0 CS0n 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
R1 5K6 GND 3.3V 3.3V
IDERESETn DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GND DMARQ IOWRn IORDn IORDY DMACKn INTQ DA1 DA0 CS0n DASPn
GND DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 Keypin GND GND GND CSEL GND IOCS16n PDIAGn DA2 CS1n GND
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
3U
LP D
GND R5 3.3V 3.3V 3.3V DP DM GND
DATA11 DATA12 DATA13 DATA14 DATA15 INTQ IORDY IO16n GND 3.3V GND GND 3.3V GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
93LC46
Serial EEPROM 64X16
L1 322522-47uH 3.3VA1 C8 10uF/16V C9 0.1uF C10 0.01uF
GND DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 GND GND GND GND GND IO16n
C14 0.1uF GND
C15 0.1uF
C16 0.1uF
C17 0.1uF
C18 0.1uF
C19 0.1uF
C20 0.1uF
C21 0.1uF
C22 0.1uF
JP2 USBVDD DM DP USBGND USB_CON_B 1 2 3 4 R6 1K5 R7 5 R8 5 C6 22pF 3.3V DM DP C7 22pF GND U3 JP3 1 2 3 4 Ext.Power 3 C11 0.1uF C12 0.01uF GND VIN VOUT 2 1 3.3V 2K R9 RESETn C13 0.1uF GND
A2 CS1n GND
IDE Interface
ADJ/GND
AMS1117/SOT-223
Figure-2 Using 100-pin LQFP package
page 24 of 24

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