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Microcomputer Components
16-Bit CMOS Single-Chip Microcontroller 3 V Operation
C165
Specification 01.96 Advance Information
C165 Revision History: Previous Releases: Page 2 5 - 15 6 10 13 14
01.96 3 Volt Specification 07.95
Subjects (changes since last revision) SAF-C165-L25M added. VCC range changed. VOH conditions changed, IPD reduced, RRST changed to IRST. t38, t39 updated. t38, t39 updated. t33 updated.
Edition 01.96
Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation Balanstrae 73, D-81541 Munchen. (c) Siemens AG 1996. All Rights Reserved. As far as patents or other rights of third parties are concerned, liability is only assumed for components per se, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Offices of Siemens Aktiengesellschaft in Germany or the Siemens Companies and Representatives worldwide. Due to technical requirements components may contain dangerous substances. For information on the type in question please contact your nearest Siemens Office, Components Group. Siemens AG is an approved CECC manufacturer.
C16x-Family of High-Performance CMOS 16-Bit Microcontrollers Advance Information C165 16-Bit Microcontroller Additional Specification for Operation at 3 V Supply
q q q q q q q q q q q q q q q q q q q q q q q q
C165 / 3 V
q q q
High Performance 16-bit CPU with 4-Stage Pipeline 143 ns Instruction Cycle Time at 14 MHz CPU Clock 715 ns Multiplication (16 x 16 bits), 1.43 s Division (32 / 16 bit) Enhanced Boolean Bit Manipulation Facilities Additional Instructions to Support HLL and Operating Systems Register-Based Design with Multiple Variable Register Banks Single-Cycle Context Switching Support Up to 16 MBytes Linear Address Space for Code and Data 2 KBytes On-Chip RAM 4 KBytes On-Chip ROM (RM types only) Programmable External Bus Characteristics for Different Address Ranges 8-Bit or 16-Bit External Data Bus Multiplexed or Demultiplexed External Address/Data Buses Five Programmable Chip-Select Signals Hold- and Hold-Acknowledge Bus Arbitration Support 1024 Bytes On-Chip Special Function Register Area Idle and Power Down Modes 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) 16-Priority-Level Interrupt System with 28 Sources, Sample-Rate down to 72 ns Two Multi-Functional General Purpose Timer Units with 5 Timers Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous) Programmable Watchdog Timer Up to 77 General Purpose I/O Lines Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards On-Chip Bootstrap Loader 100-Pin MQFP Package (EIAJ) 100-Pin TQFP Package (Thin QFP)
This document describes specific items relevant for operation at 3 V. For functional descriptions please refer to the standard C165 data sheet.
This document describes the SAB-C165-L25M, the SAB-C165-L25F, the SAB-C165-R25M, the SAB-C165-RF and the SAF-C165-L25M. For simplicity all versions are referred to by the term C165 throughout this document.
1
01.96
C165 / 3 V
11Jul97@13:32h Intermediate Version
Introduction The C165's technology, originally a 5 V technology, allows to run the device at supply voltages down to 2.7 V. This addendum specifies the characteristics of the C165 when operated at 3 V. The input and output levels are still TTL compatible, the power supply current is reduced. The timing characteristics, however, are effected by the reduced voltage differences between supply voltages and IO levels. For this reason some timings are adjusted to the new circumstances and the operation at 3 V is limited to a CPU clock frequency of up to 14 MHz for the standard temperature range (0...70C) and up to 12 MHz for the temperature range -40...85C.
Ordering Information: Type SAB-C165-R25M Ordering Code Q67121-D... Package P-MQFP-100-2 Function 16-bit microcontroller with 2 KByte RAM and 4 KByte ROM Temperature range 0 to +70 C 16-bit microcontroller with 2 KByte RAM Temperature range 0 to +70 C 16-bit microcontroller with 2 KByte RAM Temperature range -40 to +85 C 16-bit microcontroller with 2 KByte RAM and 4 KByte ROM Temperature range 0 to +70 C 16-bit microcontroller with 2 KByte RAM Temperature range 0 to +70 C
SAB-C165-L25M
Q67121-C1005
P-MQFP-100-2
SAF-C165-L25M
Q67123-C1007
P-MQFP-100-2
SAB-C165-R25F
Q67121-D...
P-TQFP-100-3
SAB-C165-L25F
Q67121-C1004
P-TQFP-100-3
Note: The ordering codes (Q67121-D...) for the Mask-ROM versions are defined for each product after verification of the respective ROM code.
Semiconductor Group
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11Jul97@13:32h Intermediate Version
C165 / 3 V
Pin Configuration MQFP Package (top view)
C165
Figure 1
3
Semiconductor Group
C165 / 3 V
11Jul97@13:32h Intermediate Version
Pin Configuration TQFP Package (top view)
C165
Figure 2
Semiconductor Group
4
11Jul97@13:32h Intermediate Version
C165 / 3 V
Absolute Maximum Ratings Ambient temperature under bias (TA): SAB-C165-L25M, SAB-C165-R25M, SAB-C165-L25F, SAB-C165-R25F....................... 0 to +70 C SAF-C165-L25M ........................................................................................................... -40 to +85 C Storage temperature (TST)......................................................................................... - 65 to +150 C Voltage on VCC pins with respect to ground (VSS) ....................................................... -0.5 to +6.5 V Voltage on any pin with respect to ground (VSS) ...................................................-0.5 to VCC +0.5 V Input current on any pin during overload condition .................................................... -10 to +10 mA Absolute sum of all input currents during overload condition ..............................................|100 mA| Power dissipation..................................................................................................................... 1.5 W Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN>VCC or VINParameter Interpretation The parameters listed in the following partly represent the characteristics of the C165 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column "Symbol": CC (Controller Characteristics): The logic of the C165 will provide signals with the respective timing characteristics. SR (System Requirement): The external system must provide signals with the respective timing characteristics to the C165.
DC Characteristics
VCC = 2.7 V to 3.6 V; VSS = 0 V TA = 0 to +70 C for SAB-C165-L25M, SAB-C165-R25M, SAB-C165-L25F, SAB-C165-R25F TA = -40 to +85 C for SAF-C165-L25M
Parameter Symbol min. Input low voltage Input high voltage (all except RSTIN and XTAL1) Input high voltage RSTIN Input high voltage XTAL1 Limit Values max. 0.8 V V V V - - - - Unit Test Condition
VIL VIH
SR - 0.5 SR 2.0
VCC + 0.5 VCC + 0.5 VCC + 0.5
VIH1 SR 0.6 VCC VIH2 SR 0.7 VCC
5
Semiconductor Group
C165 / 3 V
11Jul97@13:32h Intermediate Version
Parameter
Symbol min.
Limit Values max. 0.45
Unit
Test Condition
Output low voltage VOL CC - (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output low voltage (all other outputs)
V
IOL = 1.6 mA
VOL1 CC -
0.45 -
V V
IOL1 = 1.0 mA IOH = - 500 A
Output high voltage VOH CC 0.9 VCC (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output high voltage (all other outputs)
1)
VOH1 CC 0.9 VCC IOZ1 CC - IOZ2 CC - IRST CC 5
5)
- 200 500 40 -10 - 20 - -10 - -5 - 20 10 10 + 1.5 * fCPU 2+ 0.7 * fCPU 30
V V nA nA A A A A A A A A A A pF mA mA A
IOH = - 250 A
0.45V < VIN < VCC 0.45V < VIN < VCC
Input leakage current (Port 5) Input leakage current (all other) RSTIN pullup current
2)
VCC = 3 V, VIN = 0.8 V VOUT = 2.4 V VOUT = VOLmax VOUT = VOLmax VOUT = 2.4 V VOUT = 2.4 V VOUT = VOL1max VIN = 1.4 V VIN = VILmax
0 V < VIN < VCC
Read/Write inactive current Read/Write active current ALE inactive current ALE active current
5) 5) 5) 5)
IRWH IRWL IALEL IALEH IP6H IP6L
5)
3) 4) 3) 4) 3) 4) 3) 4)
- -500 - 500 - -500 - -100
Port 6 inactive current Port 6 active current
5)
PORT0 configuration current XTAL1 input current Pin capacitance 6) (digital inputs/outputs) Power supply current Idle mode supply current
IP0H IP0L IIL CIO ICC IID IPD
CC - CC - - - -
f = 1 MHz TA = 25 C
RSTIN = VIL2 fCPU in [MHz] 7) RSTIN = VIH1 fCPU in [MHz] 7)
Power-down mode supply current
VCC = VCCmax 8)
Semiconductor Group
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11Jul97@13:32h Intermediate Version
C165 / 3 V
Notes
1)
This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. The pullup device on the RSTIN input is a transistor rather than a real resistor. It is intended to drive current into an external capacitor in order to realize an automatic power on reset. After a short power shutdown the external capacitor may hold a low residual charge due to the nature of the pullup device. The test condition with VIN = 0.8 V refers to this fact. The maximum current may be drawn while the respective signal line remains inactive. The minimum current must be drawn in order to drive the respective signal line active. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used for CS output and the open drain function is not enabled. Not 100% tested, guaranteed by design characterization. The supply current is a function of the operating frequency. This dependency is illustrated in the figure below. These parameters are tested at VCCmax and maximum CPU clock with all outputs disconnected and all inputs at VIL or VIH. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VCC - 0.1 V to VCC, VREF = 0 V, all outputs (including pins configured as outputs) disconnected.
2)
3) 4) 5)
6) 7)
8)
7
Semiconductor Group
C165 / 3 V
11Jul97@13:32h Intermediate Version
I [mA]
35
ICCmax
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30
25
20
15
10
5
5
10
15
20
fCPU [MHz]
Figure 3 Supply/Idle Current as a Function of Operating Frequency
Semiconductor Group
8
11Jul97@13:32h Intermediate Version
C165 / 3 V
AC Characteristics External Clock Drive XTAL1
VCC = 2.7 V to 3.6 V; VSS = 0 V TA = 0 to +70 C for SAB-C165-L25M, SAB-C165-R25M, SAB-C165-L25F, SAB-C165-R25F
Parameter Symbol Max. CPU Clock = 14 MHz min. Oscillator period High time Low time Rise time Fall time max. 35.7 - - 5
1)
Variable CPU Clock 1 / 2TCL = 1 to 14 MHz min. 35.7 6 1) 6 - -
1)
Unit
max. 500 - - 5
1)
tOSC SR 35.7 t1 t2 t3 t4
SR 6 1) SR 6 SR - SR -
1)
ns ns ns ns ns
5 1)
5 1)
VCC = 2.7 V to 3.6 V; VSS = 0 V TA = -40 to +85 C for SAF-C165-L25M
Parameter Symbol Max. CPU Clock = 12 MHz min. Oscillator period High time Low time Rise time Fall time
1)
Variable CPU Clock 1 / 2TCL = 1 to 12 MHz min. 41.7 6 1) 6 - -
1)
Unit
max. 41.7 - - 5 1) 5 1)
max. 500 - - 5 1) 5 1) ns ns ns ns ns
tOSC SR 41.7 t1 t2 t3 t4
SR 6 1) SR 6 SR - SR -
1)
The clock input signal must reach the defined levels VIL and VIH2.
Figure 4 External Clock Drive XTAL1
9
Semiconductor Group
C165 / 3 V
11Jul97@13:32h Intermediate Version
Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Description ALE Extension Memory Cycle Time Waitstates Memory Tristate Time Symbol Values
tA tC tF
TCL *
1)
2TCL * (15 - ) 2TCL * (1 - )
The following notes apply to the next two timing tables (Multiplexed Bus and Demultiplexed Bus):
1) 2)
RW-delay and tA refer to the next following bus cycle.
Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes before the end of RD have no impact on read cycles. The rising edges of CS represent the worst case. The delay for falling edges is lower.
*)
AC Characteristics Multiplexed Bus
VCC = 2.7 V to 3.6 V; VSS = 0 V TA = 0 to +70 C for SAB-C165-L25M, SAB-C165-R25M, SAB-C165-L25F, SAB-C165-R25F TA = -40 to +85 C for SAF-C165-L25M CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF CL (for Port 6, CS) = 100 pF ALE cycle time = 6 TCL + 2tA + tC + tF (214.3/250 ns at 14/12 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock = 14 MHz (0 to 70 C) min. ALE high time Address setup to ALE Address hold after ALE max. - - - Variable CPU Clock Unit 1/2TCL=1..14 MHz, 0..70 C 1/2TCL=1..12 MHz, -40..85C min. TCL - 20 + tA TCL - 30 + tA TCL - 10 + tA max. - - - ns ns ns
t5 t6 t7
CC 16 + tA CC 6 + tA CC 26 + tA
Semiconductor Group
10
11Jul97@13:32h Intermediate Version
C165 / 3 V
Parameter
Symbol
Max. CPU Clock = 14 MHz (0 to 70 C) min. max. - - 5 41 - - 41 + tC 77 + tC 82 + tA + tC 98 + 2tA + tC - 56 + tF - - - - 20 - tA *) 72 + tC + 2tA
Variable CPU Clock Unit 1/2TCL=1..14 MHz, 0..70 C 1/2TCL=1..12 MHz, -40..85C min. TCL - 10 + tA -10 + tA - - 2TCL - 20 + tC 3TCL - 20 + tC - - - - 0 - 2TCL - 35 + tC 2TCL - 15 + tF 2TCL - 15 + tF 2TCL - 15 + tF -5 - tA - max. - - 5 TCL + 5 - - 2TCL - 30 + tC 3TCL - 30 + tC 3TCL - 25 + tA + tC 4TCL - 45 + 2tA + tC - 2TCL - 15 + tF - - - - 20 - tA *) 3TCL - 35 + tC+2tA ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) Address float after RD, WR (with RW-delay) Address float after RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD Data valid to WR Data hold after WR ALE rising edge after RD, WR Address hold after RD, WR ALE falling edge to CS CS low to Valid Data In
t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t22 t23 t25 t27 t38 t39
CC 26 + tA CC -10 + tA CC - CC - CC 51 + tC CC 87 + tC SR - SR - SR - SR - SR 0 SR - CC 36 + tC CC 56 + tF CC 56 + tF CC 56 + tF CC -5 - tA SR -
11
Semiconductor Group
C165 / 3 V
11Jul97@13:32h Intermediate Version
Parameter
Symbol
Max. CPU Clock = 14 MHz (0 to 70 C) min. max. - - - 0 36 42 + tC 77 + tC - - - - 51 + tF - -
Variable CPU Clock Unit 1/2TCL=1..14 MHz, 0..70 C 1/2TCL=1..12 MHz, -40..85C min. 3TCL - 20 + tF TCL - 5 + tA -5 + tA - - - - 2TCL - 15 + tC 3TCL - 15 + tC 2TCL - 25 + tC 0 - 2TCL - 20 + tF 2TCL - 20 + tF max. - - - 0 TCL 2TCL - 30 + tC 3TCL - 30 + tC - - - - 2TCL - 20 + tF - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CS hold after RD, WR ALE fall. edge to RdCS, WrCS (with RW delay) ALE fall. edge to RdCS, WrCS (no RW delay) Address float after RdCS, WrCS (with RW delay) Address float after RdCS, WrCS (no RW delay) RdCS to Valid Data In (with RW delay) RdCS to Valid Data In (no RW delay) RdCS, WrCS Low Time (with RW delay) RdCS, WrCS Low Time (no RW delay) Data valid to WrCS Data hold after RdCS Data float after RdCS Address hold after RdCS, WrCS Data hold after WrCS
t40 t42 t43 t44 t45 t46 t47 t48 t49 t50 t51 t52 t54 t56
CC 87 + tF CC 31 + tA CC -5 + tA CC - CC - SR - SR - CC 56 + tC CC 92 + tC CC 46 + tC SR 0 SR - CC 51 + tF CC 51 + tF
Semiconductor Group
12
11Jul97@13:32h Intermediate Version
C165 / 3 V
AC Characteristics Demultiplexed Bus
VCC = 2.7 V to 3.6 V; VSS = 0 V TA = 0 to +70 C for SAB-C165-L25M, SAB-C165-R25M, SAB-C165-L25F, SAB-C165-R25F TA = -40 to +85 C for SAF-C165-L25M CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF CL (for Port 6, CS) = 100 pF ALE cycle time = 4 TCL + 2tA + tC + tF (143/166.7 ns at 14/12 MHz CPU clock without waitstates)
Parameter Symbol Max. CPU Clock = 14 MHz (0 to 70 C) min. ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD rising edge (with RW-delay 1)) Data float after RD rising edge (no RW-delay 1)) Data valid to WR max. - - - - - - 41 + tC 77 + tC 82 + tA + tC 98 + 2tA + tC - 56 + tF 26 + tF - Variable CPU Clock Unit 1/2TCL=1..14 MHz, 0..70 C 1/2TCL=1..12 MHz, -40..85C min. TCL - 20 + tA TCL - 30 + tA TCL - 10 + tA -10 + tA 2TCL - 20 + tC 3TCL - 20 + tC - - - - 0 - - 2TCL - 35 + tC max. - - - - - - 2TCL - 30 + tC 3TCL - 30 + tC 3TCL - 25 + tA + tC 4TCL - 45 + 2tA + tC - 2TCL - 15 + 2tA + tF 1) TCL - 10 + 2tA + tF 1) - ns ns ns ns ns ns ns ns ns ns ns ns ns ns
t5 t6 t8 t9 t12 t13 t14 t15 t16 t17 t18 t20 t21 t22
CC 16 + tA CC 6 + tA CC 26 + tA CC -10 + tA CC 51 + tC CC 87 + tC SR - SR - SR - SR - SR 0 SR - SR - CC 36 + tC
13
Semiconductor Group
C165 / 3 V
11Jul97@13:32h Intermediate Version
Parameter
Symbol
Max. CPU Clock = 14 MHz (0 to 70 C) min. max. - - - 20 - tA *) 72 + tC + 2tA - - - 42 + tC 77 + tC - - - - 51 + tF 16 + tF - -
Variable CPU Clock Unit 1/2TCL=1..14 MHz, 0..70 C 1/2TCL=1..12 MHz, -40..85C min. TCL - 10 + tF -10 + tF 0 + tF -5 - tA - TCL - 20 + tF TCL - 5 + tA -5 + tA - - 2TCL - 15 + tC 3TCL - 15 + tC 2TCL - 25 + tC 0 - - -5 + tF TCL - 15 + tF max. - - - 20 - tA *) 3TCL - 35 + tC+2tA - - - 2TCL - 30 + tC 3TCL - 30 + tC - - - - 2TCL - 20 + tF TCL - 20 + tF - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Data hold after WR ALE rising edge after RD, WR Address hold after WR 2) ALE falling edge to CS CS low to Valid Data In CS hold after RD, WR ALE falling edge to RdCS, WrCS (with RW-delay) ALE falling edge to RdCS, WrCS (no RW-delay) RdCS to Valid Data In (with RW-delay) RdCS to Valid Data In (no RW-delay) RdCS, WrCS Low Time (with RW-delay) RdCS, WrCS Low Time (no RW-delay) Data valid to WrCS Data hold after RdCS Data float after RdCS (with RW-delay) Data float after RdCS (no RW-delay) Address hold after RdCS, WrCS Data hold after WrCS
t24 t26 t28 t38 t39 t41 t42 t43 t46 t47 t48 t49 t50 t51 t53 t68 t55 t57
CC 26 + tF CC -10 + tF CC 0 + tF CC -5 - tA SR - CC 16 + tF CC 31 + tA CC -5 + tA SR - SR - CC 56 + tC CC 92 + tC CC 46 + tC SR 0 SR - SR - CC -5 + tF CC 21 + tF
Semiconductor Group
14
11Jul97@13:32h Intermediate Version
C165 / 3 V
AC Characteristics CLKOUT and READY
VCC = 2.7 V to 3.6 V; VSS = 0 V TA = 0 to +70 C for SAB-C165-L25M, SAB-C165-R25M, SAB-C165-L25F, SAB-C165-R25F TA = -40 to +85 C for SAF-C165-L25M CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF CL (for Port 6, CS) = 100 pF
Parameter Symbol Max. CPU Clock = 14 MHz (0 to 70 C) min. CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY setup time to CLKOUT Synchronous READY hold time after CLKOUT Asynchronous READY low time Asynchronous READY setup time 1) Asynchronous READY hold time 1) Async. READY hold time after RD, WR high (Demultiplexed Bus) 2) max. 72 - - 15 10 5 + tA - - - - - 11 + 2tA + tC + tF 2) Variable CPU Clock Unit 1/2TCL=1..14 MHz, 0..70 C 1/2TCL=1..12 MHz, -40..85C min. 2TCL TCL - 20 TCL - 15 - - -10 + tA 20 0 2TCL + 20 20 0 0 max. 2TCL - - 15 10 5 + tA - - - - - ns ns ns ns ns ns ns ns ns ns ns
t29 t30 t31 t32 t33 t34 t35 t36 t37 t58 t59 t60
CC 72 CC 16 CC 21 CC - CC - CC -10 + tA SR 20 SR 0 SR 91 SR 20 SR 0 SR 0
TCL - 25 ns + 2tA + tC + tF
2)
Notes
1) 2)
These timings are given for test purposes only, in order to assure recognition at a specific clock edge. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle.
15
Semiconductor Group
C165 / 3 V
11Jul97@13:32h Intermediate Version
AC Characteristics External Bus Arbitration
VCC = 2.7 V to 3.6 V; VSS = 0 V TA = 0 to +70 C for SAB-C165-L25M, SAB-C165-R25M, SAB-C165-L25F, SAB-C165-R25F TA = -40 to +85 C for SAF-C165-L25M CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF CL (for Port 6, CS) = 100 pF
Parameter Symbol Max. CPU Clock = 14 MHz (0 to 70 C) min. HOLD input setup time to CLKOUT CLKOUT to HLDA high or BREQ low delay CLKOUT to HLDA low or BREQ high delay CSx release CSx drive Other signals release Other signals drive max. - 20 20 20 30 20 30 Variable CPU Clock Unit 1/2TCL=1..14 MHz, 0..70 C 1/2TCL=1..12 MHz, -40..85C min. 30 - - - -5 - -5 max. - 20 20 20 30 20 30 ns ns ns ns ns ns ns
t61 t62 t63 t64 t65 t66 t67
SR 30 CC - CC - CC - CC -5 CC - CC -5
Semiconductor Group
16

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