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| Microcomputer Components 16-Bit CMOS Single-Chip Microcontroller Bare Die, Step BA C167CR/C167SR-LC Data Sheet 05.97 (Bare Die Delivery) C167CR-LC/C167SR-LC Revision History: Previous Releases: Page Subjects (Bare Die Delivery) Original Version 05.97 - Controller Area Network (CAN): License of Robert Bosch GmbH Edition 05.97 Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation Balanstrae 73, D-81541 Munchen. (c) Siemens AG 1997. All Rights Reserved. As far as patents or other rights of third parties are concerned, liability is only assumed for components per se, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Offices of Siemens Aktiengesellschaft in Germany or the Siemens Companies and Representatives worldwide. Due to technical requirements components may contain dangerous substances. For information on the type in question please contact your nearest Siemens Office, Components Group. Siemens AG is an approved CECC manufacturer. C16x-Family of High-Performance CMOS 16-Bit Microcontrollers Advance Information C167xR-LC 16-Bit Microcontroller q q q q q q q q q q q q q q q q q q q q q q q q q q q q q C167xR-LC q High Performance 16-bit CPU with 4-Stage Pipeline 100 ns Instruction Cycle Time at 20 MHz CPU Clock 500 ns Multiplication (16 x 16 bit), 1 s Division (32 / 16 bit) Enhanced Boolean Bit Manipulation Facilities Additional Instructions to Support HLL and Operating Systems Register-Based Design with Multiple Variable Register Banks Single-Cycle Context Switching Support Clock Generation via on-chip PLL or via direct clock input Up to 16 MBytes Linear Address Space for Code and Data 2 KBytes On-Chip Internal RAM (IRAM) 2 KBytes On-Chip Extension RAM (XRAM) Programmable External Bus Characteristics for Different Address Ranges 8-Bit or 16-Bit External Data Bus Multiplexed or Demultiplexed External Address/Data Buses Five Programmable Chip-Select Signals Hold- and Hold-Acknowledge Bus Arbitration Support 1024 Bytes On-Chip Special Function Register Area Idle and Power Down Modes 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 50 ns 16-Channel 10-bit A/D Converter with 9.7s Conversion Time Two 16-Channel Capture/Compare Units 4-Channel PWM Unit Two Multi-Functional General Purpose Timer Units with 5 Timers Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous) On-Chip CAN Interface with 15 Message Objects (Full-CAN/Basic-CAN, C167CR-LC only) Programmable Watchdog Timer Up to 111 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards On-Chip Bootstrap Loader This document describes the SAK-C167CR-LC and the SAK-C167SR-LC. For simplicity all versions are referred to by the term C167xR-LC throughout this document. 1 05.97 C167xR-LC 07May97@09:45h Intermediate Version Introduction The C167xR-LC is a derivative of the Siemens C16x Family of full featured single-chip CMOS microcontrollers. It combines high CPU performance (up to 10 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. It also provides on-chip high-speed RAM and clock generation via PLL. C167xRLC Figure 1 Logic Symbol Ordering Information Type SAK-C167CR-LC SAK-C167CR-LC SAK-C167SR-LC Ordering Code Q67120-C1089 Q67120-C1028 Q67120-C1080 Wafers Whole Sawn Sawn Function 16-bit microcontroller with 2*2 KByte RAM Temperature range -40 to +125 C 16-bit microcontroller with 2*2 KByte RAM Temperature range -40 to +125 C 16-bit microcontroller with 2*2 KByte RAM Temperature range -40 to +125 C Semiconductor Group 2 07May97@09:45h Intermediate Version C167xR-LC Pad Configuration (top view) Pad 112 Pad 76 Pad 113 C167xR-LC Pad 150 y 0.0 Pad 1 x 0.0 Pad 36 Figure 2 3 Semiconductor Group Pad 37 Pad 75 C167xR-LC 07May97@09:45h Intermediate Version Pad Definitions and Functions Symbol Pad Input Position [m] Function Num. Outp. x y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 293 451 609 766 924 1082 1240 1604 1788 2046 2226 2463 2621 2778 2945 3103 3261 3419 3577 3735 3893 4050 4208 4366 0 Reference ground for the A/D converter. 0 Port 5 input, analog input AN10, ext.up/down T6EUD. 0 Port 5 input, analog input AN11, ext.up/down T5EUD. 0 Port 5 input, analog input AN12, timer input T6IN. 0 Port 5 input, analog input AN13, timer input T5IN. 0 Port 5 input, analog input AN14, ext.up/down T4EUD. 0 Port 5 input, analog input AN15, ext.up/down T2EUD. 0 Digital Ground. 0 Digital Ground. 0 Digital Supply Voltage. 0 Digital Supply Voltage. 0 Port 2 input/output (open drain, special threshold), Capture-Input/Compare-Output CC0IO. 0 Port 2 input/output (open drain, special threshold), Capture-Input/Compare-Output CC1IO. 0 Port 2 input/output (open drain, special threshold), Capture-Input/Compare-Output CC2IO. 0 Port 2 input/output (open drain, special threshold), Capture-Input/Compare-Output CC3IO. 0 Port 2 input/output (open drain, special threshold), Capture-Input/Compare-Output CC4IO. 0 Port 2 input/output (open drain, special threshold), Capture-Input/Compare-Output CC5IO. 0 Port 2 input/output (open drain, special threshold), Capture-Input/Compare-Output CC6IO. 0 Port 2 input/output (open drain, special threshold), Capture-Input/Compare-Output CC7IO. 0 Digital Ground. 0 Digital Supply Voltage. 0 Port 2 input/output (open drain, special threshold), Capt. Input/Comp. Output CC8IO, Fast Interrupt EX0IN. 0 Port 2 input/output (open drain, special threshold), Capt. Input/Comp. Output CC9IO, Fast Interrupt EX1IN. 0 Port 2 input/output (open drain, special threshold), Capt. Input/Comp. Output CC10IO, Fast Interrupt EX2IN. VAGND P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 VSS VSS VCC VCC P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 VSS VCC P2.8 P2.9 P2.10 Semiconductor Group 4 07May97@09:45h Intermediate Version C167xR-LC Pad Definitions and Functions (cont'd) Symbol P2.11 P2.12 P2.13 P2.14 P2.15 Pad Input Position [m] Function Num. Outp. x y 25 26 27 28 29 I/O I/O I/O I/O I/O 4542 4699 4857 5015 5173 0 Port 2 input/output (open drain, special threshold), Capt. Input/Comp. Output CC11IO, Fast Interrupt EX3IN. 0 Port 2 input/output (open drain, special threshold), Capt. Input/Comp. Output CC12IO, Fast Interrupt EX4IN. 0 Port 2 input/output (open drain, special threshold), Capt. Input/Comp. Output CC13IO, Fast Interrupt EX5IN. 0 Port 2 input/output (open drain, special threshold), Capt. Input/Comp. Output CC14IO, Fast Interrupt EX6IN. 0 Port 2 input/output (open drain, special threshold), Capt. Input/Comp. Output CC15IO, Fast Interrupt EX7IN, Timer T7 input T7IN. 0 Port 3 input/output (open drain, special threshold), Timer T0 Input T0IN. 0 Port 3 input/output (open drain, special threshold), Timer T6 Toggle Latch Output T6OUT. 0 Port 3 input/output (open drain, special threshold), CAPREL Capture Input CAPIN. 0 Port 3 input/output (open drain, special threshold), Timer T3 Toggle Latch Output T3OUT. 0 Port 3 input/output (open drain, special threshold), Timer T3 ext.up/down T3EUD. 0 Port 3 input/output (open drain, special threshold), Timer T4 Input T4IN. 0 Digital Ground. 277 Digital Supply Voltage. 435 Port 3 input/output (open drain, special threshold), Timer T3 Input T3IN. 593 Port 3 input/output (open drain, special threshold), Timer T2 Input T2IN. 751 Port 3 input/output (open drain, special threshold), SSC Master-Rec./Slave-Transmit I/O MRST. 909 Port 3 input/output (open drain, special threshold), SSC Master-Transmit/Slave-Rec. O/I MTSR. 1067 Port 3 input/output (open drain, special threshold), ASC0 Clock/Data Output (Asyn./Syn.) TxD0. P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 30 31 32 33 34 35 36 37 38 39 40 41 42 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 5340 5498 5656 5814 5971 6129 6287 6564 6564 6564 6564 6564 6564 VSS VCC P3.6 P3.7 P3.8 P3.9 P3.10 5 Semiconductor Group C167xR-LC 07May97@09:45h Intermediate Version Pad Definitions and Functions (cont'd) Symbol P3.11 P3.12 Pad Input Position [m] Function Num. Outp. x y 43 44 45 P3.13 P3.15 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 I/O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I O I I/O I/O I/O I/O I/O I/O 6564 6564 6564 6564 6564 6564 6564 6564 6564 6564 6564 6564 6564 6564 6564 6564 6564 6564 6564 6564 6564 6564 6564 6564 6564 6564 6564 6564 6564 1225 Port 3 input/output (open drain, special threshold), ASC0 Data Input (Asyn.) or I/O (Syn.) RxD0. 1383 Port 3 input/output (open drain, special threshold). 1540 High Byte Enable BHE, High Byte Write Strobe WRH. 1698 Port 3 input/output (open drain, special threshold), SSC Master Clock Outp./Slave Clock Input SCLK. 1856 Port 3 input/output (open drain, special threshold). 2014 System Clock Output (=CPU Clock) CLKOUT. 2433 Digital Supply Voltage. 2643 Digital Ground. 3062 Port 4 input/output, Segment Address Line A16. 3220 Port 4 input/output, Segment Address Line A17. 3378 Port 4 input/output, Segment Address Line A18. 3693 Port 4 input/output, Segment Address Line A19. 3062 Port 4 input/output, Segment Address Line A20. 3851 Port 4 input/output, Segment Address Line A21, CAN Receive Data Input CAN_RxD. 4009 Port 4 input/output, Segment Address Line A22 CAN Transmit Data Output CAN_TxD. 4184 Port 4 input/output, Segment Address Line A23. 4360 Digital Supply Voltage. 4535 Digital Ground. 4710 External Memory Read Strobe RD. 4885 External Memory Write (Low) Strobe WR (WRL). 5060 Ready Input. 5236 Address Latch Enable Output. 5394 External Access Enable pin. 5664 PORT0 input/output, Address/Data Line AD0. 5822 PORT0 input/output, Address/Data Line AD1. 5980 PORT0 input/output, Address/Data Line AD2. 6138 PORT0 input/output, Address/Data Line AD3. 6295 PORT0 input/output, Address/Data Line AD4. 6453 PORT0 input/output, Address/Data Line AD5. VCC VSS P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 VCC VSS RD WR(L) READY ALE EA P0L.0 P0L.1 P0L.2 P0L.3 P0L.4 P0L.5 Semiconductor Group 6 07May97@09:45h Intermediate Version C167xR-LC Pad Definitions and Functions (cont'd) Symbol P0L.6 P0L.7 P0H.0 Pad Input Position [m] Function Num. Outp. x y 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O 6564 6564 6564 6564 6052 6564 5894 5736 5578 5420 5262 5104 4946 4788 4630 4472 4314 4157 3999 3841 3683 3525 3367 3209 3051 2893 2735 2577 2419 2262 2104 6611 PORT0 input/output, Address/Data Line AD6. 6769 PORT0 input/output, Address/Data Line AD7. 7014 PORT0 input/output, Address/Data Line AD8. 7313 Digital Supply Voltage. 7590 Digital Ground. 7590 PORT0 input/output, Address/Data Line AD9. 7590 PORT0 input/output, Address/Data Line AD10. 7590 PORT0 input/output, Address/Data Line AD11. 7590 PORT0 input/output, Address/Data Line AD12. 7590 PORT0 input/output, Address/Data Line AD13. 7590 PORT0 input/output, Address/Data Line AD14. 7590 PORT0 input/output, Address/Data Line AD15. 7590 PORT1 input/output, Address Line A0. 7590 PORT1 input/output, Address Line A1. 7590 PORT1 input/output, Address Line A2. 7590 PORT1 input/output, Address Line A3. 7590 PORT1 input/output, Address Line A4. 7590 PORT1 input/output, Address Line A5. 7590 PORT1 input/output, Address Line A6. 7590 PORT1 input/output, Address Line A7. 7590 Digital Supply Voltage. 7590 CAN module enable input, must be connected to VSS (for the C167CR-LC) or to VCC (for the C167SR-LC). 7590 Digital Ground. 7590 PORT1 input/output, Address Line A8. 7590 PORT1 input/output, Address Line A9. 7590 PORT1 input/output, Address Line A10. 7590 PORT1 input/output, Address Line A11. 7590 PORT1 input/output, Addr. Line A12, Capt. Input CC24. 7590 PORT1 input/output, Addr. Line A13, Capt. Input CC25. 7590 PORT1 input/output, Addr. Line A14, Capt. Input CC26. 7590 PORT1 input/output, Addr. Line A15, Capt. Input CC27. VCC VSS P0H.1 P0H.2 P0H.3 P0H.4 P0H.5 P0H.6 P0H.7 P1L.0 P1L.1 P1L.2 P1L.3 P1L.4 P1L.5 P1L.6 P1L.7 VCC XP1_EN VSS P1H.0 P1H.1 P1H.2 P1H.3 P1H.4 P1H.5 P1H.6 P1H.7 7 Semiconductor Group C167xR-LC 07May97@09:45h Intermediate Version Pad Definitions and Functions (cont'd) Symbol Pad Input Position [m] Function Num. Outp. x y 103 104 105 106 107 108 109 I O I I O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 1867 1650 1492 1334 1146 988 751 593 435 277 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7590 Digital Supply Voltage. 7590 Must be connected to VSS. 7590 Output of the oscillator amplifier circuit. 7590 Input to oscillator amplifier and internal clock generator. 7590 Digital Ground. 7590 Digital Ground. 7590 Reset Input with Schmitt-Trigger characteristics. 7590 Internal Reset Indication Output. 7590 Non-Maskable Interrupt Input. 7590 Digital Ground. 7313 Digital Supply Voltage. 7051 Port 6 input/output, Chip Select 0 Output CS0. 6893 Port 6 input/output, Chip Select 1 Output CS1. 6735 Port 6 input/output, Chip Select 2 Output CS2. 6577 Port 6 input/output, Chip Select 3 Output CS3. 6419 Port 6 input/output, Chip Select 4 Output CS4. 6261 Port 6 input/output, External Hold Request Input HOLD. 6103 Port 6 input/output, External Hold Ackn. Output HLDA. 5946 Port 6 input/output, Bus Request Output BREQ. 5658 Port 8 input/output, Capt.-Input/Comp.-Output CC16IO. 5483 Port 8 input/output, Capt.-Input/Comp.-Output CC17IO. 5325 Port 8 input/output, Capt.-Input/Comp.-Output CC18IO. 5167 Port 8 input/output, Capt.-Input/Comp.-Output CC19IO. 5009 Port 8 input/output, Capt.-Input/Comp.-Output CC20IO. 4834 Port 8 input/output, Capt.-Input/Comp.-Output CC21IO. 4641 Port 8 input/output, Capt.-Input/Comp.-Output CC22IO. 4483 Port 8 input/output, Capt.-Input/Comp.-Output CC23IO. 4135 Digital Supply Voltage. 3978 Digital Ground. 3820 Port 7 input/output, (open drain, special threshold), PWM Channel Output POUT0. VCC TLRON XTAL2 XTAL1 VSS VSS RSTIN RSTOUT 110 NMI 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 VSS VCC P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7 P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 P8.7 VCC VSS P7.0 Semiconductor Group 8 07May97@09:45h Intermediate Version C167xR-LC Pad Definitions and Functions (cont'd) Symbol P7.1 P7.2 P7.3 P7.4 P7.5 P7.6 P7.7 P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P5.8 P5.9 Pad Input Position [m] Function Num. Outp. x y 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3644 Port 7 input/output, (open drain, special threshold), PWM Channel Output POUT1. 3469 Port 7 input/output, (open drain, special threshold), PWM Channel Output POUT2. 3294 Port 7 input/output, (open drain, special threshold), PWM Channel Output POUT3. 3119 Port 7 input/output, (open drain, special threshold), Capt.-Input/Comp.-Output CC28IO. 2944 Port 7 input/output, (open drain, special threshold), Capt.-Input/Comp.-Output CC29IO. 2768 Port 7 input/output, (open drain, special threshold), Capt.-Input/Comp.-Output CC30IO. 2593 Port 7 input/output, (open drain, special threshold), Capt.-Input/Comp.-Output CC31IO. 1872 Port 5 input, analog input AN0. 1714 Port 5 input, analog input AN1. 1556 Port 5 input, analog input AN2. 1398 Port 5 input, analog input AN3. 1240 Port 5 input, analog input AN4. 1082 Port 5 input, analog input AN5. 924 Port 5 input, analog input AN6. 766 Port 5 input, analog input AN7. 609 Port 5 input, analog input AN8. 451 Port 5 input, analog input AN9. 293 Reference voltage for the A/D converter. VAREF Note: All VSS pads and all VCC pads must be connected to the system ground and the power supply, respectively. The pad definitions and locations in this table are only valid for the indicated device and design step. 9 Semiconductor Group C167xR-LC 07May97@09:45h Intermediate Version Functional Description As the standard packaged devices are made from this silicon the C167xR-LC dies provide exactly the same functionality and behaviour. Also the DC characteristics and AC characteristics are compatible with those of the packaged devices. For a description of the functionality and the DC and AC parameters please refer to the following documents (or later versions thereof): q C167SR Data Sheet 06.95 q C167CR Data Sheet 06.95 q C167 Derivatives User's Manual Version 2.0 Figure 3 Block Diagram Semiconductor Group 10 07May97@09:45h Intermediate Version C167xR-LC Absolute Maximum Ratings Chip temperature under bias (TD): SAF-C167xR-LC .......................................................................................................... -40 to +85 C SAK-C167xR-LC........................................................................................................ -40 to +125 C Storage temperature (TST)......................................................................................... - 65 to +150 C Voltage on VCC pads with respect to ground (VSS) ...................................................... -0.5 to +6.5 V Voltage on any pad with respect to ground (VSS)..................................................-0.5 to VCC +0.5 V Input current on any pad during overload condition................................................... -10 to +10 mA Absolute sum of all input currents during overload condition ..............................................|100 mA| Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN>VCC or VIN Storage Conditions The C167xR-LC dies may be stored for a certain time under the conditions described below. Bare Die Storage Conditions and Duration Packing Vacuum pack Environment Air Temperature 15...30 C Relative Humidity < 60 % Storage Time < 4 Months 11 Semiconductor Group C167xR-LC 07May97@09:45h Intermediate Version Chip Outline 0.45 6.95 y x 0,0 0.110 0.100 0.150 min 0.100 0.110 Typical Dimensions in mm Figure 4 Semiconductor Group 12 7.98 07May97@09:45h Intermediate Version C167xR-LC Wafer Characteristics Item Chips per wafer Metallization layers Metallization material Metallization thickness Metallization barrier material Metallization isolation Metallization material on pads Passivation Backside metallization Inkdot diameter Characteristic 258 (geometrically) 2 AlSiCu (Al 98.5% - SI 1% - Cu 0.5%) Met1: 800 nm, Met2: 1000 nm Ti/TiN Oxide AlSiCu (Al 98.5% - SI 1% - Cu 0.5%) Oxide (300 nm) + nitride (550 nm), polyimid None (silicon) 1.0-1.3 mm typical The wafers are glued to a plastic tape which is fixed within a plastic ring (see figure below). Wafers can be shipped in one piece or sawn into individual dies. 13 Semiconductor Group C167xR-LC 07May97@09:45h Intermediate Version Wafer Outline Plastic Frame Plastic Tape Wafer 152.4 (6") 210 230 Dimensions in mm Figure 5 Semiconductor Group 14 |
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