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DAC 122 0
DAC1220
20-Bit Low Power DIGITAL-TO-ANALOG CONVERTER
FEATURES
q 20-BIT MONOTONICITY GUARANTEED OVER -40C to +85C q LOW POWER: 2.5mW q VOLTAGE OUTPUT q SETTLING TIME: 2ms to 0.012% q MAX LINEARITY ERROR: 0.0015% q ON-CHIP CALIBRATION
APPLICATIONS
q PROCESS CONTROL q ATE PIN ELECTRONICS q CLOSED-LOOP SERVO-CONTROL q SMART TRANSMITTERS q PORTABLE INSTRUMENTS
DESCRIPTION
The DAC1220 is a 20-bit digital-to-analog (D/A) converter offering 20-bit monotonic performance over the specified temperature range. It utilizes delta-sigma technology to achieve inherently linear 20-bit performance in a small package at very low power. The resolution of the device can be programmed to 20 bits for full-scale settling to 0.003% within 15ms typical or 16 bits for full-scale settling to 0.012% within 2ms max. The output range is 0V to two times the external reference voltage and on-chip calibration circuitry provides extremely low offset and gain error.
XIN XOUT VREF
The DAC1220 features a synchronous serial interface that is SPI and Microwire compatible. In single converter applications, the serial interface can be accomplished with just two wires, allowing low cost isolation. For multiple converters, a third CS signal allows for selection of the appropriate D/A converter. The DAC1220 has been designed for closed-loop control applications in the industrial process control market and high resolution applications in the test and measurement market. It is also ideal for remote applications, battery powered instruments and isolated systems. The DAC1220 is available in a 16-lead SSOP package.
AVDD AGND
Clock Generator
Microcontroller Instruction Register Command Register Data Register Offset Register Full-Scale Register Second-Order Modulator First-Order Switched Capacitor Filter Second-Order Continuous Time Post Filter C1 VOUT C2
SCLK SDIO
Serial Interface
Modulator Control
CS
DVDD
DGND
International Airport Industrial Park * Mailing Address: PO Box 11400, Tucson, AZ 85734 * Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 * Tel: (520) 746-1111 Twx: 910-952-1111 * Internet: http://www.burr-brown.com/ * Cable: BBRCORP * Telex: 066-6491 * FAX: (520) 889-1510 * Immediate Product Info: (800) 548-6132
(c) 1998 Burr-Brown Corporation
PDS-1418A
Printed in U.S.A. December, 1998
SPECIFICATIONS
All specifications TMIN to TMAX, AVDD = DVDD = +5V, fXIN = 2.5MHz, VREF = +2.5V, and 16-bit mode, unless otherwise noted. DAC1220E PARAMETER ACCURACY Monotonicity Monotonicity Linearity Error Unipolar Offset Error(2) Unipolar Offset Error Drift(3) Bipolar Zero Offset Error(2) Bipolar Zero Offset Drift(3) Gain Error(2) Gain Error Drift(3) Power Supply Rejection Ratio ANALOG OUTPUT Output Voltage(4) Output Current Capacitive Load Short-Circuit Current Short-Circuit Duration DYNAMIC PERFORMANCE Settling Time(5) Output Noise Voltage REFERENCE INPUT Input Voltage Input Impedance DIGITAL INPUT/OUTPUT Logic Family Logic Levels (all except XIN) VIH VIL VOH VOL XIN Frequency Range (fXIN) Data Format POWER SUPPLY REQUIREMENTS Power Supply Voltage Supply Current Analog Current Digital Current Analog Current Digital Current Power Dissipation 20-Bit Sleep Mode TEMPERATURE RANGE Specified Performance -40 +85 C 20-Bit Mode 20-Bit Mode 360 140 460 140 2.5 3.0 0.45 3.5 A A A A mW mW mW 4.75 5.25 V User Programmable IIH = 10A IIL = 10A IOH = -0.8mA IOL = 1.6mA 0.5 Binary Two's Complement or Offset Binary 2.0 -0.3 3.6 0.4 2.5 DVDD +0.3 0.8 V V V V MHz TTL-Compatible CMOS 2.25 2.5 100 2.75 V k To 0.012% 20-Bit Mode, to 0.003% 0.1Hz to 10Hz 1.8 15 1 2 ms ms Vrms GND or VDD 500 20 Indefinite 0 2 * VREF 0.5 V mA pF mA 2 60 1 1 1 10 20-Bit Mode 16 20 1(1) 4 Bits Bits LSB LSB ppm/C LSB ppm/C LSB ppm/C dB CONDITIONS MIN TYP MAX UNITS
NOTES: (1) Valid from AGND + 20mV to AVDD - 20mV, in the 16-bit mode. (2) Applies after calibration, in 16-bit mode. (3) Re-calibration can remove these errors. (4) Ideal output voltage, does not take into account gain and offset error. (5) Valid from AGND +20mV to AVDD -20mV. Outside of this range, settling time may be twice the value indicated. For 16-bit mode, C1 = 2.2nF, C2 = 0.22nF; for 20-bit mode, C1 = 10nF, C2 = 3.3nF.
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DAC1220
2
PIN CONFIGURATION
Top View SSOP
PIN DESCRIPTIONS
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME DVDD XOUT XIN DGND AVDD DNC DNC DNC C1 C2 VOUT VREF AGND CS SDIO SCLK DESCRIPTION Digital Supply, +5V nominal System Clock Output (for Crystal) System Clock Input Digital Ground Analog Supply, +5V nominal Do Not Connect Do Not Connect Do Not Connect Filter Capacitor, see text. Filter Capacitor, see text. Analog Output Voltage Reference Input Analog Ground Chip Select Input Serial Data Input/Output Clock Input for Serial Data Transfer
DVDD XOUT XIN DGND AVDD DNC DNC DNC
1 2 3 4 DAC1220E 5 6 7 8
16 15 14 13 12 11 10 9
SCLK SDIO CS AGND VREF VOUT C2 C1
ABSOLUTE MAXIMUM RATINGS(1)
AVDD to DVDD ................................................................................... 0.3V AVDD to AGND ........................................................................ -0.3V to 6V DVDD to DGND ....................................................................... -0.3V to 6V AGND to DGND ............................................................................... 0.3V VREF Voltage to AGND .......................................................... 2.0V to 3.0V Digital Input Voltage to DGND .............................. -0.3V to DVDD + 0.3V Digital Output Voltage to DGND ........................... -0.3V to DVDD + 0.3V Package Power Dissipation ............................................. (TJMAX - TA)/JA Maximum Junction Temperature (TJMAX) ..................................... +150C Thermal Resistance, JA 16-Lead SSOP ...................................................................... 200C/W Lead Temperature (soldering, 10s) ............................................... +300C NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
MAXIMUM LINEARITY ERROR (LSB) 1 PACKAGE DRAWING NUMBER(1) 322 SPECIFICATION TEMPERATURE RANGE -40C to +85C
PRODUCT DAC1220E
PACKAGE 16-Lead SSOP
ORDERING NUMBER(2) DAC1220E/250 DAC1220E/2K5
TRANSPORT MEDIA Tape and Reel Tape and Reel
"
"
"
"
"
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of "DAC1220E/2K5" will get a single 2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
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3
DAC1220
TYPICAL PERFORMANCE CURVES
At TA = +25C, AVDD = DVDD = +5.0V, fXIN = 2.5MHz, VREF = 2.5V, C1 = 2.2nF and C2 = 0.22nF, calibrated mode, unless otherwise specified.
POWER SUPPLY REJECTION RATIO vs FREQUENCY 60 50 40 30 20 10 0 10 100 Frequency (Hz) 1k 10k 400mVp-p Ripple Mid-Range Output
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LARGE-SIGNAL SETTLING TIME 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2 Time (ms) 3 4
PSRR (dB)
OUTPUT NOISE VOLTAGE vs FREQUENCY 10k
UNIPOLAR OFFSET ERROR vs TEMPERATURE 0.5
1k
Unipolar Offset Error (LSB)
Noise (nV/Hz)
0.25
100
0
10
-0.25
1 10 100 1k 10k 100k 1M Frequency (Hz)
-0.5 -60 -40 -20 0 20 40 60 80 100 Temperature (C)
GAIN ERROR vs TEMPERATURE 2.0 1.5 0.5 0.4
BIPOLAR OFFSET ERROR vs TEMPERATURE
Bipolar Offset Error (LSB)
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
1.0
Gain Error (LSB)
0.5 0 -0.5 -1.0 -1.5 -2.0 -60 -40 -20 0 20 40 60 80 100 Temperature (C)
-60
-40
-20
0
20
40
60
80
100
Temperature (C)
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DAC1220
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TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25C, AVDD = DVDD = +5.0V, fXIN = 2.5MHz, VREF = 2.5V, C1 = 2.2nF and C2 = 0.22nF, calibrated mode, unless otherwise specified.
LINEARITY ERROR vs CODE 10 -40C 8
Linearity Error (ppm)
+25C 6 4 2 0 -2 0 10000 20000 30000 40000 50000 60000 70000 Code +85C
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DAC1220
THEORY OF OPERATION
The DAC1220 is precision, high dynamic range, self-calibrating, 20-bit, delta-sigma D/A converter. It contains a second-order delta-sigma modulator, a first-order switched capacitor filter, a second-order continuous time post filter, a microcontroller including the Instruction, Command and Calibration registers, a serial interface, and a clock generator circuit. The design topology provides low system noise and good power supply rejection. The modulator frequency of the delta-sigma D/A converter is controlled by the system clock. With a 2.5MHz system clock, the delta-sigma D/A converter operates at 312.5kHz. The DAC1220 also includes complete onboard calibration that can correct for internal offset and gain errors. The calibration registers are fully readable and writable. This feature allows for system calibration. The various settings, modes, and registers of the DAC1220 are read or written via a synchronous serial interface. This interface operates as an externally clocked interface. The high resolution and flexibility of the DAC1220 allows this converter to fill a wide variety of D/A conversion tasks. In order to ensure that a particular configuration will meet the design goals, there are several important items which must be considered. These include (but are certainly not limited to) the needed resolution, required linearity, desired settling time, and power consumption goal. The remainder of this data sheet discusses the operation of the DAC1220 in detail. DEFINITION OF TERMS An attempt has been made to be consistent with the terminology used in this data sheet. In that regard, the definition of each term is given as follows: Differential Nonlinearity Error--The differential nonlinearity error is the difference between an actual step width and the ideal value of 1LSB. If the step width is exactly 1LSB, then the differential nonlinearity error is zero. A differential nonlinearity specification of 1LSB guarantees monotonicity. Drift--The drift is the change in a parameter over temperature.
Full-Scale Range (FSR)--The full-scale range of the DAC1220 is defined as the digital code which produces the positive full-scale analog output. For example, when the converter is configured with a 2.5V reference and a gain setting of 2, the full-scale range is [2.5V (positive full scale) * 2] = 5V. Gain Error--The gain error is the difference between gain points on the transfer function after the offset error has been corrected to zero. This error represents a difference in the slope of the actual and ideal transfer functions and as such, corresponds to the same percentage error in each step. Gain error may be adjusted to zero externally. Integral Nonlinearity--The integral nonlinearity error is the deviation of the values on the actual transfer function calculated from data end points. The name "integral nonlinearity" derives from the fact that the summation of the differential nonlinearities, from the bottom up to a particular step, determines the value of the integral nonlinearity at that step. Least Significant Bit (LSB) Weight--This is the theoretical amount of voltage that the voltage at the analog output would change with a change in the digital input code of 1LSB. Main Controller--A generic term for the external microcontroller, microprocessor, or digital signal processor which is controlling the operation of the DAC1220 and writing input data. Monotonicity--Monotonicity assures that the analog output will increase or stay the same for increasing digital input codes. Offset Error--The offset error is the difference between the expected and actual offset points when the digital input is zero. Settling Time--The settling time is the time is takes the output to settle to its new value after the digital code has been changed. It is specified for a worst-case change of all digital zeros to all digital ones and vice versa and is measured from AGND + 20mV to AVDD - 20mV. Voltage Span--This is the magnitude of the typical analog output voltage range. For example, when the converter is configured with a 2.5V reference and placed in a gain setting of 2, the output voltage span is 5.0V. fXIN--The frequency of the crystal oscillator or CMOScompatible input signal at the XIN input of the DAC1220.
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DAC1220
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ANALOG OPERATION
The system clock is divided down to provide the sample clock for the modulator. The sample clock is used by the modulator to convert the multi-bit digital input into a one-bit digital output stream. The use of a 1-bit DAC provides inherent linearity. The digital output stream is then converted into an analog signal via the 1-bit DAC and then filtered by the 1st-order switched capacitor filter. The output of the switched-capacitor filter feeds into the continuous time filter. The continuous time filter uses external capacitors connected between the C1, C2, VREF, and VOUT pins to adjust the settling time. The connections for the capacitors are shown in Figure 1 (C1 connects between the VREF and C1 pins, and C2 connects between the VOUT and C2 pins).
Note that the values in the calibration registers will vary from configuration-to-configuration and from part-to-part. There is no method of reliably computing what a particular calibration register should be to correct for a given amount of system error. Self-Calibration A self-calibration is performed after the bits "01" have been written to the Command Register Operation Mode bits (MD1 through MD0) and a "1" has been written to the Command Register sample-and-hold bit (SH). This initiates a self-calibration on the next clock cycle. The self-calibration starts with the OCR being cleared. The offset correction code is determined by a repeated sequence of auto-zeroing the calibration comparator to the offset reference and then comparing the DAC output to the offset reference value. The end result is then averaged, Binary Two's Complement adjusted, and placed in the OCR. The gain correction is done in a similar fashion except the correction is done against VREF to eliminate common-mode errors. The FCR result represents the gain code and is not Binary Two's Complement adjusted. The calibration function takes between 300ms and 500ms to complete. Once calibration is initiated, further writing of register bits is disabled until calibration completes. The status of calibration can be verified by reading the status of the Command Register Operation Mode bits (MD1 through MD0). These bits will return to normal mode "00" when calibration is complete. Self-calibration can be done with the output isolated or connected. This is done by setting (output connected) or clearing (output isolated) the CALPIN bit in the CMR register. The load at the output affects the calibration accuracy. If the load sinks excessive current, the calibration will be out-of-specification. Output Mode The DAC1220 can operate in either 16-bit mode or 20-bit mode. The mode is determined by setting (20-bit) or clearing (16-bit) the RES bit in the CMR register. The output of the DAC1220 can be synchronously reset. By setting the CLR bit in the CMR, the data input register is cleared to zero. This will result in an output of 0V in unipolar mode or VREF in bipolar mode. The settling time is determined by the DISF, RES, and ADPT bits of the CMR register. By clearing the DISF bit, the enhanced settling filter is disabled. The ADPT bit of the CMR determines whether the data step controls activation of fast settling. By clearing this bit, the adaptive filter is disabled which enables fast settling. The SH bit of the CMR register determines if C2 is internally connected to VREF. By clearing the SH bit, C2 is disconnected from VREF. The CRST bit of the CMR register can be used to reset the offset and calibration registers. By setting the CRST bit, the contents of the calibration register are reset to 0.
DAC1220 VREF VOUT C2 C1 12 11 C2 10 9 C1
FIGURE 1. Capacitor Connections for Settling Time.
CAPACITOR C1 C2 16-BIT MODE 2.2nF 0.22nF 20-BIT MODE 10nF 3.3nF
TABLE I. Capacitor Values. CALIBRATION The DAC1220 offers a self-calibration mode which automatically calibrates the output offset and gain. The calibration is performed once and then normal operation is resumed. In general, calibration is recommended immediately after power-on and whenever there is a "significant" change in the operating environment. The amount of change which should cause a re-calibration is dependent on the application. Where high accuracy is important, re-calibration should be done on changes in temperature and power supply. After a calibration has been accomplished, the Offset Calibration Register (OCR) and the Full-Scale Calibration Register (FCR) contain the results of the calibration. The data in these registers are accurate to the effective resolution of the DAC1220's mode of operation during the calibration. The calibration registers can also be used to provide system offset and gain corrections separate from those computed by the DAC1220. For example, these might be burned into E2PROM during final product testing. On power on, the main controller would load these values into the calibration registers. A further possibility is a look-up table based on the current temperature. 7
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DAC1220
+5V
+5V 0.10F 7 4.99k 2 6 To VREF Pin + 4 10F 0.1F
1
10k + LM4040-2.5
3 10F 0.10F
OPA340
FIGURE 2. Recommended External Voltage Reference Circuit for Best Low Noise Operation with the DAC1220. REFERENCE INPUT The reference input voltage of 2.5V can be directly connected to VREF. Higher reference voltages will cause the fullscale range to increase up to the supply voltage while the internal circuit noise of the converter remains approximately the same. The recommended reference circuit for the DAC1220 is shown in Figure 2. Calibration Registers (OCR and FCR) contain data used for correcting the internal conversion value after it is placed into the DIR. The data in these two registers may be the result of a calibration routine, or they may be values which have been written directly via the serial interface.
INSR DIR CMR OCR FCR Instruction Register Data Input Register Command Register Offset Calibration Register Full-Scale Calibration Register 8 Bits 24 Bits 16 Bits 24 Bits 24 Bits
DIGITAL OPERATION
SYSTEM CONFIGURATION The DAC1220 supports Serial Peripheral Interface (SPI) and Synchronous Serial Interface (SSI) interfaces. Via the serial interface, the DAC1220 is controlled by 8-bit instruction codes and 16-bit command codes. Two kinds of protocol are available for the serial interface: SPI and SSI. SPI is a bytebased, 2-wire serial interface. SSI is a popular 3-wire interface. The serial input is externally clocked in both protocols. The Microcontroller (MC) consists of an ALU and a register bank. The MC has three states: power-on reset, calibration, and normal operation. In the power-on reset state, the MC resets all the registers to their default states. In the calibration state, the MC performs offset and gain self-calibration. In the normal state, the MC performs D/A conversions. The DAC1220 has five internal registers, as shown in Table II. Two of these, the Instruction Register (INSR) and the Command Register (CMR), control the operation of the converter. The Instruction register utilizes an 8-bit instruction code to control the serial interface to determine whether the next operation is either a read or a write, to control the word length and to select the appropriate register to read/ write. Communication with the DAC1220 is controlled via the INSR. Under normal operation, the INSR is written as the first part of each serial communication. The instruction that is sent determines what type of communication will occur next. It is not possible to read the INSR. The Command register has a 16-bit command code to set up the DAC1220 operation mode, resolution mode, settling mode and data format. The Data Input Register (DIR) contains the value for the next conversion. The Offset and Full-Scale
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TABLE II. DAC1220 Registers. Instruction Register (INSR) Each serial communication starts with the 8 bits of the INSR being sent to the DAC1220. This directs the remainder of the communication cycle, which consists of n bytes being read from or written to the DAC1220. The read/write bit, the number of bytes n, and the starting register address are defined, as shown in Table III. When the n bytes have been transferred, the INSR is complete. A new communication cycle is initiated by sending a new INSR (under restrictions outlined in the Interfacing section).
MSB R/W MB1 MB0 0 A3 A3 A1 LSB A0
TABLE III. Instruction Register. NOTE: INSR is a write-only register with the MSB (most significant byte and bit) be written first, independent of the BD bit. R/W (Read/Write) Bit--For a write operation to occur, this bit of the INSR must be 0. For a read, this bit must be 1, as follows:
R/W 0 1 Write Read
DAC1220
8
MB1, MB0 (Multiple Bytes) Bits--These two bits are used to control the word length (number of bytes) of the read or write operation, as follows:
MB1 0 0 1 1 MB0 0 1 0 1 1 Byte 2 Bytes 3 Bytes 4 Bytes
RES (Resolution) Bit--The Resolution bit selects either 16-bit or 20-bit resolution.
RES 0 1 16-Bit 20-Bit Default
A3 - A0 (Address) Bits--These four bits select the beginning register location which will be read from or written to, as shown in Table IV. Each subsequent byte will be read from or written to the next higher location. (If the BD bit in the Command register is set, each subsequent byte will be read from the next lower location. This bit does not affect the write operation.) If the next location is not defined in Table IV, the results are unknown. Reading or writing continues until the number of bytes specified by MB1 and MB0 have been transferred.
A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Data Input Register Byte 2 Data Input Register Byte 1 Data Input Register Byte 0 Reserved Command Register Byte 1 Command Register Byte 0 Reserved Reserved Offset Cal Register Byte 2 Offset Cal Register Byte 1 Offset Cal Register Byte 0 Reserved Full-Scale Cal Register Byte 2 Full-Scale Cal Reigster Byte 1 Full-Scale Cal Register Byte 0 Reserved
CLR (Clear) Bit--The clear bit synchronously resets the data input register to zero. The analog output will be based on the DF bit (1 = unipolar for 0V output, 0 = bipolar for VREF output).
CLR 0 1 OFF ON Default
DF (Data Format) Bit--The DF bit controls the format of the input data, either Binary Two's Complement (bipolar) or Offset Binary (unipolar), as follows:
DF 0 1 Binary Two's Complement (bipolar) Default Offset Binary (unipolar)
DISF (Disable Enhanced Settling of Filter) Bit--The disable enhanced settling of filter bit disables the settling filter. The time for settling is dependent upon this bit setting, the RES bit, and the ADPT bit.
DISF 0 1 Disabled Enabled Default
TABLE IV. A3 - A0 Addressing. Command Register (CMR) The CMR controls all of the functionality of the DAC1220. The new configuration takes effect on the negative transition of SCLK for the last bit in each byte of data being written to the Command register. The organization of the CMR is comprised of 16 bits of information in 2 bytes of 8 bits each.
MSB ADPT CALPIN SH Byte 1 0 Byte 0 RES CLR DF DISF BD MSB MD1 1 0 CRST X LSB MD0
BD (Byte Order) Bit--The BD bit controls the order in which bytes of data are read, either most significant byte first or least significant byte first, as follows:
BD 0 1 Byte Access from MSB Byte to LSB Byte Byte Access From LSB Byte from LSB Byte to MSB Byte Default
MSB (Bit Order) Bit--The MSB bit controls the order in which bits within a byte of data are read, either most significant bit first or least significant bit first, as follows:
MSB 0 1 MSB-First LSB-First Default
NOTE: In order to obtain optimal performance, the default bit states for the Command Register should be used (refer to Table VI). The only exception is the SH bit--the default bit state is 0, however, the bit should be set to 1 for optimal performance.
TABLE V. Command Register.
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DAC1220
MD1 - MD0 (Operating Mode) Bits--The Operating Mode bits control the calibration functions of the DAC1220. In operation, the Normal mode is used to perform conversions. The Self-Calibration mode is a one-step calibration sequence that calibrates both the offset and full scale.
MD1 0 0 1 1 MD0 0 1 0 1 Normal Mode Self-Cal Sleep X
Offset Calibration Register (OCR) The OCR is a 24-bit register which contains the offset correction factor that is applied to the digital input before it is transferred to the modulator. The contents of this register will be the result of the self-calibration. The calibration is very precise. The OCR is both readable and writeable via the serial interface. For applications requiring an accurate system calibration, a system calibration can be performed, the results averaged, and a more precise system offset calibration value written back to the OCR. The actual OCR value will change from part to part and with configuration, temperature, and power supply. Thus, the actual OCR value for any arbitrary situation cannot be accurately predicted. That is, a given system offset could not be corrected simply by measuring the error externally, computing a correction factor, and writing that value to the OCR. In addition, be aware that the contents of the OCR are not used to directly correct the digital input. Rather, the correction is a function of the OCR value. This function is linear and two known points can be used as a basis for interpolating intermediate values for the OCR. Consult the Calibration section for more details.
MSB Byte 2 OCR22 OCR21 OCR20 Byte 1 OCR15 OCR14 OCR13 OCR12 Byte 0 OCR11 OCR10 OCR9 OCR8 LSB OCR3 OCR2 OCR1 OCR0 OCR19 OCR18 OCR17 OCR16
ADPT (Adaptive Filter) Bit--The Adaptive Filter bit determines if the adaptive filter is enabled or disabled. Disabling this bit will always do fast settling.
ADPT 0 1 Enabled Disabled Default
CALPIN (Calibration Pin) Bit--The Calibration Pin bit determines if the output is isolated or connected during calibration.
CALPIN 0 1 Output Isolated Output Connected Default
OCR23
SH (Sample/Hold) Bit --The Sample-and-Hold bit determines if C2 is internally connected to VREF. For best performance, it is recommended to set this bit to 1.
SH 0 1 Disconnected Connected Default Recommended
OCR7
OCR6
OCR5
OCR4
TABLE VII. Offset Calibration Register. Full-Scale Calibration Register (FCR) The FCR is a 24-bit register which contains the full-scale correction factor that is applied to the digital input before it is transferred to the modulator. The contents of this register will be the result of a self-calibration. The FCR is both readable and writable via the serial interface. For applications requiring an accurate system calibration, a system calibration can be performed, the results averaged, and a more precise system offset calibration value written back to the FCR. The actual FCR value will change from part to part and with configuration, temperature, and power supply. Thus, the actual FCR value for any arbitrary situation cannot be accurately predicted. That is, a given system full-scale error cannot be corrected simply by measuring the error externally, computing a correction factor, and writing that value to the FCR. In addition, be aware that the contents of the FCR are not used to directly correct the digital input. Rather, the correction is a function of the FCR value. This function is linear and two known points can be used as a basis for interpolating intermediate values for the FCR. Consult the Calibration
CRST (Calibration Reset) Bit--The CRST bit resets the offset and full-scale calibration registers.
CRST 0 1 OFF Reset Default
MSB 0 0 0
Byte 1 0(1) Byte 0 1(1) 0(1) 0 0(1) LSB 0 0 0 0
0
0
0
0
NOTE: (1) These bit locations are readable and writable. Modifying these bit values will reduce the performance of the device.
TABLE VI. Command Register Default Condition.
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section for more details. The contents of the FCR are in unsigned binary format. This is not affected by the DF bit in the Command register.
MSB FCR23 FCR22 FCR21 Byte 2 FCR20 Byte 1 FCR15 FCR14 FCR13 FCR12 Byte 0 FCR7 FCR6 FCR5 FCR4 FCR3 FCR2 FCR1 FCR11 FCR10 FCR9 FCR8 LSB FCR0 FCR19 FCR18 FCR17 FCR16
Once serial communication is resumed, the Sleep mode is exited by changing the MD1 - MD0 bits to any other mode. When a new mode (other than Sleep) has been entered, the DAC1220 will execute a very brief internal power-up sequence of the analog and digital circuitry. In addition, the settling of the external VREF and other circuitry must be taken into account to determine the amount of time required to resume normal operation. SERIAL INTERFACE The DAC1220 includes a flexible serial interface which can be connected to microcontrollers and digital signal processors in a variety of ways. Along with this flexibility, there is also a good deal of complexity. This section describes the trade-offs between the different types of interfacing methods in a top-down approach--starting with the overall flow and control of serial data, moving to specific interface examples, and then providing information on various issues related to the serial interface. The serial interface has two basic protocols which are SPI (Serial Peripheral Interface) and SSI (Synchronous Serial Interface). Reset, Power-On Reset and Brown-Out The DAC1220 contains an internal power-on reset circuit. If the power supply ramp rate is greater than 50mV/ms, this circuit will be adequate to ensure the device powers up correctly. (Due to oscillator settling considerations, communication to and from the DAC1220 should not occur for at least 25ms after power is stable.) If this requirement cannot be met or if the circuit has brownout considerations, the timing diagram of Figure 3 can be used to reset the DAC1220. This accomplishes the reset by controlling the duty cycle of the SCLK input. In general, reset is required after power-up, after a brown-out has been detected, or when a watchdog timer event has occurred. I/O Recovery If serial communication stops during an instruction or data transfer for longer than 4 tDATA, the DAC1220 will reset its serial interface. This will not affect the internal registers. The main controller must not continue the transfer after this event but, must restart the transfer from the beginning. This feature is very useful if the main controller can be reset at any point. After reset, simply wait 8 tDATA before starting serial communication.
TABLE VIII. Full-Scale Calibration Register. Data Input Register (DIR) The DIR is a 24-bit register which contains the digital input value (see Table IX). The register is latched on the falling edge of the LSB. The contents of the DIR are then loaded into the modulator. In the 16-bit mode, DIR23 through DIR8 are used to represent the 16-bit value. Therefore, the register data is latched on the falling edge of DIR8. In 20-bit mode, DIR23 through DIR4 are used to represent the 20-bit value. Therefore, the register data is latched on the falling edge of DIR4. The contents of the DIR Register can be Binary Two's Complement (bipolar mode) or Offset Binary (unipolar mode).
MSB DIR23 DIR22 DIR21 Byte 2 DIR20 Byte 1 DIR15 DIR14 DIR13 DIR12 Byte 0 DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR11 DIR10 DIR9 DIR8 LSB DIR0 DIR19 DIR18 DIR17 DIR16
TABLE IX. Data Input Register. SLEEP MODE The Sleep mode is entered after the bits 10 have been written to the Command Register Operation Mode bits (MD1 through MD0). This mode is exited by entering a new mode into the MD1 - MD0 bits. To establish serial communication with the converter while it is in Sleep mode, one of the following procedures must be used: if CS is being used, simply taking CS LOW will enable serial communication to proceed normally. Additionally, if CS is not being used (tied LOW), simply sending a normal Instruction Register command will re-establish communication.
Reset occurs at 1024 * tXIN t2 SCLK t3 t1 t3 t4 t2 t2
t1: > 512 * tXIN < 800 * tXIN t2: > 10 * tXIN t3: > 1024 * tXIN < 1800 * tXIN t4: 2048 * tXIN < 2400 * tXIN
FIGURE 3. Resetting the DAC1220.
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DAC1220
Isolation The serial interface of the DAC1220 provides for simple isolation methods. An example of an isolated two-wire interface is shown in Figure 4. Using CS The serial interface may make use of the CS signal, or this input may simply be tied LOW. There are several issues associated with choosing to do one or the other. The CS signal does not directly control the tri-state condition of the SDIO output. These signals are normally in the tri-state condition. They only become active when serial data is being transmitted from the DAC1220. If the DAC1220 is in the middle of a serial transfer and the SDIO is an output, taking CS HIGH will not tri-state the output signal. If there are multiple serial peripherals utilizing the same serial I/O lines and communication may occur with any peripheral at any time, the CS signal must be used. The CS signal is then used to enable communication with the DAC1220.
Serial Clock The DAC1220 allows multiple instructions to be issued per settling period as well as allowing the main controller to set the serial clock frequency and pace the serial data transfer. There are several important items regarding the serial clock for this mode of operation. The maximum serial clock frequency cannot exceed the DAC1220 XIN frequency divided by 10. TIMING Table X and Figures 5 through 9 define the basic digital timing characteristics of the DAC1220. Figure 5 and the associated timing symbols apply to the XIN input signal. Figures 6 through 9 and associated timing symbols apply to the serial interface signals (SCLK, SDIO, and CS). The serial interface is discussed in detail in the Serial Interface section.
Isolated Power DVDD C1 12pF XTAL 3 C2 12pF AVDD 4 5 6 7 8 DAC1220 1 2 DVDD XOUT XIN DGND AVDD DNC DNC DNC SCLK SDIO CS AGND VREF VOUT C2 C1 16 15 14 13 12 11 C2 10 9 = AGND C1 VGND = DGND VREF Opto Coupler P1.0
Opto Coupler
P1.1
8051
FIGURE 4. Isolation for Two-Wire Interface
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SYMBOL fXIN tXIN t2 t3 t10 t11 t12 t13 t14 t15 t19 t24 t26 t27 t28 t30 t36 t37
DESCRIPTION XIN Clock Frequency XIN Clock Period XIN Clock High XIN Clock LOW External Serial Clock HIGH External Serial Clock LOW Data In Valid to External SCLK Falling Edge (Setup) External SCLK Falling Edge to Data In Not Valid (Hold) Data Out Valid to External SCLK Falling Edge (Setup) External SCLK Falling Edge to Data Out Not Valid (Hold) Falling Edge of Last SCLK for INSR to Rising Edge of First SCLK for Register Data Falling Edge of CS to Rising Edge of SCLK SDIO as Output to Rising Edge of First SCLK for Register Data Falling Edge of Last SCLK for INSR to SDIO Tri-state SDIO Tri-state Time Falling Edge of Last SCLK for Register Data to SDIO Tri-State Falling Edge of Last SCLK for Register Data to Rising Edge of First SCLK of next INSR (CS Tied LOW) Rising Edge of CS to Falling Edge of CS (Using CS)
MIN 0.5 400 0.4 * tXIN 0.4 * tXIN 5 * tXIN 5 * tXIN 40 20 tXIN -40 4 * tXIN 13 * tXIN 11 * tXIN
NOM 1
MAX 2.5 2000
UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns
4 * tXIN 6 * tXIN 2 * tXIN 4 * tXIN 41 * tXIN 22 * tXIN 6 * tXIN 8 * tXIN
ns ns ns ns ns ns
TABLE X. Digital Timing Characteristics.
t10
tXIN t2 XIN
SDIO
t11
t12
t14
t3
SCLK (External) t13 t15
FIGURE 5. XIN Clock Timing.
FIGURE 6. Serial Input/Output Timing.
t19 SCLK SDIO IN7 IN1 IN0 INM IN1 IN0
t36
IN7
Write Register Data SDIO IN7 IN1 IN0 OUTM OUT1 OUT0 IN7
Read Register Data using SDIO
FIGURE 7. Serial Interface Timing (CS LOW).
t37 CS t24 SCLK SDIO IN7 IN1 IN0 Write Register Data SDIO IN7 IN1 IN0 OUTM OUT1 OUT0 IN7 INM IN1 IN0 IN7 t19 t24
Read Register Data Using SDIO SDIO IN7 IN1 IN0 IN7
FIGURE 8. Serial Interface Timing (using CS).
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DAC1220
CS(1) t24 t27 t26 t30 SDIO IN7 IN0 t28 t19 SDIO is an input NOTE: (1) CS is optional. SDIO is an output OUT MSB OUT0
SCLK Slave Mode
FIGURE 9. SDIO Input to Output Transition Timing.
From Read flowchart Start Writing CS taken HIGH for 22 tXIN periods minimum (see text if CS tied LOW) CS state CS state Start Reading
To Write flowchart
CS taken HIGH for 22 tXIN periods minimum (see text if CS tied LOW)
HIGH CS state
HIGH CS state
LOW External device generates 8 serial clock cylces and transmits instruction register data via SDIO
LOW HIGH External device generates 8 serial clock cycles and transmits instruction register data via SDIO
HIGH
LOW
LOW
External device generates n serial clock cycles and transmits specified register data via SDIO
SDIO input to output transition
External device generates n serial clock cycles and receives specified register data via SDIO Yes Is next instruction a read? No SDIO transitions to tri-state condition
More instructions?
See text for restrictions No Yes
End
To Read flowchart
More instructions?
Yes See text for restrictions
Is next instruction a Write?
No
No
Yes
End
To Write flowchart
FIGURE 10. Flowchart for Writing and Reading Register Data.
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LAYOUT
POWER SUPPLIES The DAC1220 requires the digital supply (DVDD) to be no greater than the analog supply (AVDD) +0.3V. In the majority of systems, this means that the analog supply must come up first, followed by the digital supply and VREF. Failure to observe this condition could cause permanent damage to the DAC1220. Inputs to the DAC1220, such as SDIO or VREF should not be present before the analog and digital supplies are on. Violating this condition could cause latch-up. If these signals are present before the supplies are on, series resistors should be used to limit the input current. The best scheme is to power the analog section of the design and AVDD of the DAC1220 from one +5V supply and the digital section (and DVDD) from a separate +5V supply. The analog supply should come up first. This will ensure that SCLK, SDIO, CS and VREF do not exceed AVDD and that the digital inputs are present only after AVDD has been established, and that they do not exceed DVDD. The analog supply should be well regulated and low noise. For designs requiring very high resolution from the DAC1220, power supply rejection will be a concern. See the "PSRR vs Frequency" curve in the Typical Performance Curves section of this data sheet for more information. The requirements for the digital supply are not as strict. However, high frequency noise on DVDD can capacitively couple into the analog portion of the DAC1220. This noise can originate from switching power supplies, very fast microprocessors or digital signal processors. If one supply must be used to power the DAC1220, the AVDD supply should be used to power DVDD. This connection can be made via a 10 resistor which, along with the decoupling capacitors, will provide some filtering between DVDD and AVDD. In some systems, a direct connection can be made. Experimentation may be the best way to determine the appropriate connection between AVDD and DVDD. GROUNDING The analog and digital sections of the design should be carefully and cleanly partitioned. Each section should have its own ground plane with no overlap between them. AGND should be connected to the analog ground plane as well as all other analog grounds. DGND should be connected to the digital ground plane and all digital signals referenced to this plane. The DAC1220 pinout is such that the converter is cleanly separated into an analog and digital portion. This should allow simple layout of the analog and digital sections of the design.
For a single converter system, AGND and DGND of the DAC1220 should be connected together, underneath the converter. Do not join the ground planes, but connect the two with a moderate signal trace. For multiple converters, connect the two ground planes at one location as central to all of the converters as possible. In some cases, experimentation may be required to find the best point to connect the two planes together. The printed circuit board can be designed to provide different analog/digital ground connections via short jumpers. The initial prototype can be used to establish which connection works best. DECOUPLING Good decoupling practices should be used for the DAC1220 and for all components in the design. All decoupling capacitors, but specifically the 0.1F ceramic capacitors, should be placed as close as possible to the pin being decoupled. A 1F to 10F capacitor, in parallel with a 0.1F ceramic capacitor, should be used to decouple AVDD to AGND. At a minimum, a 0.1F ceramic capacitor should be used to decouple DVDD to DGND, as well as for the digital supply on each digital component. SYSTEM CONSIDERATIONS The recommendations for power supplies and grounding will change depending on the requirements and specific design of the overall system. In general, a system can be broken up into four different stages: Digital Processing Digital Portion of the DAC1220 Analog Portion of the DAC1220 Analog Processing For the simplest system consisting of a self-contained microcontroller, one clock source, and minimal analog signal conditioning (basic filtering and gain), high performance could be achieved by powering all components by a common power supply. In addition, all components could share a common ground plane. Thus, there would be no distinctions between "analog" and "digital" power and ground. The layout should still include a power plane, a ground plane, and careful decoupling. In a more extreme case, the design could include: multiple DAC1220s; one or more microcontrollers, digital signal processors, or microprocessors; many different clock sources; or extensive analog signal conditioning and interconnections to various other systems. High performance will be very difficult to achieve for this design. The approach would be to break the system into as many different parts as possible. For example, each DAC1220 may have its own analog power and ground (possibly shared with the analog back end), and its own "digital" power and ground. The converter's "digital" power and ground would be separate from the power and ground for the system's processors, RAM, ROM, and "glue" logic.
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DAC1220

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