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DAC122S085 12-Bit Micro Power DUAL Digital-to-Analog Converter with Rail-to-Rail Output
PRELIMINARY
May 2006
DAC122S085 12-Bit Micro Power DUAL Digital-to-Analog Converter with Rail-to-Rail Output
General Description
The DAC122S085 is a full-featured, general purpose DUAL 12-bit voltage-output digital-to-analog converter (DAC) that can operate from a single +2.7V to 5.5V supply and consumes 210 A at 3V and 320 A at 5V. The DAC122S085 is packaged in 10-lead LLP and MSOP packages. The 10-lead LLP package makes the DAC122S085 the smallest DUAL DAC in its class. The on-chip output amplifier allows rail-torail output swing and the three wire serial interface operates at clock rates up to 40 MHz over the entire supply voltage range. Competitive devices are limited to 25 MHz clock rates at supply voltages in the 2.7V to 3.6V range. The serial interface is compatible with standard SPITM, QSPI, MICROWIRE and DSP interfaces. The reference for the DAC122S085 serves all four channels and can vary in voltage between 1V and VA, providing the widest possible output dynamic range. The DAC122S085 has a 16-bit input shift register that controls the outputs to be updated, the mode of operation, the powerdown condition, and the binary input data. Both outputs can be updated simultaneously or individually depending on the setting of the two mode of operation bits. A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a valid write to the device. A power-down feature reduces power consumption to less than a microWatt with three different termination options. The low power consumption and small packages of the DAC122S085 make it an excellent choice for use in battery operated equipment. The DAC122S085 is one of a family of pin compatible DACs, including the 8-bit DAC082S085 and the 10-bit DAC102S085. The DAC122S085 operates over the extended industrial temperature range of -40C to +105C.
Features
n n n n n n n n Guaranteed Monotonicity Low Power Operation Rail-to-Rail Voltage Output Power-on Reset to 0V Simultaneous Output Updating Wide power supply range (+2.7V to +5.5V) Industry's Smallest Package Power Down Modes
Key Specifications
n n n n n n n Resolution 12 bits 8 LSB (max) INL DNL +0.7 / -0.5 LSB (max) Settling Time 8.5 s (max) Zero Code Error +15 mV (max) Full-Scale Error -0.75 %FS (max) Power Consumption -- Normal 270 A (3.6V) / 410 A (5.5V) max -- Pwr Down 20 nA (3.6V) / 30 nA (5.5V) typ
Applications
n n n n Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage & Current Sources Programmable Attenuators
Pin Configuration
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SPITM is a trademark of Motorola, Inc.
(c) 2006 National Semiconductor Corporation
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DAC122S085
Ordering Information
Order Numbers DAC122S085CISD DAC122S085CISDX DAC122S085CIMM DAC122S085CIMMX DAC122S085EVAL Temperature Range -40C TA +105C -40C TA +105C -40C TA +105C -40C TA +105C Package LLP LLP Tape-and-Reel MSOP MSOP Tape-and-Reel Evaluation Board Top Mark X73C X73C X72C X72C
Block Diagram
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DAC122S085
Pin Descriptions
LLP MSOP Pin No. 1 2 3 4 5 6 7 Symbol VA VOUTA VOUTB NC NC GND VREFIN Ground Analog Input Type Supply Analog Output Analog Output Description Power supply input. Must be decoupled to GND. Channel A Analog Output Voltage. Channel B Analog Output Voltage. Not Connected Not Connected Ground reference for all on-chip circuitry. Unbuffered reference voltage shared by both channels. Must be decoupled to GND. Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC. Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin. Exposed die attach pad can be connected to ground or left floating. Soldering the pad to the PCB offers optimal thermal performance and enhances package self-alignment during reflow.
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DIN
Digital Input
9
SYNC
Digital Input
10
SCLK
Digital Input
11
PAD (LLP only)
Ground
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DAC122S085
Absolute Maximum Ratings
(Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage, VA Voltage on any Input Pin Input Current at Any Pin (Note 3) Package Input Current (Note 3) Power Consumption at TA = 25C ESD Susceptibility (Note 5) Human Body Model Machine Model Soldering Temperature, Infrared, 10 Seconds (Note 6) Storage Temperature 6.5V -0.3V to 6.5V 10 mA 20 mA See (Note 4) 2500V 250V 235C -65C to +150C
Operating Ratings (Notes 1, 2)
Operating Temperature Range Supply Voltage, VA Reference Voltage, VREFIN Any Digital Input Voltage (Note 7) Output Load SCLK Frequency -40C TA +105C +2.7V to 5.5V +1.0V to VA 0.0V to 5.5V 0 to 1500 pF Up to 40 MHz
Package Thermal Resistances
Package 10-Lead MSOP 10-Lead LLP JA 240C/W 250C/W
Electrical Characteristics
Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. Boldface limits apply for TMIN TA TMAX: all other limits TA = 25C, unless otherwise specified. Symbol Parameter Conditions Typical (Note 9) Limits (Note 9) 12 12 Over Decimal codes 48 to 4047 VA = 2.7V to 5.5V VA = 4.5V to 5.5V (Note 10) ZE FSE GE ZCED TC GE Zero Code Error Full-Scale Error Gain Error Zero Code Error Drift Gain Error Tempco VA = 3V VA = 5V IOUT = 0 IOUT = 0 All ones Loaded to DAC register Units (Limits) Bits (min) Bits (min) LSB (max) LSB (max) LSB (min) LSB (max) mV (max) %FSR (max) %FSR V/C ppm/C ppm/C 0 VREFIN V (min) V (max) A (max) mV mV mV mV V V V V
STATIC PERFORMANCE Resolution Monotonicity INL DNL Integral Non-Linearity Differential Non-Linearity
2.4
+0.2 -0.1
8
+0.7 -0.5
0.15
+4 -0.1 -0.2 -20 -0.7 -1.0
0.5
+15 -0.75 -1.0
OUTPUT CHARACTERISTICS Output Voltage Range IOUT Output Current (Note 10) VA = 3V, IOUT = 200 A ZCO Zero Code Output VA = 3V, IOUT = 1 mA VA = 5V, IOUT = 200 A VA = 5V, IOUT = 1 mA VA = 3V, IOUT = 200 A FSO Full Scale Output VA = 3V, IOUT = 1 mA VA = 5V, IOUT = 200 A VA = 5V, IOUT = 1 mA 1.3 6.0 7.0 10.0 2.984 2.934 4.989 4.958 (Note 10)
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DAC122S085
Electrical Characteristics
(Continued) Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. Boldface limits apply for TMIN TA TMAX: all other limits TA = 25C, unless otherwise specified. Parameter Conditions VA = 3V, VOUT = 0V, Input Code = FFFh VA = 5V, VOUT = 0V, Input Code = FFFh VA = 3V, VOUT = 5V, Input Code = 000h VA = 5V, VOUT = 5V, Input Code = 000h IO CL ZOUT Continuous Output Current (Note 10) Maximum Load Capacitance DC Output Impedance Input Range Minimum Available on each DAC output RL = RL = 2k 1500 1500 7.5 0.2 60 1.0 VA Typical (Note 9) -56 -69 52 75 11 Limits (Note 9) Units (Limits) mA mA mA mA mA (max) pF pF V (min) V (max) k A (max) V (max) V (max) V (min) V (min) pF (max) V (min) V (max) A (max) A (max) A (max) A (max) A (max) A (max) 1.0 1.0 A (max) A (max)
Symbol
IOS
Output Short Circuit Current
INPUT CHARACTERISTICS VREFIN IIN VIL VIH CIN Input Range Maximum Input Impedance Input Current (Note 10) Input Low Voltage (Note 10) Input High Voltage (Note 10) Input Capacitance (Note 10) Supply Voltage Minimum Supply Voltage Maximum VA = 2.7V to 3.6V VA = 4.5V to 5.5V VA = 2.7V to 3.6V VA = 4.5V to 5.5V VA = 2.7V to 3.6V VA = 4.5V to 5.5V VA = 2.7V to 3.6V VA = 4.5V to 5.5V 210 320 190 290 0.02 0.03 0.015 0.025 VA = 3V VA = 5V VA = 3V VA = 5V 0.9 1.5 1.4 2.1
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0.6 0.8 2.1 2.4 3 2.7 5.5 270 410
POWER REQUIREMENTS VA
fSCLK = 30 MHz IN Normal Supply Current (output unloaded) fSCLK = 0
IPD
Power Down Supply Current (output unloaded, SYNC = 0V after PD mode loaded)
All PD Modes, fSCLK = 30 MHz
All PD Modes, fSCLK = 0 (Note 10)
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DAC122S085
A.C. and Timing Characteristics
Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, RL = 2k to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. Boldface limits apply for TMIN TA TMAX: all other limits TA = 25C, unless otherwise specified. Symbol fSCLK ts SR Parameter SCLK Frequency Output Voltage Settling Time (Note 10) Output Slew Rate Glitch Impulse Digital Feedthrough Digital Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion tWU 1/fSCLK tCH tCL tSS tDS tDH tCFSR tSYNC Wake-Up Time SCLK Cycle Time SCLK High time SCLK Low Time SYNC Set-up Time prior to SCLK Falling Edge Data Set-Up Time prior to SCLK Falling Edge Data Hold Time after SCLK Falling Edge SCLK fall prior to rise of SYNC SYNC High Time VREFIN = 2.5V 0.1Vpp VREFIN = 2.5V 0.1Vpp input frequency = 10kHz VA = 3V VA = 5V 0.8 0.5 25 7 7 4 1.5 1.5 0 6 33 10 10 10 3.5 3.5 3 10 Code change from 800h to 7FFh 400h to C00h code change 6 1 12 0.5 1 3 200 Conductions Typical Limits 30 8.5 Units (Limits) MHz (max) s (max) V/s nV-sec nV-sec nV-sec nV-sec kHz dB sec sec ns (min) ns (min) ns (min) ns (min) ns (min) ns (min) ns (min) ns (min)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified Note 3: When the input voltage at any pin exceeds 5.5V or is less than GND, the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (JA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax - TA) / JA. The values for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed). Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k resistor. Machine model is 220 pF discharged through ZERO Ohms. Note 6: See the section entitled "Surface Mount" found in any post 1986 National Semiconductor Linear Data Book for methods of soldering surface mount devices. Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 5.5V, regardless of VA, will not cause errors in the conversion result. For example, if VA is 3V, the digital input pins can be driven with a 5V logic device.
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Note 8: To guarantee accuracy, it is required that VA and VREFIN be well bypassed. Note 9: Typical figures are at TJ = 25C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 10: This parameter is guaranteed by design and/or characterization and is not tested in production.
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DAC122S085
Specification Definitions
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB, which is VREF / 4096 = VA / 4096. DAC-to-DAC CROSSTALK is the glitch impulse transferred to a DAC output in response to a full-scale change in the output of another DAC. DIGITAL CROSSTALK is the glitch impulse transferred to a DAC output at mid-scale in response to a full-scale change in the input register of another DAC. DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the data bus. FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (FFFh) loaded into the DAC and the value of VA x 4095 / 4096. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and FullScale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error. GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register changes. It is specified as the area of the glitch in nanovolt-seconds. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line through the input to output transfer function. The deviation of any given code from this straight line is measured from the center of that code value. The end point method is used. INL for this product is specified over a limited range, per the Electrical Tables. LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is LSB = VREF / 2n where VREF is the supply voltage for this product, and "n" is the DAC resolution in bits, which is 12 for the DAC122S085.
MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output stability maintained. MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when the input code increases. MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is 1/2 of VA. MULTIPLYING BANDWIDTH is the frequency at which the output amplitude falls 3dB below the input sine wave on VREFIN with a full-scale code loaded into the DAC. POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from the power supply. The difference between the supply and output currents is the power consumed by the device without a load. SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is updated. TOTAL HARMONIC DISTORTION (THD) is the measure of the harmonics present at the output of the DACs with an ideal sine wave applied to VREFIN. THD is measured in dB. WAKE-UP TIME is the time for the output to exit powerdown mode. This is the time from the falling edge of the 16th SCLK pulse to when the output voltage deviates from the power-down voltage of 0V. ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been entered.
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DAC122S085
Transfer Characteristic
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FIGURE 1. Input / Output Transfer Characteristic
Timing Diagrams
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FIGURE 2. Serial Timing Diagram
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DAC122S085
Typical Performance Characteristics
unless otherwise stated INL at VA = 3.0V
fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047, INL at VA = 5.0V
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DNL at VA = 3.0V
DNL at VA = 5.0V
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INL/DNL vs VREFIN at VA = 3.0V
INL/DNL vs VREFIN at VA = 5.0V
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DAC122S085
Typical Performance Characteristics fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047,
unless otherwise stated (Continued) INL/DNL vs fSCLK at VA = 2.7V INL/DNL vs VA
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INL/DNL vs Clock Duty Cycle at VA = 3.0V
INL/DNL vs Clock Duty Cycle at VA = 5.0V
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INL/DNL vs Temperature at VA = 3.0V
INL/DNL vs Temperature at VA = 5.0V
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DAC122S085
Typical Performance Characteristics fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047,
unless otherwise stated (Continued) Zero Code Error vs. VA Zero Code Error vs. VREFIN
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Zero Code Error vs. fSCLK
Zero Code Error vs. Clock Duty Cycle
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Zero Code Error vs. Temperature
Full-Scale Error vs. VA
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DAC122S085
Typical Performance Characteristics fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047,
unless otherwise stated (Continued) Full-Scale Error vs. VREFIN Full-Scale Error vs. fSCLK
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Full-Scale Error vs. Clock Duty Cycle
Full-Scale Error vs. Temperature
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Supply Current vs. VA
Supply Current vs. Temperature
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DAC122S085
Typical Performance Characteristics fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047,
unless otherwise stated (Continued) 5V Glitch Response Power-On Reset
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3V Wake-Up Time
5V Wake-Up Time
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DAC122S085
1.0 Functional Description
1.1 DAC SECTION The DAC122S085 is fabricated on a CMOS process with an architecture that consists of switches and resistor strings that are followed by an output buffer. The reference voltage is externally applied at VREFIN and is shared by all four DACs. For simplicity, a single resistor string is shown in Figure 3. This string consists of 4096 equal valued resistors with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register determines which switch is closed, connecting the proper node to the amplifier. The input coding is straight binary with an ideal output voltage of: VOUTA,B,C,D = VREFIN x (D / 4096) where D is the decimal equivalent of the binary code that is loaded into the DAC register and can take on any value between 0 and 4095. This configuration guarantees that the DAC is monotonic.
mended that VREFIN be driven by a voltage source with low output impedance. The reference voltage range is 1.0V to VA, providing the widest possible output dynamic range. 1.4 SERIAL INTERFACE The three-wire interface is compatible with SPI, QSPI and MICROWIRE, as well as most DSPs and operates at clock rates up to 40 MHz. See the Timing Diagram for information on a write sequence. A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the DIN line is clocked into the 16-bit serial input register on the falling edges of SCLK. To avoid misclocking data into the shift register, it is critical that SYNC not be brought low on a falling edge of SCLK (see Serial Timing Diagram, Figure 2). On the 16th falling clock edge, the last data bit is clocked in and the programmed function (a change in the DAC channel address, mode of operation and/or register contents) is executed. At this point the SYNC line may be kept low or brought high. Any data and clock pusles after the 16th falling clock edge will be ignored. In either case, SYNC must be brought high for the minimum specified time before the next write sequence is initiated with a falling edge of SYNC. Since the SYNC and DIN buffers draw more current when they are high, they should be idled low between write sequences to minimize power consumption. 1.5 INPUT SHIFT REGISTER The input shift register, Figure 4, has sixteen bits. The first bit must be set to "0" and the second bit is an address bit. The address bit determines whether the register data is for DAC A or DAC B. This bit is followed by two bits that determine the mode of operation (writing to a DAC register without updating the outputs of both DACs, writing to a DAC register and updating the outputs of both DACs, writing to the register of both DACs and updating their outputs, or powering down both outputs). The final twelve bits of the shift register are the data bits. The data format is straight binary (MSB first, LSB last), with all 0's corresponding to an output of 0V and all 1's corresponding to a full-scale output of VREFIN - 1 LSB. The contents of the serial input register are transferred to the DAC register on the sixteenth falling edge of SCLK. See Timing Diagram, Figure 2.
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FIGURE 3. DAC Resistor String 1.2 OUTPUT AMPLIFIERS The output amplifiers are rail-to-rail, providing an output voltage range of 0V to VA when the reference is VA. All amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0V and VA, in this case). For this reason, linearity is specified over less than the full output range of the DAC. However, if the reference is less than VA, there is only a loss in linearity in the lowest codes. The output capabilities of the amplifier are described in the Electrical Tables. The output amplifiers are capable of driving a load of 2 k in parallel with 1500 pF to ground or VA. The zero-code and full-scale outputs for given load currents are available in the Electrical Characterisics Table. 1.3 RERENCE VOLTAGE The DAC122S085 has a single external reference that is shared by both channels. The reference pin, VREFIN, is not buffered and has an input impedance of 60 k. It is recom-
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FIGURE 4. Input Register Contents Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the data transfer to the shift register is aborted and the write sequence is invalid. The DAC register is not updated and there is no change in the mode of operation or in the DAC output voltages.
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DAC122S085
1.0 Functional Description
1.6 POWER-ON RESET
(Continued)
a 0.1F capacitor and the VOUT pin with a 2.2F capacitor will improve stability and reduce output noise. The LM4130 comes in a space-saving 5-pin SOT23.
The power-on reset circuit controls the output voltages both DACs during power-up. Upon application of power, the DAC registers are filled with zeros and the output voltages are 0V. The outputs remain at 0V until a valid write sequence is made to the DAC. 1.7 POWER-DOWN MODES The DAC122S085 has four power-down modes, two of which are identical. In power-down, the supply current drops to 20 A at 3V and 30 A at 5V. The DAC122S085 is set in power-down mode by setting OP1 and OP0 to 11. Since this mode powers down both DACs, the first two bits of the shift register are used to select different output terminations for the DAC outputs. Setting them to 00 or 11 causes the outputs to be tri-stated or set to a high impedance state. While setting them to 01 or 10 causes the outputs to be terminated by 2.5 k or 100 k to ground respectively (see Table 1). TABLE 1. Power-Down Modes PD 0 0 1 1 A0 0 1 0 1 OP1 1 1 1 1 OP0 1 1 1 1 Operating Mode High-Z outputs 2.5 k to GND 100 k to GND High-Z outputs
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FIGURE 5. The LM4130 as a power supply 2.1.2 LM4050 Available with accuracy of 0.44%, the LM4050 shunt reference is also a good choice as a reference for the DAC122S085. It is available in 4.096V and 5V versions and comes in a space-saving 3-pin SOT23.
The bias generator, output amplifiers, resistor strings, and other linear circuitry are all shut down in any of the powerdown modes. However, the contents of the DAC registers are unaffected when in power-down. Each DAC register maintains its value prior to the DAC122S085 being powered down unless it is changed during the write sequence which instructed it to recover from power down. Minimum power consumption is achieved in the power-down mode with SYNC and DIN idled low and SCLK disabled. The time to exit power-down (Wake-Up Time) is typically 0.8 sec at 3V and 0.5 sec at 5V.
2.0 Applications Information
2.1 USING REFERENCES AS POWER SUPPLIES While the simplicity of the DAC122S085 implies ease of use, it is important to recognize that the path from the reference input (VREFIN) to the VOUTs will have essentially zero Power Supply Rejection Ratio (PSRR). Therefore, it is necessary to provide a noise-free supply voltage to VREFIN. In order to utilize the full dynamic range of the DAC122S085, the supply pin (VA) and VREFIN can be connected together and share the same supply voltage. Since the DAC122S085 consumes very little power, a reference source may be used as the reference input and/or the supply voltage. The advantages of using a reference source over a voltage regulator are accuracy and stability. Some low noise regulators can also be used. Listed below are a few reference and power supply options for the DAC122S085. 2.1.1 LM4130 The LM4130, with its 0.05% accuracy over temperature, is a good choice as a reference source for the DAC122S085. The 4.096V version is useful if a 0 to 4.095V output range is desirable or acceptable. Bypassing the LM4130 VIN pin with
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FIGURE 6. The LM4050 as a power supply The minimum resistor value in the circuit of Figure 6 must be chosen such that the maximum current through the LM4050 does not exceed its 15 mA rating. The conditions for maximum current include the input voltage at its maximum, the LM4050 voltage at its minimum, and the DAC122S085 drawing zero current. The maximum resistor value must allow the LM4050 to draw more than its minimum current for regulation plus the maximum DAC122S085 current in full operation. The conditions for minimum current include the input voltage at its minimum, the LM4050 voltage at its maximum, the resistor value at its maximum due to tolerance, and the DAC122S085 draws its maximum current. These conditions can be summarized as R(min) = ( VIN(max) - VZ(min) ) /IZ(max) and R(max) = ( VIN(min) - VZ(max) ) / ( (IDAC(max) + IZ(min) ) where VZ(min) and VZ(max) are the nominal LM4050 output voltages the LM4050 output tolerance over temperature, IZ(max) is the maximum allowable current through the
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DAC122S085
2.0 Applications Information
(Continued) LM4050, IZ(min) is the minimum current required by the LM4050 for proper regulation, and IDAC(max) is the maximum DAC122S085 supply current. 2.1.3 LP3985 The LP3985 is a low noise, ultra low dropout voltage regulator with a 3% accuracy over temperature. It is a good choice for applications that do not require a precision reference for the DAC122S085. It comes in 3.0V, 3.3V and 5V versions, among others, and sports a low 30 V noise specification at low frequencies. Since low frequency noise is relatively difficult to filter, this specification could be important for some applications. The LP3985 comes in a space-saving 5-pin SOT23 and 5-bump micro SMD packages.
tors are attractive due to their small size but generally have ESR values that are too low for use with the LP2980. Aluminum electrolytic capacitors are typically not a good choice due to their large size and have ESR values that may be too high at low temperatures. 2.2 BIPOLAR OPERATION The DAC122S085 is designed for single supply operation and thus has a unipolar output. However, a bipolar output may be obtained with the circuit in Figure 9. This circuit will provide an output voltage range of 5 Volts. A rail-to-rail amplifier should be used if the amplifier supplies are limited to 5V.
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FIGURE 9. Bipolar Operation
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FIGURE 7. Using the LP3985 regulator An input capacitance of 1.0F without any ESR requirement is required at the LP3985 input, while a 1.0F ceramic capacitor with an ESR requirement of 5m to 500m is required at the output. Careful interpretation and understanding of the capacitor specification is required to ensure correct device operation. 2.1.4 LP2980 The LP2980 is an ultra low dropout regulator with a 0.5% or 1.0% accuracy over temperature, depending upon grade. It is available in 3.0V, 3.3V and 5V versions, among others.
The output voltage of this circuit for any code is found to be VO = (VA x (D / 4096) x ((R1 + R2) / R1) - VA x R2 / R1) where D is the input code in decimal form. With VA = 5V and R1 = R2, VO = (10 x D / 4096) - 5V A list of rail-to-rail amplifiers suitable for this application are indicated in Table 2. TABLE 2. Some Rail-to-Rail Amplifiers AMP LMC7111 LM7301 LM8261 PKGS DIP-8 SOT23-5 SO-8 SOT23-5 SOT23-5 Typ VOS 0.9 mV 0.03 mV 0.7 mV Typ ISUPPLY 25 A 620 A 1 mA
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FIGURE 8. Using the LP2980 regulator Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor must be at least 1.0F over temperature, but values of 2.2F or more will provide even better performance. The ESR of this capacitor should be within the range specified in the LP2980 data sheet. Surface-mount solid tantalum capacitors offer a good combination of small size and ESR. Ceramic capaciwww.national.com 16
DAC122S085
2.0 Applications Information
(Continued) 2.3 DSP/MICROPROCESSOR INTERFACING Interfacing the DAC122S085 to microprocessors and DSPs is quite simple. The following guidelines are offered to hasten the design process. 2.3.1 ADSP-2101/ADSP2103 Interfacing Figure 10 shows a serial interface between the DAC122S085 and the ADSP-2101/ADSP2103. The DSP should be set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control register and should be configured for Internal Clock Operation, Active Low Framing and 16-bit Word Length. Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled.
SCLK. PC7 is taken low to transmit data to the DAC. The 68HC11 transmits data in 8-bit bytes with eight falling clock edges. Data is transmitted with the MSB first. PC7 must remain low after the first eight bits are transferred. A second write cycle is initiated to transmit the second byte of data to the DAC, after which PC7 should be raised to end the write sequence.
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FIGURE 12. 68HC11 Interface 2.3.4 Microwire Interface Figure 13 shows an interface between a Microwire compatible device and the DAC122S085. Data is clocked out on the rising edges of the SK signal. As a result, the SK of the Microwire device needs to be inverted before driving the SCLK of the DAC122S085.
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FIGURE 10. ADSP-2101/2103 Interface 2.3.2 80C51/80L51 Interface A serial interface between the DAC122S085 and the 80C51/ 80L51 microcontroller is shown in Figure 11. The SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown here uses port line P3.3. This line is taken low when data is transmitted to the DAC122S085. Since the 80C51/80L51 transmits 8-bit bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the P3.3 line must be left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the second byte of data, after which port line P3.3 is brought high. The 80C51/80L51 transmit routine must recognize that the 80C51/80L51 transmits data with the LSB first while the DAC122S085 requires data with the MSB first.
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FIGURE 13. Microwire Interface 2.4 LAYOUT, GROUNDING, AND BYPASSING For best accuracy and minimum noise, the printed circuit board containing the DAC122S085 should have separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes. Both of these planes should be located in the same board layer. There should be a single ground plane. A single ground plane is preferred if digital return current does not flow through the analog ground area. Frequently a single ground plane design will utilize a "fencing" technique to prevent the mixing of analog and digital ground current. Separate ground planes should only be utilized when the fencing technique is inadequate. The separate ground planes must be connected in one place, preferably near the DAC122S085. Special care is required to guarantee that digital signals with fast edge rates do not pass over split ground planes. They must always have a continuous return path below their traces. The DAC122S085 power supply should be bypassed with a 10F and a 0.1F capacitor as close as possible to the device with the 0.1F right at the device supply pin. The 10F capacitor should be a tantalum type and the 0.1F capacitor should be a low ESL, low ESR type. The power supply for the DAC122S085 should only be used for analog circuits. Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the board. The clock and data lines should have controlled impedances.
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FIGURE 11. 80C51/80L51 Interface 2.3.3 68HC11 Interface A serial interface between the DAC122S085 and the 68HC11 microcontroller is shown in Figure 12. The SYNC line of the DAC122S085 is driven from a port line (PC7 in the figure), similar to the 80C51/80L51. The 68HC11 should be configured with its CPOL bit as a zero and its CPHA bit as a one. This configuration causes data on the MOSI output to be valid on the falling edge of
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DAC122S085
Physical Dimensions
inches (millimeters) unless otherwise noted
10-Lead MSOP Order Numbers DAC122S085CIMM NS Package Number MUB10A
10-Lead LLP Order Numbers DAC122S085CISD NS Package Number SDA10A
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DAC122S085 12-Bit Micro Power DUAL Digital-to-Analog Converter with Rail-to-Rail Output
Notes
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ``Banned Substances'' as defined in CSP-9-111S2. Leadfree products are RoHS compliant.
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