Part Number Hot Search : 
2SB1645P NTE1497 CN13193 583SYGD ACE1501V MR141L 40D271K MC035
Product Description
Full Text Search
 

To Download DMILL Datasheet File

  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
 
 


  Datasheet File OCR Text:
 Atmel is manufacturing the DMILL technology in its Nantes' factory. Primarily developed to serve the High Energy Physics market, the technology offers versatile components suitable for any advanced mixed or pure digital conception. Taking advantage of SOI use and trench insulators, the SCR structures inherently present in std CMOS technology and responsible for LATCH-UP is totally eliminated. Moreover, in association with outstanding radiation properties, product designed and fabricated with DMILL offers total security for use in highly energetic particle environments.
DMILL Process
Introduction
DMILL is a BiCMOS technology fabricated using Silicon On Insulator (SOI) substrate. The decision to develop new equipment for High Energy Physics (HEP) research has lead to the need of ultra hard technology. The detector electronics adjacent to the collision areas can accumulate radiation doses above 10Mrad. Furthermore, the low level of the detector signals imposes very high signal to noise ratios. To meet these new requirements, the French Commissariat a l'Energie Atomique (CEA), an organization highly involved in almost all advanced nuclear Physics research, has, by taking advantage of its extensive experience in SOI hardened technologies, developed the DMILL technology, a mixed analog/digital technology hardened to tolerate more than 10Mrad and 1014 neutrons/cm.
Rad Hard Mixed Signal Technology
DMILL
DMILL Performance
Active and passive devices The DMILL process offers a designer the possibility to use 4 different active devices, i.e. NMOS, PMOS, NPN Bipolar and PJFET. With regards to advanced analog needs, several passive elements are also available, such as resistors and capacitors. For interconnect, 1 low-rho polysilicon and 2 AlSi layers can be used. Table 1 lists the electrical performance of DMILL. For Radiation hardness reasons, DMILL uses several features, which are silicon consuming. However, trench is efficient to reduce the critical dimension, which is common in BULK CMOS technologies. Thus, the overall layout-inflating factor is limited to 30% compared to a similar 0.8m BiCMOS technology. Today, mixed complex designs have achieved 1Million transistors/cm. Thanks to SOI, parasitic capacitors are reduced. Therefore, the intrinsic speed of the devices is increased compared to similar BULK technology: * *
1.
Integration
Speed
- Propagation delay = 150pS @ ambient temperature (180pS @ 150C) (1) - Bipolar Ft = 5.0GHz at ambient temperature
inverter made of NMOS (4.0x0.8) and PMOS (8.0/0.8)
Rev. B - 24-Aug-01
1
DMILL
Table 1. DMILL basic parameters
Parameter Typ value Unit Description
MOS transistors Leff N Leff P VTN VTP IDSN (0.8m) 0.72 0.70 0.93 -0.80 8.30 m m V V mA Electrical length of a 0.8m N channel transistor Electrical length of a 0.8m N channel transistor Threshold voltage of a 0.8m N channel transistor Threshold voltage of a 0.8m P channel transistor Drain current for a 25/0.8m N transistor with VGS=VDS=5.0V Drain current for a 25/0.8m P transistor with VGS=VDS=5.0V Drain / Source breakdown voltage at ID = 1.0A
IDSP (0.8m) BVDSS (1A) VTN Field VTP Field NPN bipolar Beta (1.2x1.2) VEARLY BVCE0 BVCB0 P-JFET VPPJ (1.2m)
4.60 >8.00 >10.0 >10.0
mA V V V
250 96 5.70 17.0
NU V V V
NPN 1.2x1.2 ideal forward beta NPN Forward early voltage Breakdown of collector/emitter with base open Breakdown of collector/base with emitter open
1.20
V S/m
Pinch-off voltage of a 100/1.2 P-JFET Drain transconducatnce of a 100/1.2 PJFET (VGS=0V; VDS=-3V)
GDPJ (1.2m) 1.135 Oxides Eox EField Ecapa Resistors RP+ RPRextrins R POL R M1 R M2 118 3550 1650 2.35 0.050 0.040 17.5 470 42.0
nm nm nm
Gate oxide thickness Gate oxide thickness Gate oxide thickness
/square /square /square /square /square /square
P+ resistivity P- resistivity Extrinsic base resistivity Poly gate resistivity Metal 1 resistivity Metal2 resistivity
2
Rev. B - 24-Aug-01
Cross sections
Technology cross-section in Figure 1 gives an indication of how the devices are built on top of the insulator layer of the SOI substrate.
Figure 1. DMILL Technology Cross Section
PMOS PMOS lost area NMOS NMOS lost area NMOS
TRENCH TRENCH
N+ N+
P+ N-
P+ P -
N+ P-
N+
N+ P-
N+
P+
TRENCH
LOCOS
LOCOS
LOCOS
N+ PP-
N+
N+
SIMOX BURRIED OXIDE
SUBSTRAT ( BACK SILICON)
NPN BJT
High Value RES
Capacitor
Biased `lost' area
PJFET (HALF)
N+ N+
LOCOS
N+ N- DRIFT N+ collector P+
PTRENCH
PTRENCH
P-
N+
P-
N+ N+
LOCOS
N+ P- Channel N+ collector P+ P+
SIMOX BURRIED OXIDE
SUBSTRAT (BACK SILICON)
No Latch-Up
The use of combined SOI substrate and lateral isolation by trench removes the usual three-dimensional SRC parasitic structure inherent to CMOS/Bulk technologies. Thus, no Latch-up can be triggered, either by electrical injection or prompt charges deposited by heavy particles during their travel across silicon. The proximity of the electronics from the area the protons collide in HEP experiments makes the radiation requirements extremely high. Some of the circuits will suffer from 30Mrad combined with a fluence of 6.0E14 neutrons/cm after 10 years lifetime! Therefore, particular attention is paid to make all devices radiation hard. Characterizations are conducted using various ionizing particles because of HEP bombarding cocktails. Of particular interest, X and Gamma rays as well as proton and neutron. Cumulated doses up to 30Mrad are regularly deposited to measure post radiation parameter's variation. Hardness demonstration up to 350Mrad was done with a 16bit sliced processor. The following figures give some indication on the repeatability of the radiation hardness of the DMILL process. Notice that Radiation induced drifts are continuously verified and Statistical Process Control is in force, as for any other technological parameter (thickness, electrical, dimension...).
Radiation properties
3
DMILL
Rev. B - 24-Aug-01
DMILL
Figure 2. NMOS transistor thrshold voltage with dose over production
1200 1000 Vt (mV) 800 600 400 200 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Batch num ber 0 rad 10 Mrad
Figure 3. PMOS transistor thrshold voltage with dose over production
-1200 -1000 Vt (mV) -800 -600 -400 -200 0
1 2 3 4 5 6 7 8 9 1 0 11 1 2 1 3 14
0 rad 10 Mrad
Batch num ber
Figure 4. NPN gain versus batch numberft
400 350 300 250 200 150 100 50 0 batch num ber Process under optimization Final Process USL@0rad 0 rad 10 Mrad LSL@0rad LSL@10Mrad
4
Rev. B - 24-Aug-01
Figure 5.
NPN gain versus 1MeV equivalent neutron fluence
120
/0 (100A)
100 80 60 40 20 0 1.E+12 1.E+13 1.E+14 1.E+15 1.E+16 b/b0 for Ic=1E-4A
Neutron (p/cm )
Figure 6. PJFET Vp versus 1MeV equivalent neutron fluence
0 -0.2 -0.4 -0.6 -0.8 -1 1.E+12 1.E+13 1.E+14 Neutron (p/cm ) 1.E+15 1.E+16 Ic=100A
Post 10Mrad parameter drifts
To allow designer to assess design robustness, Atmel offers, in the design kit, a set of 10Mrad post irradiation drifts. Therefore, sensitive parameters drift is injected in the simulation. It is recommended to use these numbers in combination with typical technology parameters to avoid over-pessimistic simulation. Since no significant degradation is observed before 1Mrad accumulated dose, most of the space design will not require any post-rad simulation.
Radiation Hardness Assurance
In order to verify the process stability over the production period, Atmel has installed a Radiation Hardness Assurance (RHA) program. Each and every DMILL production run is irradiated up to 10Mrad with 10keV X-rays. This is a non-destructive test performed at wafer level on process control monitors located in the street line (scribe lines) of the wafers. Irradiation is collimated so that customer's circuits are not damaged. Wafers are delivered with a Radiation Certificate of Conformance (CoC) to post radiation specifications that are scheduled in the Electrical Design Rules. The possibility exists to remove this control when not necessary. Single Event Upset is a temporary event that can occur in storing elements by highly energetic particles crossing over the silicon layer. If the quantity of charges deposited by this particle is higher than the stored charge, then, the information contained in the storing element is corrupted. This error is not permanent and can be restored.
SEU characteristics
5
DMILL
Rev. B - 24-Aug-01
DMILL
DMILL is intrinsically hardened against SEU because the silicon layer on top of the insulator is very thin (1.2m). So, deposited charge is very small. Thus, compared to standard Bulk CMOS technology, DMILL offers improved SEU figures:
SEU threshold Storing element Memory Cell DFF cell Combinatorial (MeV/(mg/cm)) 15 70 70 Reduction factor (*) 200 130 40
Note:
(*)
By comparison to standard BULK CMOS technology with similar lithography.
Most importantly for this mixed analog/digital application, Atmel offers SEU hardened cells (DFFs, SRAM) by use of additional logic. Demonstration of the applicability of this technique to various technologies has been done by irradiating cells up to 115 MeV/(mg/cm2) without any SEU detection. SEU must be evaluated on a case-by-case basis. From a digital standpoint, the process provides for latchup-free operation up to the specified radiation limits. If Customer requires performance beyond the radiation parameters, either in Total Dose, or in flux, a fault-tolerant design approach can be adopted. From an analog standpoint, SEU is a more complex issue. SEU depends on a number of variables such as the amount and duration of transients on signal lines, charge stored on (or dissipated from) capacitors, etc. Essentially, this becomes a tradeoff issue where, for instance, capacitors can be made larger so that SEU's have a proportionally smaller effect. Similar tradeoffs exist in almost every type of analog circuit.
6
Rev. B - 24-Aug-01
Noise Characteristics
DMILL devices have particularly low noise properties. This is illustrated in the figures below. Even after 10Mrad accumulated dose, noise figures remain lower than a few nV/Hz. This property is of very high importance for analog designers dealing with low input signals as well as harsh environments. In addition, substrate partitioning is possible with DMILL technology. The use of a lateral trench is a way to reduce noise and parasitic coupling between analog and digital portions of a mixed design. A specific "User's Guide" (RDER2402) is available to give designers techniques to reduce spurious effects and to take into account parasitic elements in complex designs. Figure 7. Noise properties of NMOS transistors up to 10 Mrad
100
nV/sqrt(Hz)
Ic=100A ; Vb=-3V 13 batches 10
1 1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
Frequency (Hz)
Figure 8. Noise properties of PMOS transistors up to 10 Mrad
100
nV/sqrt(Hz)
Ic=100A ; Vb=3V 11 batches 10
1 1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
Frequency (Hz)
7
DMILL
Rev. B - 24-Aug-01
DMILL
Figure 9. Noise properties of PJFET transistors up to 10 Mrad
100
nV/sqrt(Hz)
PJFET 2000/1.2 Ic = 100A 9 batches 10
1 1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
Frequency (Hz)
Figure 10. Noise properties of NPN transistors up to 10 Mrad
100
nV/sqrt(Hz)
NPN 1.2/1.2 ; Ic = 100A 13 batc hes 10
1 1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
Fre que ncy (Hz)
8
Rev. B - 24-Aug-01
Development Tools
Atmel offers, for free, a DMILL design kit. This set of tools allows the designer to develop advanced and highly integrated circuits for mixed analog/digital applications. The design kit, which is being distributed to Customer under the signed Non Disclosure Agreement (NDA), is comprised of several files and paper documents that are included in the Cadence 9502 environment. Part of the content is described in 18.4.1. Topological design rules (RDTR2401) - - - - - - - - - - - Design rules for layout Specific rules for ESD protection Mask generation for drawn layers Electrical parameters (resistance, capacitance, currents, etc.) Electrical models for simulation including -55 to +150C and 250C MOS transistors: BSIM3v3 for ELDO NPN Bipolar: Gummel & Poon PJFET: Spice Corner files (typN / typP; fastN / fastP; slowN / slowP; slowN / fastP; fastN / slowP) Reliability characteristics (Electromigration, Hot Carrier Injection, etc.) DMILL specific characteristics (noise, radiation, etc.)
List of specifications and files
Electrical design rules (RDER2401)
SOI/DMILL design users guide (RDER2402) Included is a set of design rules and techniques to get a first pass yield design with particular focus on parasitic and cross talk effects. Cadence library (v9502) The Cadence library is composed of several files including: DDK DDK.lib DDK.drc Parameters Basic ESD Protection DMILL design kit offers several types of ESD protection depending on I/O structure:
Type Digital Input Protection Analog Input Protection Output Buffer Power Supply protection Description / test Diode & resistor / Specific Poly-contact spacing / > 4000V Grounded gate NMOS transistors / Specific Poly-contact spacing / > 4000V NMOS & PMOS / Specific Poly-contact spacing / > 4000V Grounded gate NMOS transistors / Specific Poly-contact spacing / > 4000V
Cadence library root directory Cadence library file DMILL technology Cadence file DRC format ELDO BSIM3v3 parameters for DMILL in Cadence format Framework independent basic DMILL information
ASSEMBLY rules Bonding Pads are defined and verified by DRC. However, specific rules can be adapted for modern assembly techniques. Scribe lines are defined according to Atmel HIgh RELiability rules. No waiver is accepted since Process Control Monitors must be inserted in those lines.
9
DMILL
Rev. B - 24-Aug-01
DMILL
Digital library In the frame of one CERN funding, a digital std-cell library for automatic place and route has been developed. The content of the library is listed in Table 2. VERILOG and SYNOPSYS libraries are provided. Table 2. Digital Library
Cell function Inverter Power inverter (double drive) Power inverter (triple drive) Power inverter (four-time drive) 2-Input AND 3-Input AND 2-Input NAND 3-Input NAND 4-Input NAND 6-Input NAND 8-Input NAND 2-Input OR 3-Input OR 2-Input NOR 3-Input NOR 4-Input NOR 2- Input exclusive OR 2- Input exclusive NOR 2 x 2 input AND into 2 input NOR 2 input AND into 3 input NOR 2 input OR into 3 input NAND 2 x 2 input OR into 2 input NAND Fulladder 2 to 1 multiplexer 4 to 1 multiplexer 8 to 1 multiplexer 1 to 2 decoder with active low enable 2 to 4 decoder with active low enable Tristate buffer Non inverting buffer D latch with active low reset Symbol Jiv1 Jiv2 Jiv3 Jiv4 Jan2 Jan3 Jnd2 Jnd3 Jnd4 Jnd6 Jnd8 Jor2 Jor3 Jnr2 Jnr3 Jnr4 Jxo2 Jxn2 Jaoi1 Jaoi2 Joai1 Joai2 Jfuadd Jmx2 Jmx4 Jmx8 Jdec2e Jdec4e Jtbuf Jbuf Jldrl
10
Rev. B - 24-Aug-01
Cell function D latch with active high set D Flip-Flop Scan D Flip-Flop D Flip-Flop with active high reset D Flip-Flop with active low set D Flip-Flop with active low set & active high reset JK Flip-Flop with active high reset JK Flip-Flop with active low set Schmitt trigger TTL input TTL input with pull-up resistor CMOS input CMOS input with pull-up resistor CMOS input with pull-down resistor TTL output CMOS output Open drain with pull-up resistor Open drain with pull-down resistor Tri-state output Bidirection: Tri-state out + Schmitt trigger in Bidirection: Tri-state out + Schmitt trigger In + pull-up Bidirection: Tri-state out + TTL in Bidirection: Tri-state out + TTL in + pull-up Bidirection: Tri-state out + CMOS in Analog signal pad with ESD Analog signal pad Digital VDD pad Analog VDD pad Digital VSS pad Analog VSS pad
Symbol Jldsh Jfd Jfd1s Jfdrh Jfdsl Jfdslrh Jfjkrh Jfjksl Jbis1 Jbit1 Jbit2 Jbic1 Jbic2 Jbic3 Jbot1 Jboc1 Jbo2 Jbo3 Jbto1 Jbtbs1 Jbtbs2 Jbtb1 Jbtb2 Jbcb1 Jbia1 Jboa1 Jpdd1 Jpdda1 Jpss1 Jpssa1
11
DMILL
Rev. B - 24-Aug-01
DMILL
Analog library To answer immediate needs, Atmel gives access to a limited set of analog cells. 9 cells are available and described in the Table 3. Table 3. Analog library
Cell function Trimable Band-gap Voltage Reference Band-Gap Voltage Reference 40nA Current generator 50A Current Generator Low Power, Low Voltage High DC Gain Operational Amplifier High DC Gain Folded Cascade Operational Amplifier CMOS Operational Amplifier with class AB output stage Low Noise Charge preamplifier Symbol BGP01 BGP02 IG01 IG02 OPA01 OPA02 OPA03 PRE01
Note:
This list is not exhaustive.
Program Management
Atmel will designate a program manager, with necessary authority for planning and management of financial resources. A program manager will provide Customer with one overall schedule. The schedule will be maintained throughout the life of the contract. Monthly reports, teleconferences, or other reports will be generated as mutually agreed. Any particular event will be immediately reported to Customer when a schedule is affected. Mixed analog/digital development often requires prototyping for function or architecture validation. It is also accepted that analog debug requires several loops to refine design. The prototyping phase allows assessing yield figures before larger scale production. Considering the high Non Recurrent Expenses (NRE) necessary to access ASIC prototyping, Atmel is offering the Multi-Project Wafer (MPW) service. The objective of this approach is to group circuits from different customers together on one single reticule. Thus, sets of masks and numbers of wafers are minimized.
Prototyping
MPW organization
The MPW service is organized for DMILL either at Atmel or through IMEC, a Belgium company in the frame of the Europractice projects context. Starting 4 times a year, MPW runs collect DMILL designs. Under Atmel responsibility, IMEC will receive tape or FTP files. Then, DRC verification will be done on the net-lists and reticule physical placement will be done prior to sending the GDSII tape to Atmel for further mask manufacturing and wafer processing. The lead-time is generally 14 weeks from submission date to die delivery. In addition to pure foundry, additional test and assembly services are possible. More information can be gathered at: www.imec.be/europractice/ More wafer runs can also be organized when requested.
Debug / extended characterization
In case the design of the chip is sub-contracted, the design house can handle several design validation and prototype evaluation. First silicon will be used to verify and characterize the basic functionality as well as electrical performances. Extended verifications
12
Rev. B - 24-Aug-01
can also be conducted over the Military (-55C; +125C) temperature and power supply ranges. A detailed report will be furnished to Customer with available functional and performance margins. When necessary, specific radiation tests such as heavy ion induced Single Event Upset (SEU) sensitivity will be tested on several parts according to the existing standards. When a non-qualified assembly technique or package is used, extended thermal and mechanical characterization can be performed to give Customer proof of suitable quality and reliability. Price and delivery for prototyping Basic MPW offer: - - - - - Fixed price of $800 per mm. Minimum dimension of 10mm No maximum dimension but maximal edge dimension will be limited to 10mm 20 prototypes (non-tested or packaged) will be sent to the customer Quality level is Engineering thus Atmel in-house specifications are in force
Several options are possible and must be clearly identified in the Purchase order, based on prior negotiation with Atmel: - - - - - - Maximum quantity up to 500 parts Inspection level can be done according to the MIL-std 883, tm 2010 cond.B. Parts can be packaged in either hermetic or plastic Wafer can be sent to any subcontractor for any modern assembly technique Wafer can be tested provided positive answer to prior test feasibility study is given etc...
13
DMILL
Rev. B - 24-Aug-01
DMILL
Large scale production
If the MPW approach is not acceptable (confidentiality, quantity, etc.), dedicated runs can be ordered directly with Atmel. The netlist is transferred to the Atmel design center for DRC verification. A GDSII tape is made available for mask generation. The Quantity of wafers necessary to deliver the requested quantity of final products is calculated taking into account manufacturing, test, visual inspection and assembly yields. DMILL maximum production is 150 wafers per week. Different possibilities exist to produce DMILL circuits: - - - - Pure foundry: Wafers are manufactured according to in-house procedures and delivered with a CoC. Tested wafers: Provided a test program is validated, Atmel can either test or sub-contract test of the wafers to sort Good dice. Tested dice: Probed wafers are diced to extract and deliver only good dice. Packaged dice: Provided bonding diagram and prior feasibility study is concluded positively, Atmel can make or can sub-contract assembly of good die to a quality grade selected by Customer. Screened parts: Atmel can conduct or subcontract part screening from commercial up to highest quality level required for space applications. Any combination of the above possibilities
DMILL production
- - Test
The test program is developed according to the requirements of the Source Control Drawing (customer specification). Prototypes coming from previous MPW runs are used to debug both test program and hardware. The final test program will use the frame developed during the prototyping phase with a possible extension according to the final specification. A review of the test program content will be done with Customer representatives prior to production release. Customer may require a Customer Source Inspection (CSI) at any step of the fabrication. Notification to Customer representative will be made at least 15 days prior to the CSI.
Customer Source Inspection
14
Rev. B - 24-Aug-01
Design background
Atmel customers widely use the DMILL technology for various final applications. Today, more than 20cm of different designs have been fabricated for High Energy Physics and Nuclear Industry applications. The application breakdown is roughly 70% HEP, 15% nuclear and 15% misc.
Examples of DMILL designs
1. Advanced Synthesizer Local oscillator: It realizes a PLL Frequency synthesizer based on fractional division, including spurious cancellation technique (SigmaDelta). RF input frequency up to 400MHz. 2. Low noise charge Preamplifier with DC coupling for Large Hadron Collider Experiment 3. Mixed-signal data receiver/clock synchronizer ASIC for analog front end 4. Analog readout for position sensitive radiation detectors 5. Four-channel rad-hard delay generator with 1ns minimum time step 6. 80MHz clock and data recovery circuit 7. Analog signal processor for a calorimeter with a multi-gain preamplifier 8. Sample and hold multiplexer 9. Clock and Digital logic for front end rad-hard electronics 10. Analog memory 11. 12-bit, 5 MHz ADC 12. 4-channel tri-gain shaper 13. 128 channel analog pipeline for MSGC detectors 14. 128 channel preamplifier, shaper, and buffer 15. Analog pulse shape processor 16. 128 x 1 multiplexer 17. Bias generator/pulse generator 18. 128 channel binary readout 19. Bipolar front end preamplifier and comparator 20. Dynamic FIFO 21. De-randomizer and data compressor 22. Charge sensitive preamplifier and shaper 23. 12-bit 40 MHz ADC 24. Satellite thermal controller/multiplexer 25. Bus driver for satellite on-board systems 26. Sun sensor system using Silicon photodiodes 27. Front-end for astrophysics experiment 28. Angular coder for nuclear industry (10Mrad) 29. Nuclear robotics component
15
DMILL
Rev. B - 24-Aug-01
Atmel Wireless & Microcontrollers Sales Offices
France
3, Avenue du Centre 78054 St.-Quentin-en-Yvelines Cedex France Tel: 33130 60 70 00 Fax: 33130 60 71 11
Sweden
Kavallerivaegen 24, Rissne 17402 Sundbyberg Sweden Tel: 468587 48 800 Fax: 468587 48 850
Hong Kong
77 Mody Rd., Tsimshatsui East, Rm.1219 East Kowloon Hong Kong Tel: 85223789 789 Fax: 85223755 733
Germany
Erfurter Strasse 31 85386 Eching Germany Tel: 49893 19 70 0 Fax: 49893 19 46 21 Kruppstrasse 6 45128 Essen Germany Tel: 492 012 47 30 0 Fax: 492 012 47 30 47 Theresienstrasse 2 74072 Heilbronn Germany Tel: 4971 3167 36 36 Fax: 4971 3167 31 63
United Kingdom
Easthampstead Road Bracknell, Berkshire RG12 1LX United Kingdom Tel: 441344707 300 Fax: 441344427 371
Korea
Ste.605,Singsong Bldg. Youngdeungpo-ku 150-010 Seoul Korea Tel: 8227851136 Fax: 8227851137
USA
2325 Orchard Parkway San Jose California 95131 USA-California Tel: 1408441 0311 Fax: 1408436 4200 1465 Route 31, 5th Floor Annandale New Jersey 08801 USA-New Jersey Tel: 1908848 5208 Fax: 1908848 5232
Singapore
25 Tampines Street 92 Singapore 528877 Rep. of Singapore Tel: 65260 8223 Fax: 65787 9819
Taiwan
Wen Hwa 2 Road, Lin Kou Hsiang 244 Taipei Hsien 244 Taiwan, R.O.C. Tel: 88622609 5581 Fax: 88622600 2735
Italy
Via Grosio, 10/8 20151 Milano Italy Tel: 390238037-1 Fax: 390238037-234
Japan
1-24-8 Shinkawa, Chuo-Ku 104-0033 Tokyo Japan Tel: 8133523 3551 Fax: 8133523 7581
Spain
Principe de Vergara, 112 28002 Madrid Spain Tel: 3491564 51 81 Fax: 3491562 75 14
Web site
http://www.atmel-wm.com
(c) Atmel Nantes SA, 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems.
Printed on recycled paper.


▲Up To Search▲   

 
Price & Availability of DMILL

All Rights Reserved © IC-ON-LINE 2003 - 2022  

[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]


 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X