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DSP56F807/D Rev. 8.0, 11/2002
DSP56F807
Technical Data
DSP56F807 16-bit Digital Signal Processor
* * * * Up to 40 MIPS at 80MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture Hardware DO and REP loops MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes 60K x 16-bit words Program Flash 2K x 16-bit words Program RAM 8K x 16-bit words Data Flash 4K x 16-bit words Data RAM 2K x 16-bit words Boot Flash
6 3 4 6
* * * * * * * * * * *
Up to 64K x 16- bit words each of external program and data memory Two 6 channel PWM Modules Four 4 channel, 12-bit ADCs Two Quadrature Decoders CAN 2.0 B Module Two Serial Communication Interfaces (SCIs) Serial Peripheral Interface (SPI) Up to four General Purpose Quad Timers JTAG/OnCETM port for debugging
* * * * *
14 Dedicated and 18 Shared GPIO lines 160-pin LQFP or 160 MAPBGA Packages
PWM Outputs Current Sense Inputs Fault Inputs PWM Outputs Current Sense Inputs Fault Inputs A/D1 A/D2 A/D1 A/D2 ADCA VREF ADCB VREF2
PWMA
RSTO RESET IRQA
EXTBOOT IRQB 6 JTAG/ OnCE Port VPP VCAPC VDD 2 8 VSS 10* Digital Reg VDDA 3 VSSA 3 Analog Reg
PWMB
3 4 4 4 4 4
Low Voltage Supervisor
4
Quadrature Decoder 0 / Quad Timer A Quadrature Decoder 1 / Quad Timer B Quad Timer C
Interrupt Controller
Program Controller and Hardware Looping Unit
Address Generation Unit
Data ALU 16 x 16 + 36 36-Bit MAC Three 16-bit Input Registers Two 36-bit Accumulators
Bit Manipulation Unit
4 2 4 2 2
Program Memory 61440 x 16 Flash 2048 x 16 SRAM Boot Flash 2048 x 16 Flash Data Memory 8192 x 16 Flash 4096 x 16 SRAM
*
PAB
PLL
* *
PDB
* * * *
IPBB CONTROLS 16
CLKO
Quad Timer D / Alt Func CAN 2.0A/B SCI0 or GPIO SCI1 or GPIO SPI or GPIO Dedicated GPIO
XDB2 CGDB XAB1 XAB2
16-Bit DSP56800 Core
XTAL Clock Gen EXTAL
*
INTERRUPT CONTROLS 16 COP/ Watchdog COP RESET MODULE CONTROLS ADDRESS BUS [8:0] DATA BUS [15:0]
2
4 14
ApplicationSpecific Memory & Peripherals
IPBus Bridge (IPBB)
External Bus Interface Unit
External Address Bus Switch External Data Bus Switch Bus Control
A[00:05] 6 10 16 PS Select DS Select WR Enable RD Enable A[06:15] or GPIO-E2:E3 & GPIO-A0:A7 D[00:15]
*includes TCS pin which is reserved for factory use and is tied to VSS
Figure 1. DSP56F807 Block Diagram
(c) Motorola, Inc., 2002. All rights reserved.
Part 1 Overview
1.1 DSP56F807 Features
1.1.1
* * * * * * * * * * * * * *
Digital Signal Processing Core
Efficient 16-bit DSP56800 family DSP engine with dual Harvard architecture As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) Two 36-bit accumulators including extension bits 16-bit bidirectional barrel shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three internal address buses and one external address bus Four internal data buses and one external data bus Instruction set supports both DSP and controller functions Controller style addressing modes and instructions for compact code Efficient C compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/OnCE debug programming interface
1.1.2
* *
Memory
Harvard architecture permits as many as three simultaneous accesses to program and data memory On-chip memory including a low-cost, high-volume flash solution -- 60K x 16-bit words of Program Flash -- 2K x 16-bit words of Program RAM -- 8K x 16-bit words of Data Flash -- 4K x 16-bit words of Data RAM -- 2K x 16-bit words of Boot Flash
*
Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states -- As much as 64K x 16 bits of data memory -- As much as 64K x 16 bits of program memory
1.1.3
*
Peripheral Circuits for DSP56F807
Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and four Fault inputs, fault tolerant design with deadtime insertion, supports both center and edge aligned modes Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions with quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized Two Quadrature Decoders each with four inputs or two additional Quad Timers
* *
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DSP56F807 Technical Data
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DSP56F807 Description
* * * * * * * * * * *
Two dedicated General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D with four pins CAN 2.0 B Module with 2-pin port for transmit and receive Two Serial Communication Interfaces each with two pins (or four additional GPIO lines) Serial Peripheral Interface (SPI) with configurable 4-pin port (or four additional GPIO lines) Computer-Operating Properly (COP) Watchdog timer Two dedicated external interrupt pins 14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins External reset input pin for hardware reset External reset output pin for system reset JTAG/On-Chip Emulation (OnCETM) for unobtrusive, processor speed-independent debugging Software-programmable, Phase Locked Loop-based frequency synthesizer for the DSP core clock
1.1.4
* * * *
Energy Information
Fabricated in high-density CMOS with 5V tolerant, TTL-compatible digital inputs Uses a single 3.3V power supply On-chip regulators for digital and analog circuitry to lower cost and reduce noise Wait and Stop modes available
1.2 DSP56F807 Description
The DSP56F807 is a member of the DSP56800 core-based family of Digital Signal Processors (DSPs). It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the DSP56F807 is well-suited for many applications. The DSP56F807 includes many peripherals that are especially useful for applications such as motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control, engine management, noise suppression, remote utility metering, industrial control for power, lighting, and automation. The DSP56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized control applications. The DSP56F807 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. The DSP56F807 also provides two external dedicated interrupt lines and up to 32 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The DSP56F807 DSP controller includes 60K, 16-bit words of program flash and 8K words of data flash (each programmable through the JTAG port) with 2K words of program RAM and 4K words of data RAM. It also supports program execution from external memory. A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable
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software routines that can be used to program the main program and data flash memory areas. Both program and data flash memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory can also be either bulk or page erased. A key application-specific feature of the DSP56F807 is the inclusion of two Pulse Width Modulator (PWM) modules. These modules each incorporate three complementary, individually programmable PWM signal outputs (each module is also capable of supporting six independent PWM functions for a total of 12 PWM outputs) to enhance motor control functionality. Complementary operation permits programmable deadtime insertion, distortion correction via current sensing by software, and separate top and bottom output polarity control. The up-counter value is programmable to support a continuously variable PWM frequency. Edge and center aligned synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance Motors), and stepper motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard optoisolators. A "smoke-inhibit", write-once protection feature for key parameters is also included. A patented PWM waveform distortion correction circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1 to 16. The PWM modules provide a reference output to synchronize the analog-todigital converters. The DSP56F807 incorporates two separate Quadrature Decoders capable of capturing all four transitions on the two-phase inputs, permitting generation of a number proportional to actual position. Speed computation capabilities accommodate both fast and slow moving shafts. An integrated watchdog timer in the Quadrature Decoder can be programmed with a timeout value to alarm when no shaft motion is detected. Each input is filtered to ensure only true transitions are recorded. This DSP controller also provides a full set of standard programmable peripherals that include two Serial Communications Interfaces (SCI), one Serial Peripheral Interface (SPI), and four Quad Timers. Any of these interfaces can be used as General-Purpose Input/Outputs (GPIO) if that function is not required. A Controller Area Network interface (CAN Version 2.0 A/B compliant), an internal interrupt controller, and 14 dedicated GPIO lines are also included on the DSP56F807.
1.3 "Best in Class" Development Environment
The SDK (Software Development Kit) provides fully debugged peripheral drivers, libraries and interfaces that allow programmers to create their unique C application code independent of component architecture. The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards support concurrent engineering. Together, the SDK, CodeWarrior, and EVMs create a complete, scalable tools solution for easy, fast, and efficient development.
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DSP56F807 Technical Data
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Product Documentation
1.4 Product Documentation
The four documents listed in Table 1 are required for a complete description and proper design with the DSP56F807. Documentation is available from local Motorola distributors, Motorola semiconductor sales offices, Motorola Literature Distribution Centers, or online at http://www.motorola.com/semiconductors/dsp.
Table 1. DSP56F807 Chip Documentation
Topic DSP56800 Family Manual Description Detailed description of the DSP56800 family architecture, and 16-bit DSP core processor and the instruction set Detailed description of memory, peripherals, and interfaces of the DSP56F801, DSP56F803, DSP56F805, and DSP56F807 Electrical and timing specifications, pin descriptions, and package descriptions (this document) Summary description and block diagram of the DSP56F807 core, memory, peripherals and interfaces Order Number DSP56800FM/D
DSP56F801/803/805/807 User's Manual
DSP56F801-7UM/D
DSP56F807 Technical Data Sheet DSP56F807 Product Brief
DSP56F807/D
DSP56F807PB/D
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. A high true (active high) signal is high or a low true (active low) signal is low. A high true (active high) signal is low or a low true (active low) signal is high. Signal/Symbol PIN PIN PIN PIN 1. Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage1 VIL/VOL VIH/VOH VIH/VOH VIL/VOL
"asserted" "deasserted" Examples:
Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
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Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the DSP56F807 are organized into functional groups, as shown in Table 2 and as illustrated in Figure 2. In Table 3 through Table 19, each table row describes the signal or signals present on a pin.
Table 2. Functional Group Pin Allocations
Functional Group Power (VDD or VDDA) Ground (VSS or VSSA) Supply Capacitors & VPP PLL and Clock Address Bus1 Data Bus Bus Control Interrupt and Program Control Dedicated General Purpose Input/Output Pulse Width Modulator (PWM) Ports Serial Peripheral Interface (SPI) Port1 Quadrature Decoder Ports2 Serial Communications Interface (SCI) Ports1 CAN Port Analog to Digital Converter (ADC) Ports Quad Timer Module Ports JTAG/On-Chip Emulation (OnCE) 1. 2. Alternately, GPIO pins Alternately, Quad Timer pins Number of Pins 11 13 4 3 16 16 4 5 14 26 4 8 4 2 20 6 6 Detailed Description Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19
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DSP56F807 Technical Data
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Introduction
Power Port Ground Port Power Port Ground Port
VDD VSS VDDA VSSA
8 10* 3 3
8 6
GPIOB0-7 GPIOD0-5
Dedicated GPIO
6 3
PWMA0-5 ISA0-2 FAULTA0-3 PWMA Port
Other Supply Ports PLL and Clock
VCAPC VPP
2 2
4
EXTAL XTAL CLKO
6 1 1 1 1 6 2 8 1 1 1 3
PWMB0-5 ISB0-2 FAULTB0-3 PWMB Port
DSP56F807
4
SCLK (GPIOE4) MOSI (GPIOE5) MISO (GPIOE6) SS (GPIOE7) SPI Port or GPIO
A0-A5 External Address Bus or GPIO A6-7 (GPIOE2-E3) A8-15 (GPIOA0-A7)
External Data Bus
D0-D15
16
1 1
TXD0 (GPIOE0) RXD0 (GPIOE1)
SCI0 Port or GPIO
PS External Bus Control DS RD WR
1 1 1 1 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 TC0-1 TD0-3 Quad Timers C&D 1 1 MSCAN_RX MSCAN_TX CAN 2 8 ANA0-7 VREF ANB0-7 ADCA Port ADCB Port 1 1 TXD1 (GPIOD6) RXD1 (GPIOD7) SCI1 Port or GPI0
PHASEA0 (TA0) Quadrature Decoder or Quad Timer A PHASEB0 (TA1) INDEX0 (TA2) HOME0 (TA3) PHASEA1 (TB0) Quadrature Decoder1 or Quad Timer B PHASEB1 (TB1) INDEX1 (TB2) HOME1 (TB3) TCK TMS JTAG/OnCE Port TDI TDO TRST DE
IRQA IRQB RESET RSTO EXTBOOT Interrupt/ Program Control
*includes TCS pin which is reserved for factory use and is tied to VSS
Figure 2. DSP56F807 Signals Identified by Functional Group1
1. Alternate pin functionality is shown in parenthesis.
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2.2 Power and Ground Signals
Table 3. Power Inputs
No. of Pins 8 Signal Name VDD Signal Description Power--These pins provide power to the internal structures of the chip, and should all be attached to VDD. Analog Power--This pin is a dedicated power pin for the analog portion of the chip and should be connected to a low noise 3.3V supply.
3
VDDA
Table 4. Grounds
No. of Pins 9 Signal Name VSS Signal Description GND--These pins provide grounding for the internal structures of the chip and should all be attached to VSS. Analog Ground--This pin supplies an analog ground. TCS--This Schmitt pin is reserved for factory use and must be tied to VSS for normal use. In block diagrams, this pin is considered an additional VSS.
3 1
VSSA TCS
Table 5. Supply Capacitors and VPP
No. of Pins 2 Signal Name VCAPC Signal Type Supply State During Reset Supply Signal Description VCAPC - Connect each pin to a 2.2uF bypass capacitor in order to bypass the core logic voltage regulator (required for proper chip operation). For more information, please refer to Section 5.2 VPP - This pin should be left unconnected as an open circuit for normal functionality. VPP2 - This pin should be left unconnected as an open circuit for normal functionality.
1
VPP
Input
Input
1
VPP2
Input
Input
2.3 Clock and Phase Locked Loop Signals
Table 6. PLL and Clock
No. of Pins 1 Signal Name EXTAL Signal Type Input State During Reset Input Signal Description External Crystal Oscillator Input--This input should be connected to an 8MHz external crystal or ceramic resonator. For more information, please refer to Section 3.5. Crystal Oscillator Output--This output should be connected to an 8MHz external crystal or ceramic resonator. For more information, please refer to Section 3.5. This pin can also be connected to an external clock source. For more information, please refer to Section 3.5.2.
1
XTAL
Input/ Output
Chip-driven
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Address, Data, and Bus Control Signals
Table 6. PLL and Clock (Continued)
No. of Pins 1 Signal Name CLKO Signal Type Output State During Reset Chip-driven Signal Description Clock Output--This pin outputs a buffered clock signal. By programming the CLOKSEL[4:0] bits in the CLKO Select Register (CLKOSR), the user can select between outputting a version of the signal applied to XTAL and a version of the DSP master clock at the output of the PLL. The clock frequency on this pin can also be disabled by programming the CLOKSEL[4:0] bits in CLKOSR.
2.4 Address, Data, and Bus Control Signals
Table 7. Address Bus Signals
No. of Pins 6 Signal Name A0-A5 Signal Type Output State During Reset Tri-stated Signal Description Address Bus--A0-A5 specify the address for external program or data memory accesses. Address Bus--A6-A7 specify the address for external program or data memory accesses. Port E GPIO--These two General Purpose I/O (GPIO) pins can individually be programmed as input or output pins. After reset, the default state is Address Bus. 8 A8-A15 Output Tri-stated Address Bus--A8-A15 specify the address for external program or data memory accesses. Port A GPIO--These eight General Purpose I/O (GPIO) pins can be individually programmed as input or output pins. After reset, the default state is Address Bus.
2
A6-A7
Output
Tri-stated
GPIOE2GPIOE3
Input/ Output
Input
GPIOA0GPIOA7
Input/ Output
Input
Table 8. Data Bus Signals
No. of Pins 16 Signal Name D0-D15 Signal Type Input/ Output State During Reset Tri-stated Signal Description Data Bus-- D0-D15 specify the data for external program or data memory accesses. D0-D15 are tri-stated when the external bus is inactive. Internal pullups may be active.
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Table 9. Bus Control Signals
No. of Pins 1 Signal Name PS Signal Type Output State During Reset Tri-stated Signal Description Program Memory Select--PS is asserted low for external program memory access. Data Memory Select--DS is asserted low for external data memory access. Write Enable--WR is asserted during external memory write cycles. When WR is asserted low, pins D0-D15 become outputs and the DSP puts data on the bus. When WR is deasserted high, the external data is latched inside the external device. When WR is asserted, it qualifies the A0-A15, PS, and DS pins. WR can be connected directly to the WE pin of a Static RAM. Read Enable--RD is asserted during external memory read cycles. When RD is asserted low, pins D0-D15 become inputs and an external device is enabled onto the DSP data bus. When RD is deasserted high, the external data is latched inside the DSP. When RD is asserted, it qualifies the A0-A15, PS, and DS pins. RD can be connected directly to the OE pin of a Static RAM or ROM.
1
DS
Output
Tri-stated
1
WR
Output
Tri-stated
1
RD
Output
Tri-stated
2.5 Interrupt and Program Control Signals
Table 10. Interrupt and Program Control Signals
No. of Pins 1 Signal Name IRQA Signal Type Input (Schmitt) State During Reset Input Signal Description External Interrupt Request A--The IRQA input is a synchronized external interrupt request that indicates that an external device is requesting service. It can be programmed to be level-sensitive or negative-edge-triggered. External Interrupt Request B--The IRQB input is an external interrupt request that indicates that an external device is requesting service. It can be programmed to be level-sensitive or negative-edge-triggered. Reset Output--This output reflects the internal reset state of the chip.
1
IRQB
Input (Schmitt)
Input
1
RSTO
Output
Output
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GPIO Signals
Table 10. Interrupt and Program Control Signals (Continued)
No. of Pins 1 Signal Name RESET Signal Type Input (Schmitt) State During Reset Input Signal Description Reset--This input is a direct hardware reset on the processor. When RESET is asserted low, the DSP is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET pin is deasserted, the initial chip operating mode is latched from the EXTBOOT pin. The internal reset signal will be deasserted synchronous with the internal clocks, after a fixed number of internal clocks. To ensure complete hardware reset, RESET and TRST should be asserted together. The only exception occurs in a debugging environment when a hardware DSP reset is required and it is necessary not to reset the OnCE/JTAG module. In this case, assert RESET, but do not assert TRST. 1 EXTBOOT Input (Schmitt) Input External Boot--This input is tied to VDD to force device to boot from off-chip memory. Otherwise, it is tied to VSS.
2.6 GPIO Signals
Table 11. Dedicated General Purpose Input/Output (GPIO) Signals
No. of Pins 8 Signal Name GPIOB0GPIOB7 Signal Type Input or Output State During Reset Input Signal Description Port B GPIO--These eight pins are dedicated General Purpose I/O (GPIO) pins that can individually be programmed as input or output pins. After reset, the default state is GPIO input. 6 GPIOD0GPIOD5 Input or Output Input Port D GPIO--These six pins are dedicated GPIO pins that can individually be programmed as an input or output pins. After reset, the default state is GPIO input.
2.7 Pulse Width Modulator (PWM) Signals
Table 12. Pulse Width Modulator (PWMA and PWMB) Signals
No. of Pins 6 3 Signal Name PWMA0-5 ISA0-2 Signal Type Output Input (Schmitt) Input (Schmitt) Output State During Reset Tri- stated Input Signal Description PWMA0-5-- Six PWMA output pins. ISA0-2-- These three input current status pins are used for top/bottom pulse width correction in complementary channel operation for PWMA. FAULTA0-3-- These Fault input pins are used for disabling selected PWMA outputs in cases where fault conditions originate off-chip. PWMB0-5-- Six PWMB output pins.
4
FAULTA0-3
Input
6
PWMB0-5
Output
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Table 12. Pulse Width Modulator (PWMA and PWMB) Signals (Continued)
No. of Pins 3 Signal Name ISB0-2 Signal Type Input (Schmitt) Input (Schmitt) State During Reset Input Signal Description ISB0-2-- These three input current status pins are used for top/bottom pulse width correction in complementary channel operation for PWMB. FAULTB0-3-- These four Fault input pins are used for disabling selected PWMB outputs in cases where fault conditions originate off-chip.
4
FAULTB0-3
Input
2.8 Serial Peripheral Interface (SPI) Signals
Table 13. Serial Peripheral Interface (SPI) Signals
No. of Pins 1 Signal Name MISO Signal Type Input/ Output State During Reset Input Signal Description SPI Master In/Slave Out (MISO)--This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. Port E GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is MISO. 1 MOSI Input/ Output Input SPI Master Out/Slave In (MOSI)--This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge that the slave device uses to latch the data. Port E GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is MOSI. 1 SCLK Input/ Output Input SPI Serial Clock--In master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. Port E GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is SCLK. 1 SS Input Input SPI Slave Select--In master mode, this pin is used to arbitrate multiple masters. In slave mode, this pin is used to select the slave. Port E GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is SS.
GPIOE6
Input/ Output
Input
GPIOE5
Input/ Output
Input
GPIOE4
Input/ Output
Input
GPIOE7
Input/ Output
Input
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Quadrature Decoder Signals
2.9 Quadrature Decoder Signals
Table 14. Quadrature Decoder (Quad Dec0 and Quad Dec1) Signals
No. of Pins 1 Signal Name PHASEA0 TA0 1 PHASEB0 TA1 Signal Type Input Input/Output Input Input/Output State During Reset Input Input Input Input Signal Description Phase A--Quadrature Decoder #0 PHASEA input TA0--Timer A Channel 0 Phase B--Quadrature Decoder #0 PHASEB input TA1--Timer A Channel 1
1
INDEX0 TA2
Input Input/Output Input Input/Output Input Input/Output Input Input/Output Input Input/Output Input Input/Output
Input Input Input Input Input Input Input Input Input Input Input Input
Index--Quadrature Decoder #0 INDEX input TA2--Timer A Channel 2 Home--Quadrature Decoder #0 HOME input TA3--Timer A Channel 3 Phase A--Quadrature Decoder #1 PHASEA input TB0--Timer B Channel 0 Phase B--Quadrature Decoder #1 PHASEB input TB1--Timer B Channel 1 Index--Quadrature Decoder #1 INDEX input TB2--Timer B Channel 2 Home--Quadrature Decoder #1 HOME input TB3--Timer B Channel 3
1
HOME0 TA3
1
PHASEA1 TB0
1
PHASEB1 TB1
1
INDEX1 TB2
1
HOME1 TB3
2.10 Serial Communications Interface (SCI) Signals
Table 15. Serial Communications Interface (SCI0 and SCI1) Signals
No. of Pins 1 Signal Name TXD0 GPIOE0 Signal Type Output Input/ Output State During Reset Input Input Signal Description Transmit Data (TXD0)--transmit data output Port E GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is SCI output.
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Table 15. Serial Communications Interface (SCI0 and SCI1) Signals (Continued)
No. of Pins 1 Signal Name RXD0 GPIOE1 Signal Type Input Input/ Output State During Reset Input Input Signal Description Receive Data (RXD0)-- receive data input Port E GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is SCI input. 1 TXD1 GPIOD6 Output Input/ Output Input Input Transmit Data (TXD1)--transmit data output Port D GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is SCI output. 1 RXD1 GPIOD7 Input Input/ Output Input Input Receive Data (RXD1)-- receive data input Port D GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is SCI input.
2.11 CAN Signals
Table 16. CAN Module Signals
No. of Pins 1 Signal Name MSCAN_ RX Signal Type Input (Schmitt) Output State During Reset Input Signal Description MSCAN Receive Data--MSCAN input. This pin has an internal pull-up resistor. MSCAN Transmit Data--MSCAN output. CAN output is open-drain output and pull-up resistor is needed.
1
MSCAN_ TX
Output
2.12 Analog-to-Digital Converter (ADC) Signals
Table 17. Analog to Digital Converter Signals
No. of Pins 4 4 1 Signal Name ANA0-3 ANA4-7 VREF Signal Type Input Input Input State During Reset Input Input Input Signal Description ANA0-3--Analog inputs to ADCA channel 1 ANA4-7--Analog inputs to ADCA channel 2 VREF--Analog reference voltage for ADC. Must be set to VDDA-0.3V for optimal performance. ANB0-3--Analog inputs to ADCB, channel 1 ANB4-7--Analog inputs to ADCB, channel 2
4 4
ANB0-3 ANB4-7
Input Input
Input Input
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Quad Timer Module Signals
Table 17. Analog to Digital Converter Signals
No. of Pins 1 Signal Name VREF2 Signal Type Input State During Reset Input Signal Description VREF2--Analog reference voltage for ADC. Must be set to VDDA-0.3V for optimal performance.
2.13 Quad Timer Module Signals
Table 18. Quad Timer Module Signals
No. of Pins 2 4 Signal Name TC0-1 TD0-3 Signal Type Input/Output Input/Output State During Reset Input Input Signal Description TC0-1--Timer C Channels 0 and 1 TD0-3--Timer D Channels 0, 1, 2, and 3
2.14 JTAG/OnCE
Table 19. JTAG/On-Chip Emulation (OnCE) Signals
No. of Pins 1 Signal Name TCK Signal Type Input (Schmitt) Input (Schmitt) Input (Schmitt) Output State During Reset Input, pulled low internally Signal Description Test Clock Input--This input pin provides a gated clock to synchronize the test logic and shift serial data to the JTAG/OnCE port. The pin is connected internally to a pull-down resistor.
1
TMS
Input, pulled Test Mode Select Input--This input pin is used to sequence the high internally JTAG TAP controller's state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Input, pulled Test Data Input--This input pin provides a serial input data high internally stream to the JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Tri-stated Test Data Output--This tri-statable output pin provides a serial output data stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR controller states, and changes on the falling edge of TCK.
1
TDI
1
TDO
1
TRST
Input (Schmitt)
Input, pulled Test Reset--As an input, a low signal on this pin provides a high internally reset signal to the JTAG TAP controller. To ensure complete hardware reset, TRST should be asserted at power-up and whenever RESET is asserted. The only exception occurs in a debugging environment when a hardware DSP reset is required and it is necessary not to reset the OnCE/JTAG module. In this case, assert RESET, but do not assert TRST. Output Debug Event--DE provides a low pulse on recognized debug events.
1
DE
Output
MOTOROLA
DSP56F807 Technical Data
15
Part 3 Specifications
3.1 General Characteristics
The DSP56F807 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The term "5-volt tolerant" refers to the capability of an I/O pin, built on a 3.3V compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such sytems, a bus may carry both 3.3V and 5Vcompatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V 10% during normal operation without causing damage). This 5V tolerant capability therefore offers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged. Absolute maximum ratings given in Table 20 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. The DSP56F807 DC/AC electrical specifications are preliminary and are from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed.
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this highimpedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
Table 20. Absolute Maximum Ratings
Characteristic Supply voltage All other input voltages, excluding Analog inputs Analog inputs, ANA0-7 and VREF Analog inputs EXTAL and XTAL Current drain per pin excluding VDD, VSS, PWM outputs, TCS, VPP, VDDA, VSSA Symbol VDD VIN VIN VIN I Min VSS - 0.3 VSS - 0.3 VSSA- 0.3 VSSA- 0.3 -- Max VSS + 4.0 VSS + 5.5V VDDA+ 0.3 VSSA+ 3.0 10 Unit V V V V mA
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DSP56F807 Technical Data
MOTOROLA
General Characteristics
Table 21. Recommended Operating Conditions
Characteristic Supply voltage, digital Supply Voltage, analog ADC reference voltage Ambient operating temperature Symbol VDD VDDA VREF TA Min 3.0 3.0 2.7 -40 Typ 3.3 3.3 - - Max 3.6 3.6 VDDA 85 Unit V V V C
Table 22. Thermal Characteristics6
Value Characteristic
Comments
Symbol
160-pin LQFP 38.5 35.4 33
160 MBGA 63.4 60.3 49.9
Unit
Notes
Junction to ambient Natural convection Junction to ambient (@1m/sec) Junction to ambient Natural convection Junction to ambient (@1m/sec) Junction to case Junction to center of case I/O pin power dissipation Power dissipation Junction to center of case Four layer board (2s2p) Four layer board (2s2p)
RJA RJMA RJMA (2s2p) RJMA RJC JT P I/O PD PDMAX
C/W C/W C/W
2 2 1,2
31.5 8.6 0.8
46.8 8.1 0.6
C/W C/W C/W W W C
1,2 3 4, 5
User Determined P D = (IDD x VDD + P I/O) (TJ - TA) /JA
Notes:
1. 2. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application. Determined on 2s2p thermal test board. Junction to ambient thermal resistance, Theta-JA (RJA) was simulated to be equivalent to the JEDEC specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on a thermal test board with two internal planes (2s2p where s is the number of signal layers and p is the number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with the non-single layer boards is Theta-JMA. Junction to case thermal resistance, Theta-JC (RJC ), was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the "case" temperature. The basic cold plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink.
3.
MOTOROLA
DSP56F807 Technical Data
17
4.
Thermal Characterization Parameter, Psi-JT (JT ), is the "resistance" from junction to reference point thermocouple on top center of case as defined in JESD51-2. JT is a useful value to use to estimate junction temperature in steady state customer environments. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. See Section 5.1 from more details on thermal design considerations.
5.
6.
3.2 DC Electrical Characteristics
Table 23. DC Electrical Characteristics
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fop = 80MHz
Characteristic Input high voltage (XTAL/EXTAL) Input low voltage (XTAL/EXTAL) Input high voltage (Schmitt trigger inputs)1 Input low voltage (Schmitt trigger inputs)1 Input high voltage (all other digital inputs) Input low voltage (all other digital inputs) Input current high (pullup/pulldown resistors disabled, VIN=VDD) Input current low (pullup/pulldown resistors disabled, VIN=VSS) Input current high (with pullup resistor, VIN=VDD) Input current low (with pullup resistor, VIN=VSS) Input current high (with pulldown resistor, VIN=VDD) Input current low (with pulldown resistor, VIN=VSS) Nominal pullup or pulldown resistor value Input current high (analog inputs, VIN=VDDA)2 Input current low (analog inputs, VIN=VSSA)3 Output High Voltage (at IOH) Output Low Voltage (at IOL) Output source current Output source current Symbol VIHC VILC VIHS VILS VIH VIL IIH Min 2.25 0 2.2 -0.3 2.0 -0.3 -1 Typ -- -- -- -- -- -- -- Max 2.75 0.5 5.5 0.8 5.5 0.8 1 Unit V V V V V V A A A A A A K 15 15 -- 0.4 -- -- A A V V mA mA
IIL
-1
--
1
IIHPU IILPU IIHPD IILPD RPU, RPD IIHA IILA VOH VOL IOH IOL
-1 -210 20 -1
-- -- -- -- 30
1 -50 180 1
-15 -15 VDD - 0.7 -- 4 4
-- -- -- -- -- --
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DSP56F807 Technical Data
MOTOROLA
DC Electrical Characteristics
Table 23. DC Electrical Characteristics (Continued)
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fop = 80MHz
Characteristic PWM pin output source current3 PWM pin output sink current4 Input capacitance Output capacitance VDD supply current Run 6 Wait7 Stop Low Voltage Interrupt, external power supply8 Low Voltage Interrupt, internal power supply9 Power on Reset10 VEIO VEIC VPOR Symbol IOHP IOLP CIN COUT IDDT5 -- -- -- 2.4 2.0 -- 195 170 115 2.7 2.2 1.7 220 200 145 3.0 2.4 2.0 mA mA mA V V V Min 10 16 -- -- Typ -- -- 8 12 Max -- -- -- -- Unit mA mA pF pF
1. Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, TCS, ISA0-2, FAULTA0-3, ISB0-2, FAULTB0-3, TCK, TRST, TMS, TDI, and MSCAN_RX 2. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling. 3. PWM pin output source current measured with 50% duty cycle. 4. PWM pin output sink current measured with 50% duty cycle. 5. IDDT = IDD + IDDA (Total supply current for VDD + VDDA) 6. Run (operating) IDD measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as inputs; measured with all modules enabled. 7. Wait IDD measured using external square wave clock source (fosc = 8MHz) into XTAL; all inputs 0.2V from rail; no DC loads; less than 50pF on all outputs. CL = 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait IDD; measured with PLL enabled. 8. This low voltage interrupt monitors the VDDA external power supply. VDDA is generally connected to the same potential as VDD via separate traces. If VDDA drops below VEIO, an interrupt is generated. Functionality of the device is guaranteed under transient conditions when VDDA>VEIO (between the minimum specified VDD and the point when the VEIO interrupt is generated). 9. This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is regulator drops below VEIC, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not be generated unless the external power supply drops below the minimum specified value (3.0V). 10. Power-on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is ramping up, this signal remains active for as long as the internal 2.5V is below 1.5V typical no matter how long the ramp up rate is. The internally regulated voltage is typically 100 mV less than VDD during ramp up until 2.5V is reached, at which time it self regulates.
MOTOROLA
DSP56F807 Technical Data
19
250
IDD Digital IDD Analog IDD Total
200
150
IDD (mA)
100
50
0
10
20
30
40
50
60
70
80
Freq. (MHz) Figure 3. Maximum Run IDD vs. Frequency (see Note 6. in Table 16)
3.3 AC Electrical Characteristics
Timing waveforms in Section 3.3 are tested using the VIL and VIH levels specified in the DC Characteristics table. In Figure 4 the levels of VIH and VIL for an input signal are shown.
VIH Input Signal Midpoint1 Fall Time
Note: The midpoint is VIL + (VIH - VIL)/2.
Low
High
90% 50% 10%
VIL
Rise Time
Figure 4. Input Signal Measurement References
Figure 5 shows the definitions of the following signal states: * * * * Active state, when a bus or signal is driven, and enters a low impedance state. Tri-stated, when a bus or signal is placed in a high impedance state. Data Valid state, when a signal level has reached VOL or VOH. Data Invalid state, when a signal level is in transition between VOL and VOH.
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DSP56F807 Technical Data
MOTOROLA
Flash Memory Characteristics
Data1 Valid Data1 Data Invalid State Data Active
Data2 Valid Data2 Data Tri-stated
Data3 Valid Data3
Data Active
Figure 5. Signal States
3.4 Flash Memory Characteristics
Table 24. Flash Memory Truth Table
Mode Standby Read Word Program Page Erase Mass Erase 1. 2. 3. 4. 5. 6. 7. 8. XE1 L H H H H YE2 L H H L L SE3 L H L L L OE4 L H L L L PROG5 L L H L L ERASE6 L L L H H MAS17 L L L L H NVSTR8 L L H H H
X address enable, all rows are disabled when XE=0 Y address enable, YMUX is disabled when YE=0 Sense amplifier enable Output enable, tri-state flash data out bus when OE=0 Defines program cycle Defines erase cycle Defines mass erase cycle, erase whole block Defines non-volatile store cycle
Table 25. IFREN Truth Table
Mode Read Word program Page erase Mass erase IFREN=1 Read information block Program information block Erase information block Erase both block IFREN=0 Read main memory block Program main memory block Erase main memory block Erase main memory block
MOTOROLA
DSP56F807 Technical Data
21
Table 26. Flash Timing Parameters
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6V, TA = -40 to +85C, CL 50pF
Characteristic Program time Erase time Mass erase time Endurance1 Data Retention1 @ 5000 cycles Symbol Min 20 20 100 10,000 10 Typ - - - 20,000 30 Max - - - - - Unit us ms ms cycles years Figure Figure 6 Figure 7 Figure 8
Tprog* Terase* Tme*
ECYC DRET
The following parameters should only be used in the Manual Word Programming Mode PROG/ERASE to NVSTR set up time NVSTR hold time NVSTR hold time (mass erase) NVSTR to program set up time Recovery time Cumulative program HV period2 Program hold time3 Address/data set up time3 Address/data hold time3
Tnvs* Tnvh* Tnvh1* Tpgs* Trcv* Thv Tpgh Tads Tadh
- - - - - -
5 5 100 10 1 3
- - - - - -
us us us us us ms
Figure 6, Figure 7, Figure 8 Figure 6, Figure 7 Figure 8 Figure 6 Figure 6, Figure 7, Figure 8 Figure 6
- - -
- - -
- - -
Figure 6 Figure 6 Figure 6
1. One cycle is equal to an erase program and read. 2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be programmed twice before next erase. 3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater. *The flash interface unit provides registers for the control of these parameters.
22
DSP56F807 Technical Data
MOTOROLA
Flash Memory Characteristics
IFREN
XADR
XE Tadh YADR
YE
DIN Tads PROG Tnvs NVSTR Tpgs Thv Tnvh Trcv Tprog Tpgh
Figure 6. Flash Program Cycle
MOTOROLA
DSP56F807 Technical Data
23
IFREN
XADR
XE
YE=SE=OE=MAS1=0
ERASE Tnvs NVSTR Tnvh Terase Trcv
Figure 7. Flash Erase Cycle
IFREN
XADR
XE
MAS1
YE=SE=OE=0
ERASE Tnvs NVSTR Tnvh1 Tme Trcv
Figure 8. Flash Mass Erase Cycle
24
DSP56F807 Technical Data
MOTOROLA
External Clock Operation
3.5 External Clock Operation
The DSP56F807 system clock can be derived from an external crystal or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal must be connected between the EXTAL and XTAL pins.
3.5.1
Crystal Oscillator
The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in Table 28. In Figure 9 a typical crystal oscillator circuit is shown. Follow the crystal supplier's recommendations when selecting a crystal, since crystal parameters determine the component values required to provide maximum stability and reliable start-up. The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time.
EXTAL XTAL Rz
fc
Sample External Crystal Parameters: Rz = 10M fc = 4-8MHz (optimized for 8MHz)
Figure 9. Connecting to a Crystal Oscillator
3.5.2
Ceramic Resonator
It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system design can tolerate the reduced signal integrity. In Figure 10, a typical ceramic resonator circuit is shown. Refer to supplier's recommendations when selecting a ceramic resonator and associated components. The resonator and components should be mounted as close as possible to the EXTAL and XTAL pins.
Sample Ceramic ResonatorParameters: Rz = 10M fc = 4-8MHz (optimized for 8MHz)
EXTAL XTAL Rz
fc
Figure 10. Connecting a Ceramic Resonator
Note: Motorola recommends only two terminal ceramic resonators vs. three terminal resonators (which contain an internal bypass capacitor to ground).
MOTOROLA
DSP56F807 Technical Data
25
3.5.3
External Clock Source
The recommended method of connecting an external clock is given in Figure 11. The external clock source is connected to XTAL and the EXTAL pin is grounded.
DSP56F807 XTAL EXTAL External Clock VSS
Figure 11. Connecting an External Clock Signal
Table 27. External Clock Operation Timing Requirements5
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C
Characteristic Frequency of operation (external clock driver)1 Clock Pulse Width2, 3 1. 2. 3. Symbol fosc tPW Min 0 6.25 Typ -- -- Max 80 -- Unit MHz ns
See Figure 11 for details on using the recommended connection of an external clock driver. The high or low pulse width must be no smaller than 6.25 ns or the chip will not function. Parameters listed are guaranteed by design.
VIH
External Clock
90% 50% 10%
90% 50% 10%
tPW
tPW
VIL
Note: The midpoint is VIL + (VIH - VIL)/2.
Figure 12. External Clock Timing
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DSP56F807 Technical Data
MOTOROLA
External Bus Asynchronous Timing
3.5.4
Phase Locked Loop Timing
Table 28. PLL Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C
Characteristic External reference crystal frequency for the PLL1 PLL output frequency2 PLL stabilization time3 0o to +85oC PLL stabilization time3 -40o to 0oC Symbol fosc fout/2 tplls tplls Min 4 40 -- -- Typ 8 -- 1 100 Max 10 110 10 200 Unit MHz MHz ms ms
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 8MHz input crystal.2. 2. ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter in the User Manual. ZCLK = fop 3. This is the minimum time required after the PLL setup is changed to ensure reliable operation.
3.6 External Bus Asynchronous Timing
Table 29. External Bus Asynchronous Timing1,2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fop = 80MHz
Characteristic Address Valid to WR Asserted WR Width Asserted Wait states = 0 Wait states > 0 WR Asserted to D0-D15 Out Valid Data Out Hold Time from WR Deasserted Data Out Set Up Time to WR Deasserted Wait states = 0 Wait states > 0 RD Deasserted to Address Not Valid Address Valid to RD Deasserted Wait states = 0 Wait states > 0 Input Data Hold to RD Deasserted RD Assertion Width Wait states = 0 Wait states > 0 Symbol tAWR tWR 7.5 (T*WS)+7.5 tWRD tDOH tDOS 2.2 (T*WS)+6.4 tRDA tARDD 18.7 (T*WS) + 18.7 tDRD tRD 19 (T*WS)+19 -- -- ns ns 0 -- 0 -- -- -- -- ns ns ns ns ns ns -- 4.8 -- -- T + 4.2 -- ns ns ns ns Min 6.5 Max -- Unit ns
MOTOROLA
DSP56F807 Technical Data
27
Table 29. External Bus Asynchronous Timing1,2 (Continued)
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fop = 80MHz
Characteristic Address Valid to Input Data Valid Wait states = 0 Wait states > 0 Address Valid to RD Asserted RD Asserted to Input Data Valid Wait states = 0 Wait states > 0 WR Deasserted to RD Asserted RD Deasserted to RD Asserted WR Deasserted to WR Asserted RD Deasserted to WR Asserted Symbol tAD -- -- tARDA tRDD -- -- tWRRD tRDRD tWRWR tRDWR 6.8 0 14.1 12.8 2.4 (T*WS) + 2.4 -- -- -- -- ns ns ns ns ns ns -4.4 1 (T*WS)+1 -- ns ns ns Min Max Unit
1. Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and T = Clock Period. For 80MHz operation, T = 12.5ns. 2. Parameters listed are guaranteed by design. To calculate the required access time for an external memory for any frequency < 80MHz, use this formula: Top = Clock period @ desired operating frequency WS = Number of wait states Memory Access Time = (Top*WS) + (Top- 11.5)
A0-A15, PS, DS (See Note)
tARDA
tARDD tRDA tRDRD
RD
tAWR tWRWR tWR tWRRD
tRD
tRDWR
WR
tWRD tDOS tAD tDOH
tRDD tDRD
D0-D15
Data Out
Data In
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Figure 13. External Bus Asynchronous Timing
28
DSP56F807 Technical Data
MOTOROLA
Reset, Stop, Wait, Mode Select, and Interrupt Timing
3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
,5
Table 30. Reset, Stop, Wait, Mode Select, and Interrupt Timing1,5
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF
Characteristic RESET Assertion to Address, Data and Control Signals High Impedance Minimum RESET Assertion Duration2 OMR Bit 6 = 0 OMR Bit 6 = 1 RESET De-assertion to First External Address Output Edge-sensitive Interrupt Request Width IRQA, IRQB Assertion to External Data Memory Access Out Valid, caused by first instruction execution in the interrupt service routine IRQA, IRQB Assertion to General Purpose Output Valid, caused by first instruction execution in the interrupt service routine IRQA Low to First Valid Interrupt Vector Address Out recovery from Wait State3 IRQA Width Assertion to Recover from Stop State4 Delay from IRQA Assertion to Fetch of first instruction (exiting Stop) OMR Bit 6 = 0 OMR Bit 6 = 1 Duration for Level Sensitive IRQA Assertion to Cause the Fetch of First IRQA Interrupt Instruction (exiting Stop) OMR Bit 6 = 0 OMR Bit 6 = 1 Delay from Level Sensitive IRQA Assertion to First Interrupt Vector Address Out Valid (exiting Stop) OMR Bit 6 = 0 OMR Bit 6 = 1 1. 2. Symbol tRAZ tRA 275,000T 128T tRDA tIRW tIDM 33T 1.5T -- -- -- 34T -- 15T ns ns ns ns ns Figure 14 Figure 15 Figure 16 Min -- Max 21 Unit ns See Figure Figure 14 Figure 14
tIG
--
16T
ns
Figure 16
tIRI tIW tIF
--
13T
ns
Figure 17
--
2T
ns
Figure 18 Figure 18
-- -- tIRQ -- -- tII -- --
275,000T 12T
ns ns Figure 19
275,000T 12T
ns ns Figure 19
275,000T 12T
ns ns
In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5 ns. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases: * After power-on reset * When recovering from Stop state 3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted. 4. The interrupt instruction fetch is visible on the pins only in Mode 3. 5. Parameters listed are guaranteed by design.
MOTOROLA
DSP56F807 Technical Data
29
RESET tRA
tRAZ
tRDA
A0-A15, D0-D15 PS, DS, RD, WR
First Fetch
First Fetch
Figure 14. Asynchronous Reset Timing
IRQA, IRQB
tIRW
Figure 15. External Interrupt Timing (Negative-Edge-Sensitive)
A0-A15,
PS, DS, RD, WR tIDM IRQA, IRQB
First Interrupt Instruction Execution
a) First Interrupt Instruction Execution
General Purpose I/O Pin
tIG IRQA, IRQB
b) General Purpose I/O
Figure 16. External Level-Sensitive Interrupt Timing
IRQA, IRQB
tIRI
A0-A15, PS, DS, RD, WR
First Interrupt Vector Instruction Fetch
Figure 17. Interrupt from Wait State Timing
30 DSP56F807 Technical Data MOTOROLA
Serial Peripheral Interface (SPI) Timing
tIW
IRQA
tIF
A0-A15, PS, DS, RD, WR
First Instruction Fetch Not IRQA Interrupt Vector
Figure 18. Recovery from Stop State Using Asynchronous Interrupt Timing
tIRQ
IRQA
tII
A0-A15 PS, DS, RD, WR
First IRQA Interrupt Instruction Fetch
Figure 19. Recovery from Stop State Using IRQA Interrupt Service
3.8 Serial Peripheral Interface (SPI) Timing
Table 31. SPI Timing1
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fOP = 80MHz
Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high time Master Slave Clock (SCK) low time Master Slave Data setup time required for inputs Master Slave Symbol tC 50 25 tELD -- 25 tELG -- 100 tCH 17.6 12.5 tCL 24.1 25 tDS 20 0 -- -- ns ns -- -- ns ns Figures 20, 21, 22, 23 -- -- ns ns -- -- ns ns Figures 20, 21, 22, 23 -- -- ns ns Figure 23 -- -- ns ns Figure 23 Min Max Unit See Figure Figures 20-23
Figure 23
MOTOROLA
DSP56F807 Technical Data
31
Table 31. SPI Timing1 (Continued)
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fOP = 80MHz
Data hold time required for inputs Master Slave Access time (time to data active from highimpedance state) Slave Disable time (hold time to high-impedance state) Slave Data Valid for outputs Master Slave (after enable edge) Data invalid Master Slave Rise time Master Slave Fall time Master Slave 1. Parameters listed are guaranteed by design. tDH 0 2 tA 4.8 tD 3.7 tDV -- -- tDI 0 0 tR -- -- tF -- -- 9.7 9.0 ns ns 11.5 10.0 ns ns -- -- ns ns 4.5 20.4 ns ns 15.2 ns Figures 20, 21, 22, 23 15 ns Figure 23 -- -- ns ns Figures 20, 21, 22, 23
Figure 23
Figures 20, 21, 22, 23
Figures 20, 21, 22, 23
Figures 20, 21, 22, 23
32
DSP56F807 Technical Data
MOTOROLA
Serial Peripheral Interface (SPI) Timing
SS
(Input)
SS is held High on master
tC tR tCL tCH tF tR tF
SCLK (CPOL = 0) (Output)
SCLK (CPOL = 1) (Output)
tDH tDS
tCL
tCH
MISO (Input)
MSB in
tDI
Bits 14-1
tDV
LSB in
tDI(ref)
MOSI (Output)
Master MSB out
tF
Bits 14-1
Master LSB out
tR
Figure 20. SPI Master Timing (CPHA = 0)
SS
(Input)
SS is held High on master
tC tCL tF tR
SCLK (CPOL = 0) (Output)
tCH
tF
SCLK (CPOL = 1) (Output)
tCL tCH tR tDS tDH
MISO (Input)
tDV(ref)
MSB in
tDI
Bits 14-1
tDV
LSB in
tDI(ref)
MOSI (Output)
Master MSB out
tF
Bits 14- 1
Master LSB out
tR
Figure 21. SPI Master Timing (CPHA = 1)
MOTOROLA
DSP56F807 Technical Data
33
SS
(Input)
tC tCL tF tR tELG
SCLK (CPOL = 0) (Input)
tELD
tCH tCL
SCLK (CPOL = 1) (Input)
tA tCH tR tF tD
MISO (Output)
tDS
Slave MSB out
Bits 14-1
tDV tDH
Slave LSB out
tDI tDI
MOSI (Input)
MSB in
Bits 14-1
LSB in
Figure 22. SPI Slave Timing (CPHA = 0)
SS
(Input)
tC tF tCL tCH tELD tCL tR
SCLK (CPOL = 0) (Input)
tELG
SCLK (CPOL = 1) (Input)
tDV tA
tCH tF
tR tD
MISO (Output)
tDS
Slave MSB out
Bits 14-1
tDV tDH
Slave LSB out
tDI
MOSI (Input)
MSB in
Bits 14-1
LSB in
Figure 23. SPI Slave Timing (CPHA = 1)
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DSP56F807 Technical Data
MOTOROLA
Quad Timer Timing
3.9 Quad Timer Timing
Table 32. Timer Timing1, 2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fOP = 80MHz
Characteristic Timer input period Timer input high/low period Timer output period Timer output high/low period 1. 2. Symbol PIN PINHL POUT POUTHL Min 4T + 6 2T + 3 2T 1T Max -- -- -- -- Unit ns ns ns ns
In the formulas listed, T = the clock cycle. For 80MHz operation, T = 12.5 ns. Parameters listed are guaranteed by design.
Timer Inputs
PIN PINHL PINHL
Timer Outputs
POUT POUTHL POUTHL
Figure 24. Timer Timing
3.10 Quadrature Decoder Timing
Table 33. Quadrature Decoder Timing1, 2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fOP = 80MHz
Characteristic Quadrature input period Quadrature input high/low period Quadrature phase period Symbol PIN PHL PPH Min 8T + 12 4T + 6 2T + 3 Max -- -- -- Unit ns ns ns
1. In the formulas listed, T = the clock cycle. For 80MHz operation, T=12.5 ns. VSS = 0 V, VDD = 3.0-3.6 V, TA = -40 to +85C, CL 50pF. 2. Parameters listed are guaranteed by design.
MOTOROLA
DSP56F807 Technical Data
35
PPH
PPH
PPH
PPH
Phase A (Input)
PHL PIN PHL
Phase B (Input)
PHL PIN PHL
Figure 25. Quadrature Decoder Timing
3.11 Serial Communication Interface (SCI) Timing
Table 34. SCI Timing4
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fOP = 80MHz
Characteristic Baud Rate1 RXD2 Pulse Width TXD3 Pulse Width 1. 2. 3. 4. Symbol BR RXDPW TXDPW Min Max (fMAX*2.5)/(80) 1.04/BR 1.04/BR Unit Mbps ns ns
--
0.965/BR 0.965/BR
fMAX is the frequency of operation of the system clock in MHz. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. Parameters listed are guaranteed by design.
RXD SCI receive data pin (Input)
RXDPW
Figure 26. RXD Pulse Width
TXD SCI receive data pin (Input)
TXDPW
Figure 27. TXD Pulse Width
36
DSP56F807 Technical Data
MOTOROLA
Analog-to-Digital Converter (ADC) Characteristics
3.12 Analog-to-Digital Converter (ADC) Characteristics
Table 35. ADC Characteristics
performance), ADC clock = 4MHz, 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fOP = 80MHz Characteristic ADC input voltages Resolution Integral Non-Linearity3 Differential Non-Linearity Monotonicity ADC internal clock5 Conversion range Conversion time Sample time Input capacitance Gain Error (transfer gain)5 Total Harmonic Distortion5 Offset Voltage5 Signal-to-Noise plus Distortion5 Effective Number of Bits5 Spurious Free Dynamic Range5 Bandwidth ADC Quiescent Current (each dual ADC) VREF Quiescent Current (each dual ADC) fADIC RAD tADC tADS CADI EGAIN THD VOFFSET SINAD ENOB SFDR BW IADC IVREF 0.5 VSSA -- -- -- 0.93 60 -90 55 9 65 -- -- -- Symbol VADCIN RES INL DNL Min 01 12 -- -- Typ -- -- +/- 2.5 +/- 0.9 GUARANTEED -- -- 6 1 5 1.00 64 -25 60 10 70 100 50 12 5 VDDA -- -- -- 1.08 -- +10 -- -- -- -- -- 16.5 mV -- bit dB KHz mA mA MHz V tAIC cycles6 tAIC cycles6 pF6 --
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, VREF = VDD-0.3V, ADCDIV = 4, 9, or 14, (for optimal
Max VREF2 12 +/- 4 +/- 1 Unit V Bits LSB4 LSB4
1. For optimum ADC performance, keep the minimum VADCIN value > 25mV. Inputs less than 25mV may convert to a digital output code of 0. 2. VREF must be equal to or less than VDDA and must be greater than 2.7V. For optimal ADC performance, set VREF to VDDA-0.3V.
3.
4. 5.
Measured in 10-90% range.
LSB = Least Significant Bit. Guaranteed by characterization.
6.
tAIC = 1/fADIC
MOTOROLA
DSP56F807 Technical Data
37
.
ADC analog input
3
1
2
4
Figure 28. Equivalent Analog Input Circuit
1. 2. 3. 4. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf) Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf) Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms) Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is only connected to it at sampling time. (1pf)
3.13 Controller Area Network (CAN) Timing
Table 36. CAN Timing2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, MSCAN Clock = 30MHz
Characteristic Baud Rate Bus Wakeup detection 1 Symbol BRCAN T WAKEUP Min Max 1 Unit Mbps s
--
5
--
1. If Wakeup glitch filter is enabled during the design initialization and also CAN is put into SLEEP mode then, any bus event (on MSCAN_RX pin) whose duration is less than 5 microseconds is filtered away. However, a valid CAN bus wakeup detection takes place for a wakeup pulse equal to or greater than 5 microseconds. The number 5 microseconds originates from the fact that the CAN wakeup message consists of 5 dominant bits at the highest possible baud rate of 1Mbps. 2. Parameters listed are guaranteed by design
MSCAN_RX CAN receive data pin (Input)
T WAKEUP
Figure 29. Bus Wakeup Detection
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DSP56F807 Technical Data
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JTAG Timing
3.14 JTAG Timing
Table 37. JTAG Timing1, 3
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fOP = 80MHz
Characteristic TCK frequency of operation2 TCK cycle time TCK clock pulse width TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO tri-state TRST assertion time DE assertion time Symbol fOP tCY tPW tDS tDH tDV tTS tTRST tDE Min DC 100 50 0.4 1.2 -- -- 50 4T Max 10 -- -- -- -- 26.6 23.5 -- -- Unit MHz ns ns ns ns ns ns ns ns
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz operation, T = 12.5ns. 2. TCK frequency of operation must be less than 1/8 the processor rate. 3. Parameters listed are guaranteed by design.
tCY tPW
VIH
tPW
VM
TCK (Input) VM = VIL + (VIH - VIL)/2
VM VIL
Figure 30. Test Clock Input Timing Diagram
MOTOROLA
DSP56F807 Technical Data
39
TCK (Input)
tDS tDH
TDI TMS (Input) TDO (Output)
Input Data Valid
tDV
Output Data Valid
tTS
TDO (Output)
tDV
TDO (Output)
Output Data Valid
Figure 31. Test Access Port Timing Diagram
TRST
(Input)
tTRST
Figure 32. TRST Timing Diagram
DE tDE
Figure 33. OnCE--Debug Event
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DSP56F807 Technical Data
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Package and Pin-Out Information DSP56F807
Part 4 Packaging
4.1 Package and Pin-Out Information DSP56F807
This section contains package and pin-out information for the DSP56F807. This device comes in two case types: low-profile quad flat pack (LQFP) or mold array process ball grid assembly (MAPBGA). Figure 34 shows the package outline for the LQFP case, Figure 35 shows the mechanical parameters for the LQFP case, and Table 38 lists the pinout for the LQFP case. Figure 36 shows the mechanical parameters for the MAPBGA case, and Table 39 lists the pinout for the MAPBGA package.
RXD0 TXD0 CLK0 VSS VPP HOME1 INDX1 VDD PHB1 PHA1 HOME0 INDX0 PHB0 PHA0 MOSI MISO SCLK SS MSCAN_RX VSS VDD MSCAN_TX VCAPC2 TDO TDI TMS TCK TCS TRST TC1 TC0 TD3 TD2 TD1 TD0 ISA2 ISA1 ISA0 VSS DE
A0 A1 A2 A3 A4 A5 A6 A7 VDD A8 A9 A10 A11 A12 A13 A14 A15 VSS PS DS WR RD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 VDD D11 D12 D13 D14 D15 GPIOB0
ORIENTATION MARK
121
PIN 1
Motorola DSP56F807
81 41
ANB7 ANB6 ANB5 ANB4 ANB3 ANB2 ANB1 ANB0 VSSA VDDA VREF2 ANA7 ANA6 ANA5 ANA4 ANA3 ANA2 ANA1 ANA0 VSSA VDDA VREF RESET RSTO VDD VSS VDD EXTAL XTAL VSS VSS VDD VDDA VSSA EXTBOOT FAULTA3 FAULTA2 FAULTA1 FAULTA0 PWMA5
Figure 34. Top View, DSP56F807 160-pin LQFP Package
MOTOROLA
GPIOB1 GPIOB2 GPIOB3 GPIOB4 GPIOB5 GPIOB6 GPIOB7 VSS GPIOD0 GPIOD1 GPIOD2 GPIOD3 GPIOD4 GPIOD5 TXD1 RXD1 PWMB0 PWMB1 PWMB2 PWMB3 PWMB4 PWMB5 VDD ISB0 VCAPC1 ISB1 ISB2 VPP2 IRQA IRQB FAULTB0 FAULTB1 FAULTB2 FAULTB3 PWMA0 VSS PWMA1 PWMA2 PWMA3 PWMA4
DSP56F807 Technical Data
41
160X
0.20 C A-B D D 6 D 2 GG D c b
(b) A B SECTION G-G
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B, AND D TO BE DETERMINED WHERE THE LEADS EXIT THE PLASTIC BODY AT DATUM PLANE H. 4. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25mm PER SIDE. DIMENSIONS D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08mm. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN A PROTRUSION AND AN ADJACENT LEAD IS 0.07mm. 6. EXACT SHAPE OF CORNERS MAY VARY.
D1 2 D1 DETAIL F
4X
0.20 H A-B D
156X
C
SEATING PLANE
4X
e e/2
160X
E1 2
E 2
0.08 C e
M MILLIMETERS DIM MIN MAX A --1.60 A1 0.05 0.15 A2 1.35 1.45 b 0.17 0.27 b1 0.17 0.23 c 0.09 0.20 c1 0.09 0.16 D 26.00 BSC D1 24.00 BSC e 0.50 BSC E 26.00 BSC E1 24.00 BSC L 0.45 0.75 L1 1.00 REF R1 0.08 --R2 0.08 0.20 S 0.20 -- 0 7 1 0 --2 11 13 3 11 13
0.08
2 1
C A-B D
H
A2
A
R1 R2
3
A1
0.25
GAGE PLANE
S L (L1) DETAIL F
CASE 1259-01 ISSUE O
Figure 35. 160-pin LQFP Mechanical Information
E1
E
c1
42
DSP56F807 Technical Data
MOTOROLA
Package and Pin-Out Information DSP56F807
Table 38. DSP56F807 LQFP Package Pin Identification by Pin Number
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Signal Name A0 A1 A2 A3 A4 A5 A6 A7 VDD Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 Signal Name GPIOB1 GPIOB2 GPIOB3 GPIOB4 GPIOB5 GPIOB6 GPIOB7 VSS GPIOD0 GPIOD1 GPIOD2 GPIOD3 GPIOD4 GPIOD5 TXD1 RXD1 PWMB0 PWMB1 PWMB2 PWMB3 PWMB4 PWMB5 VDD ISB0 VCAPC1 ISB1 ISB2 Pin No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 Signal Name PWMA5 FAULTA0 FAULTA1 FAULTA2 FAULTA3 EXTBOOT VSSA VDDA VDD VSS VSS XTAL EXTAL VDD VSS VDD RSTO RESET VREF VDDA VSSA ANA0 ANA1 ANA2 ANA3 ANA4 ANA5 Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 Signal Name DE VSS ISA0 ISA1 ISA2 TD0 TD1 TD2 TD3 TC0 TC1 TRST TCS TCK TMS TDI TDO VCAPC2 MSCAN_TX VDD VSS MSCAN_RX SS SCLK MISO MOSI PHA0
A8
A9 A10 A11 A12 A13 A14 A15 VSS PS DS WR RD D0 D1 D2 D3 D4
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DSP56F807 Technical Data
43
Table 38. DSP56F807 LQFP Package Pin Identification by Pin Number (Continued)
Pin No. 28 29 30 31 32 33 34 35 36 37 38 39 40 Signal Name D5 D6 D7 D8 D9 D10 VDD D11 D12 D13 D14 D15 GPIOB0 Pin No. 68 69 70 71 72 73 74 75 76 77 78 79 80 Signal Name VPP2 IRQA IRQB FAULTB0 FAULTB1 FAULTB2 FAULTB3 PWMA0 VSS PWMA1 PWMA2 PWMA3 PWMA4 Pin No. 108 109 110 111 112 113 114 115 116 117 118 119 120 Signal Name ANA6 ANA7 VREF2 VDDA VSSA ANB0 ANB1 ANB2 ANB3 ANB4 ANB5 ANB6 ANB7 Pin No. 148 149 150 151 152 153 154 155 156 157 158 159 160 Signal Name PHB0 INDX0 HOME0 PHA1 PHB1 VDD INDX1 HOME1 VPP VSS CLKO TXD0 RXD0
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DSP56F807 Technical Data
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Package and Pin-Out Information DSP56F807
X Y
D
LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA
M K
E
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE.
0.20
13X
e
METALIZED MARK FOR PIN 1 IDENTIFICATION IN THIS AREA A B C
S
14 13 12 11 10 9 6 5 4 3 2 1
MILLIMETERS DIM MIN MAX A 1.32 1.75 A1 0.27 0.47 A2 1.18 REF b 0.35 0.65 D 15.00 BSC E 15.00 BSC e 1.00 BSC S 0.50 BSC
S
13X
D E F G H J K L M N 160X
5 A A2 0.30 Z
e
A1
Z
4
0.15 Z
ROTATED 90 CLOCKWISE
DETAIL K
3
160X
P
b 0.30 Z X Y 0.10 Z VIEW M-M
CASE 1268-01 ISSUE O DATE 04/06/98
Figure 36. 160 MAPBGA Mechanical Information
MOTOROLA
DSP56F807 Technical Data
45
Table 39. 160 MAPBGA Package Pin Identification by Pin Number
Solder Ball
C3 B2 D3 C2 B1 D2 C1 D1 E3 E2 E1 F3 F2 F1 G3 G2 G1 F4 G4 H4 J4 K4 P1 N3 P2 P3
Signal Name
A0 A1 A2 A3 A4 A5 A6 A7
Solder Ball
N4 P4 M4 L5 N5 P5 K5 N6 L6 K6 P6 N7 L7 P7 K7 L8 K8 P8 L9 N8 P14 M13 L12 N14 L13 M14
Signal Name
GPIOB5 GPIOB6 GPIOB7
Solder Ball
K12 K13 L14 K11 K14 J13 J12 J14 J11 H13 H12 H14 H11 G12 G11 G14 B13 A14 B12 A13 A12 B11 A11 D10 B10 A10
Signal Name VSSA VDDA VDD VSS VSS
XTAL EXTAL
Solder Ball
E10 D9 B9 E9 A9 D8 B8 A8 E8 D7 E7 D6 H1 H2 J3 J1 J2 K3 K1 L1 K2 L3 M1 L2 N1 M2
Signal Name
TC1 TRST TCS TCK TMS TDI TDO VCAPC2 MSCAN_TX
VSS
GPIOD0 GPIOD1 GPIOD2 GPIOD3 GPIOD4 GPIOD5 TXD1 RXD1 PWMB0 PWMB1 PWMB2 PWMB3 PWMB4 PWMB5
VDD VSS
VDD RSTO RESET VREF
VDD
A8 A9 A10 A11 A12 A13 A14 A15
VDD VSS
MSCAN_RX D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
VDDA VSSA
ANA0 DE
VSS
PS DS WR RD GPIOB1 GPIOB2 GPIOB3 GPIOB4
VSS
ISA0 ISA1 ISA2 TD0 TD1 TD2 TD3 TC0
VDD
ISB0 PWMA5 FAULTA0 FAULTA1 FAULTA2 FAULTA3 EXTBOOT
VDD
D11 D12 D13
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DSP56F807 Technical Data
MOTOROLA
Package and Pin-Out Information DSP56F807
Table 39. 160 MAPBGA Package Pin Identification by Pin Number (Continued)
Solder Ball
N2 M3 L4 K10 K9 P9 L10 N9 P10 P11 N10 L11 M11 P12
Signal Name
D14 D15 GPIOB0 VCAPC1 ISB1 ISB2 VPP2 IRQA IRQB FAULTB0 FAULTB1 FAULTB2 FAULTB3 PWMA0
Solder Ball
N11 P13 N12 N13 M12 F11 G13 F12 F14 E11 F13 E12 E14 E13
Signal Name VSS
PWMA1 PWMA2 PWMA3 PWMA4 ANA1 ANA2 ANA3 ANA4 ANA5 ANA6 ANA7 VREF2
Solder Ball
D14 D11 D12 D13 C14 C13 C11 B14 C12 A7 E5 B7 A6 E6
Signal Name VSSA
ANA8 ANA9 ANA10 ANA11 ANA12 ANA13 ANA14 ANA15 SS SCLK MISO MOSI PHA0
Solder Ball
D5 B6 A5 E4 B5 A4 D4 C4 B4 A2 B3 A1 A3 H3
Signal Name
PHB0 INDX0 HOME0 PHA1 PHB1
VDD
INDX1 HOME1 VPP CLKO TXD0 RXD0
VSS
D0
VDDA
MOTOROLA
DSP56F807 Technical Data
47
Part 5 Design Considerations
5.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, in C can be obtained from the equation: Equation 1: Where: TA = ambient temperature C RJA = package junction-to-ambient thermal resistance C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2:
RJA = RJC + R CA TJ = T A + ( P D x R JA )
Where: RJA = package junction-to-ambient thermal resistance C/W RJC = package junction-to-case thermal resistance C/W RCA = package case-to-ambient thermal resistance C/W RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. Definitions: A complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages: * Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation across the surface. Measure the thermal resistance from the junction to where the leads are attached to the case. This definition is approximately equal to a junction to board thermal resistance. Use the value obtained by the equation (TJ - TT)/PD where TT is the temperature of the package case determined by a thermocouple.
* *
48
DSP56F807 Technical Data
MOTOROLA
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance.
5.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
Use the following list of considerations to assure correct DSP operation: * * Provide a low-impedance path from the board power supply to each VDD pin on the DSP, and from the board ground to each VSS pin. The minimum bypass requirement is to place 0.1 F capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the VDD/VSS pairs, including VDDA/VSSA. The VCAP capacitors must be low ESR capacitors, such as ceramic or tantalum. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS pins are less than 0.5 inch per capacitor lead. Bypass the VDD and VSS layers of the PCB with approximately 100 F, preferably with a highgrade capacitor such as a tantalum capacitor. Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSScircuits. Take special care to minimize noise levels on the VREF, VDDA and VSSA pins.
* * * *
*
49
DSP56F807 Technical Data
MOTOROLA
*
Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means to assert TRST independently of RESET. TRST must be asserted at power up for proper operation. Designs that do not require debugging functionality, such as consumer products, TRST should be tied low. Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an interface to this port to allow in-circuit Flash programming.
*
50
DSP56F807 Technical Data
MOTOROLA
Electrical Design Considerations
Part 6 Ordering Information
Table 40 lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales office or authorized distributor to determine availability and to order parts.
Table 40. DSP56F807 Ordering Information
Part DSP56F807 DSP56F807 Supply Voltage 3.0-3.6 V 3.0-3.6 V Package Type Low-Profile Quad Flat Pack (LQFP) Mold Array Process Ball Grid Array (MAPBGA) Pin Count 160 160 Frequency (MHz) 80 80 Order Number DSP56F807PY80 DSP56F807VF80
MOTOROLA
DSP56F807 Technical Data
51
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. (c) Motorola, Inc. 2002. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors/
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